1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#pragma once 14#include <stdint.h> 15#include <platsupport/plat/clock_indexes.h> 16 17/* Register information sourced from "NVIDIA Tegra K1 Mobile Processor TECHNICAL REFERENCE MANUAL" */ 18 19#define TK1_CLKCAR_PADDR 0x60006000 20#define TK1_CLKCAR_SIZE (0x1000) 21 22#define PLLC_START 0x80 23#define PLLC_END 0x90 24#define PLLM_START 0x90 25#define PLLM_END 0xa0 26#define PLLP_START 0xa0 27#define PLLP_END 0xb0 28#define PLLA_START 0xb0 29#define PLLA_END 0xc0 30#define PLLU_START 0xc0 31#define PLLU_END 0xd0 32#define PLLD_START 0xd0 33#define PLLD_END 0xe0 34#define PLLX_START 0xe0 35#define PLLX_END 0xe8 36#define PLLE_START 0xe8 37#define PLLE_END 0xf0 38#define DFLL_BASE_0 0x2f4 39#define PLLE_AUX_0 0x48c 40#define PLLD2_START 0x4b8 41#define PLLD2_END 0x4c0 42#define PLLREFE_START 0x4c4 43#define PLLREFE_END 0x4d0 44#define PLLC2_START 0x4e8 45#define PLLC2_END 0x4fc 46#define PLLC3_START 0x4fc 47#define PLLC3_END 0x510 48#define PLLX_1_START 0x510 49#define PLLX_1_END 0x51c 50#define PLLE_AUX1_0 0x524 51#define PLLP_RESHIFT_0 0x528 52#define PLLU_HW_PWRDN_CFG0_0 0x530 53#define PLLX_2_START 0x548 54#define PLLX_2_END 0x554 55#define PLLD2_1_START 0x570 56#define PLLD2_1_END 0x57c 57#define PLLDP_START 0x590 58#define PLLDP_END 0x5a4 59#define PLLC4_START 0x5a4 60#define PLLC4_END 0x5b8 61#define PLLP_1_START 0x67c 62#define PLLP_1_END 0x684 63 64/* These are the input clk sources to the CAR module */ 65enum ext_clk_input_sources { 66 PMIC, 67 OSC, 68}; 69 70enum clk_id { 71 NCLOCKS 72}; 73 74/* These are PLL clks that use the input clk sources. */ 75enum clk_sources { 76 PLLM, 77 PLLX, 78 PLLC, 79 PLLC2, 80 PLLC3, 81 PLLC4, 82 PLLP, 83 PLLA, 84 PLLU, 85 PLLD, 86 PLLD2, 87 refPLLe, 88 PLLE, 89 PLLDP, 90 DFLLCPU, 91 GPCPLL 92}; 93 94/* Primary clocks */ 95enum primary_clk_srcs { 96 dbg_oscout, 97 ck32khz_IB, 98 osc_div_clk, 99 car_sclk, 100 clk_m, 101 car_clk_m, 102 dfllCPU_out, 103 pllC_out, 104 pllC2_out, 105 pllC3_out, 106 pllC4_out, 107 pllM_out, 108 int_pllA_out, 109 pllD_out, 110 pllD2_out, 111 pllDP_out, 112 pllU, 113 refPLLE_out, 114 pllE_out0, 115 pllP_out, 116 pllX, 117 //GPCPLL, 118 clk_s, 119 car_clk_s, 120}; 121 122/* These go through a NV divider */ 123enum derived_clk_srcs { 124 pllC_out1, 125 pllM_out1, 126 pllP_out1, 127 pllP_out2, 128 pllP_out3, 129 pllP_out4, 130 pllP_out5, 131 pllA_out0, 132}; 133 134/* Source clocks */ 135enum src_clocks { 136 actmon_clk_t, 137 adx0_r_clk, 138 adx1_r_clk, 139 amx0_r_clk, 140 amx1_r_clk, 141 audio_r_clk, 142 cilab_clk_t, 143 cilcd_clk_t, 144 cile_clk_t, 145 clk72mhz_clk, 146 csite_clk_t, 147 dam0_r_clk, 148 dam1_r_clk, 149 dam2_r_clk, 150 display_clk_t, 151 displayb_clk_t, 152 dsia_lp_clk_t, 153 dsib_lp_clk_t, 154 dvfs_ref_r_clk, 155 dvfs_soc_r_clk, 156 emc_dll_clk_t, 157 emc_latency_clk_t, 158 entropy_r_clk, 159 extperiph1_clk, 160 extperiph2_clk, 161 extperiph3_clk, 162 hda_r_clk, 163 hdmi_audio_clk_t, 164 hdmi_clk_t, 165 host1x_clk_t, 166 hsi_clk_t, 167 i2c1_r_clk, 168 i2c2_r_clk, 169 i2c3_r_clk, 170 i2c4_r_clk, 171 i2c5_r_clk, 172 i2c6_r_clk, 173 i2c_slow_clk, 174 i2s0_r_clk, 175 i2s1_r_clk, 176 i2s2_r_clk, 177 i2s3_r_clk, 178 i2s4_r_clk, 179 int_emc_clk, 180 int_hda2codec_2x_clk, 181 isp_r_clk_t, 182 la_clk_t, 183 lvds0_pad_clockin_t, 184 mselect_clk_t, 185 msenc_clk_t, 186 nor_r_clk, 187 owr_r_clk, 188 pex_txclkref, 189 pex_txclkref_grp0, 190 pex_txclkref_grp1, 191 pex_txclkref_grp2, 192 pex_txclkref_tms, 193 pwm_r_clk, 194 sata_oob_clk_t, 195 sclk_sel, 196 sdmmc1_r_clk_t, 197 sdmmc2_r_clk_t, 198 sdmmc3_r_clk_t, 199 sdmmc4_r_clk_t, 200 se_clk_t, 201 soc_therm_t, 202 spdif_in_r_clk, 203 spdif_out_r_clk, 204 spi1_clk_t, 205 spi2_clk_t, 206 spi3_clk_t, 207 spi4_clk_t, 208 spi5_clk_t, 209 spi6_clk_t, 210 sys2hsio_sata_r_clk, 211 traceclkin_clk_t, 212 tsec_clk_t, 213 tsensor_r_clk, 214 uarta_r_clk, 215 uartb_r_clk, 216 uartc_r_clk, 217 uartd_r_clk, 218 vde_clk_t, 219 vfir_clk_t, 220 vi_clk_t, 221 vi_sensor2_clk, 222 vi_sensor_clk, 223 vic_clk_t, 224 xusb_120m_clk, 225 xusb_core_clk, 226 xusb_core_dev_clk, 227 xusb_falcon_clk, 228 xusb_fs_clk, 229 NUM_OTHER_CLOCKS 230}; 231 232/* The TK1 Clock and reset controller frame has lots of registers which can 233 be broken up into the following categories: 234 - CLK_PLL: Registers that controll the PLLs 235 - CLK_ENBRST_DEVICES: Registers for enabling and resetting devices 236 Each device has a reset line and clk enable line 237 - CLK_SOURCE: Source device regisers, one register for each src_clock 238 - CLK_MISC: All other registers. Does things like trimming and processor resets 239 - CLK_RESERVED: No register at memory location 240 */ 241typedef enum clk_register_type { 242 CLK_RESERVED, 243 CLK_PLL, 244 CLK_ENBRST_DEVICES, 245 CLK_SOURCE, 246 CLK_MISC, 247 NUM_REGISTER_TYPES 248} clk_register_type_t; 249 250/* The controller has 6 sets of enable and reset registers. Each device that 251 can be enabled/disabled/reset has a bit in one of these register banks */ 252typedef enum register_bank { 253 REG_L, 254 REG_H, 255 REG_U, 256 REG_V, 257 REG_W, 258 REG_X, 259 NUM_REGISTER_BANKS 260} register_bank_t; 261 262/* The different types of CLK_ENBRST_DEVICES registers */ 263typedef enum register_access_type { 264 ENB_SET, 265 ENB_CLR, 266 ENB_VAL, 267 RST_SET, 268 RST_CLR, 269 RST_VAL, 270 NUM_ACCESS_TYPES 271} register_access_type_t; 272 273struct enbrst_type { 274 register_bank_t rb; 275 register_access_type_t at; 276}; 277 278struct source_type { 279 enum src_clocks clks; 280}; 281 282/* Clock register struct for storing register layout in the device frame. 283 See clk_register_t tk1_clk_registers. */ 284typedef struct clk_register { 285 enum clk_register_type reg_type; 286 union { 287 struct source_type st; 288 struct enbrst_type eb; 289 }; 290} clk_register_t; 291 292extern const clk_register_t tk1_clk_registers[]; 293 294