1/* 2 * Copyright 2014, General Dynamics C4 Systems 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7#include <config.h> 8#include <types.h> 9#include <machine/io.h> 10#include <kernel/vspace.h> 11#include <arch/machine.h> 12#include <arch/kernel/vspace.h> 13#include <plat/machine.h> 14#include <linker.h> 15#include <plat/machine/devices_gen.h> 16#include <plat/machine/hardware.h> 17 18#define TIOCP_CFG_SOFTRESET BIT(1) 19#define TCLR_AUTORELOAD BIT(1) 20#define TCLR_COMPAREENABLE BIT(6) 21#define TCLR_STARTTIMER BIT(0) 22#define TIER_MATCHENABLE BIT(0) 23#define TIER_OVERFLOWENABLE BIT(1) 24 25timer_t *timer = (timer_t *) TIMER_PPTR; 26 27#ifdef CONFIG_KERNEL_MCS 28#define INTCPS_SYSCONFIG_SOFTRESET BIT(1) 29#define INTCPS_SYSSTATUS_RESETDONE BIT(0) 30uint32_t high_bits = 0; 31BOOT_CODE void initTimer(void) 32{ 33 /* Configure gptimer9 as kernel timer */ 34 timer->cfg = TIOCP_CFG_SOFTRESET; 35 36 /* disable */ 37 timer->tclr = 0; 38 39 /* wait for reset */ 40 while (!timer->tistat); 41 42 maskInterrupt(/*disable*/ true, KERNEL_TIMER_IRQ); 43 44 /* Set the reload value */ 45 timer->tldr = 0u; 46 47 /* Enables interrupt on overflow and match */ 48 timer->tier |= (TIER_OVERFLOWENABLE | TIER_MATCHENABLE); 49 50 /* Clear the read register */ 51 timer->tcrr = 0u; 52 53 /* start the timer */ 54 timer->tclr = TCLR_AUTORELOAD | TCLR_STARTTIMER | TCLR_COMPAREENABLE; 55} 56#else /* CONFIG_KERNEL_MCS */ 57#define TIMER_INTERVAL_MS (CONFIG_TIMER_TICK_MS) 58BOOT_CODE void initTimer(void) 59{ 60 /* Configure gptimer9 as kernel timer */ 61 timer->cfg = TIOCP_CFG_SOFTRESET; 62 63 while (!timer->tistat); 64 65 maskInterrupt(/*disable*/ true, KERNEL_TIMER_IRQ); 66 67 /* Set the reload value */ 68 timer->tldr = 0xFFFFFFFFUL - TIMER_RELOAD; 69 70 /* Enables interrupt on overflow */ 71 timer->tier = TIER_OVERFLOWENABLE; 72 73 /* Clear the read register */ 74 timer->tcrr = 0xFFFFFFFFUL - TIMER_RELOAD; 75 76 /* Set autoreload and start the timer */ 77 timer->tclr = TCLR_AUTORELOAD | TCLR_STARTTIMER; 78} 79#endif /* !CONFIG_KERNEL_MCS */ 80