1/*
2 * Copyright 2014, General Dynamics C4 Systems
3 *
4 * This software may be distributed and modified according to the terms of
5 * the GNU General Public License version 2. Note that NO WARRANTY is provided.
6 * See "LICENSE_GPLv2.txt" for details.
7 *
8 * @TAG(GD_GPL)
9 */
10
11#ifndef __PLAT_MACHINE_HARDWARE_H
12#define __PLAT_MACHINE_HARDWARE_H
13
14#include <config.h>
15#include <basic_types.h>
16#include <linker.h>
17#include <plat/machine.h>
18#include <plat/machine/devices.h>
19#include <arch/benchmark_overflowHandler.h>
20
21#define physBase          0x00000000
22#define kernelBase        0xe0000000
23
24static const kernel_frame_t BOOT_RODATA kernel_devices[] = {
25    {
26        /*  GIC controller and private timers */
27        MPCORE_PRIV_PADDR,
28        ARM_MP_PPTR1,
29        true  /* armExecuteNever */
30    },
31    {
32        /*  GIC distributor */
33        MPCORE_PRIV_PADDR + BIT(PAGE_BITS),
34        ARM_MP_PPTR2,
35        true  /* armExecuteNever */
36    },
37    {
38        /*  L2CC */
39        L2CC_PL310_PADDR,
40        L2CC_PL310_PPTR,
41        true  /* armExecuteNever */
42#ifdef CONFIG_PRINTING
43    },
44    {
45        /*  UART */
46        UART_PADDR,
47        UART_PPTR,
48        true  /* armExecuteNever */
49#endif /* CONFIG_PRINTING */
50    }
51};
52
53/* Available physical memory regions on platform (RAM) */
54/* NOTE: Regions are not allowed to be adjacent! */
55static const p_region_t BOOT_RODATA avail_p_regs[] = {
56    /* 1 GiB */
57    { /* .start = */ 0x00000000, /* .end = */ 0x40000000 }
58};
59
60static const p_region_t BOOT_RODATA dev_p_regs[] = {
61    { /* .start = */ UART0_PADDR             , /* .end = */ UART0_PADDR              + ( 1 << 12)},
62    { /* .start = */ UART1_PADDR             , /* .end = */ UART1_PADDR              + ( 1 << 12)},
63    { /* .start = */ USB0_PADDR              , /* .end = */ USB0_PADDR               + ( 1 << 12)},
64    { /* .start = */ USB1_PADDR              , /* .end = */ USB1_PADDR               + ( 1 << 12)},
65    { /* .start = */ I2C0_PADDR              , /* .end = */ I2C0_PADDR               + ( 1 << 12)},
66    { /* .start = */ I2C1_PADDR              , /* .end = */ I2C1_PADDR               + ( 1 << 12)},
67    { /* .start = */ SPI0_PADDR              , /* .end = */ SPI0_PADDR               + ( 1 << 12)},
68    { /* .start = */ SPI1_PADDR              , /* .end = */ SPI1_PADDR               + ( 1 << 12)},
69    { /* .start = */ CAN0_PADDR              , /* .end = */ CAN0_PADDR               + ( 1 << 12)},
70    { /* .start = */ CAN1_PADDR              , /* .end = */ CAN1_PADDR               + ( 1 << 12)},
71    { /* .start = */ GPIO_PADDR              , /* .end = */ GPIO_PADDR               + ( 1 << 12)},
72    { /* .start = */ ETH0_PADDR              , /* .end = */ ETH0_PADDR               + ( 1 << 12)},
73    { /* .start = */ ETH1_PADDR              , /* .end = */ ETH1_PADDR               + ( 1 << 12)},
74    { /* .start = */ QSPI_PADDR              , /* .end = */ QSPI_PADDR               + ( 1 << 12)},
75    { /* .start = */ SMC_PADDR               , /* .end = */ SMC_PADDR                + ( 1 << 12)},
76    { /* .start = */ SDIO0_PADDR             , /* .end = */ SDIO0_PADDR              + ( 1 << 12)},
77    { /* .start = */ SDIO1_PADDR             , /* .end = */ SDIO1_PADDR              + ( 1 << 12)},
78    { /* .start = */ SMC_NAND_PADDR          , /* .end = */ SMC_NAND_PADDR           + (16 << 20)},
79    { /* .start = */ SMC_NOR0_PADDR          , /* .end = */ SMC_NOR0_PADDR           + (32 << 20)},
80    { /* .start = */ SMC_NOR1_PADDR          , /* .end = */ SMC_NOR1_PADDR           + (32 << 20)},
81    { /* .start = */ SMC_SLCR_PADDR          , /* .end = */ SMC_SLCR_PADDR           + ( 1 << 12)},
82    { /* .start = */ TRPL_TIMER0_PADDR       , /* .end = */ TRPL_TIMER0_PADDR        + ( 1 << 12)},
83    { /* .start = */ TRPL_TIMER1_PADDR       , /* .end = */ TRPL_TIMER1_PADDR        + ( 1 << 12)},
84    { /* .start = */ DMAC_S_PADDR            , /* .end = */ DMAC_S_PADDR             + ( 1 << 12)},
85    { /* .start = */ DMAC_NS_PADDR           , /* .end = */ DMAC_NS_PADDR            + ( 1 << 12)},
86    { /* .start = */ SWDT_PADDR              , /* .end = */ SWDT_PADDR               + ( 1 << 12)},
87    { /* .start = */ DDRC_PADDR              , /* .end = */ DDRC_PADDR               + ( 1 << 12)},
88    { /* .start = */ DEVCFG_PADDR            , /* .end = */ DEVCFG_PADDR             + ( 1 << 12)},
89    { /* .start = */ AXI_HP0_PADDR           , /* .end = */ AXI_HP0_PADDR            + ( 1 << 12)},
90    { /* .start = */ AXI_HP1_PADDR           , /* .end = */ AXI_HP1_PADDR            + ( 1 << 12)},
91    { /* .start = */ AXI_HP2_PADDR           , /* .end = */ AXI_HP2_PADDR            + ( 1 << 12)},
92    { /* .start = */ AXI_HP3_PADDR           , /* .end = */ AXI_HP3_PADDR            + ( 1 << 12)},
93    { /* .start = */ OCM_PADDR               , /* .end = */ OCM_PADDR                + ( 1 << 12)},
94    { /* .start = */ EFUSE_PADDR             , /* .end = */ EFUSE_PADDR              + ( 2 << 12)},
95    { /* .start = */ DEBUG_DAP_ROM_PADDR     , /* .end = */ DEBUG_DAP_ROM_PADDR      + ( 1 << 12)},
96    { /* .start = */ DEBUG_ETB_PADDR         , /* .end = */ DEBUG_ETB_PADDR          + ( 1 << 12)},
97    { /* .start = */ DEBUG_CTI_ETB_TPIU_PADDR, /* .end = */ DEBUG_CTI_ETB_TPIU_PADDR + ( 1 << 12)},
98    { /* .start = */ DEBUG_TPIU_PADDR        , /* .end = */ DEBUG_TPIU_PADDR         + ( 1 << 12)},
99    { /* .start = */ DEBUG_FUNNEL_PADDR      , /* .end = */ DEBUG_FUNNEL_PADDR       + ( 1 << 12)},
100    { /* .start = */ DEBUG_ITM_PADDR         , /* .end = */ DEBUG_ITM_PADDR          + ( 1 << 12)},
101    { /* .start = */ DEBUG_CTI_FTM_PADDR     , /* .end = */ DEBUG_CTI_FTM_PADDR      + ( 1 << 12)},
102    { /* .start = */ DEBUG_FTM_PADDR         , /* .end = */ DEBUG_FTM_PADDR          + ( 1 << 12)},
103    { /* .start = */ DEBUG_CPU_PMU0_PADDR    , /* .end = */ DEBUG_CPU_PMU0_PADDR     + ( 1 << 12)},
104    { /* .start = */ DEBUG_CPU_PMU1_PADDR    , /* .end = */ DEBUG_CPU_PMU1_PADDR     + ( 1 << 12)},
105    { /* .start = */ DEBUG_CPU_CTI0_PADDR    , /* .end = */ DEBUG_CPU_CTI0_PADDR     + ( 1 << 12)},
106    { /* .start = */ DEBUG_CPU_CTI1_PADDR    , /* .end = */ DEBUG_CPU_CTI1_PADDR     + ( 1 << 12)},
107    { /* .start = */ DEBUG_CPU_PTM0_PADDR    , /* .end = */ DEBUG_CPU_PTM0_PADDR     + ( 1 << 12)},
108    { /* .start = */ DEBUG_CPU_PTM1_PADDR    , /* .end = */ DEBUG_CPU_PTM1_PADDR     + ( 1 << 12)},
109    { /* .start = */ GPV_TRUSTZONE_PADDR     , /* .end = */ GPV_TRUSTZONE_PADDR      + ( 1 << 12)},
110    { /* .start = */ GPV_QOS301_CPU_PADDR    , /* .end = */ GPV_QOS301_CPU_PADDR     + ( 1 << 12)},
111    { /* .start = */ GPV_QOS301_DMAC_PADDR   , /* .end = */ GPV_QOS301_DMAC_PADDR    + ( 1 << 12)},
112    { /* .start = */ GPV_QOS301_IOU_PADDR    , /* .end = */ GPV_QOS301_IOU_PADDR     + ( 1 << 12)},
113//  { /* .start = */ MPCORE_PRIV_PADDR , /* .end = */ MPCORE_PRIV_PADDR              + ( 1 << 12)},
114//  { /* .start = */ GIC_DIST_PADDR    , /* .end = */ GIC_DIST_PADDR                 + ( 1 << 12)},
115//  { /* .start = */ L2CC_PL310_PADDR  , /* .end = */ L2CC_PL310_PADDR               + ( 1 << 12)},
116    { /* .start = */ QSPI_LINEAR_PADDR , /* .end = */ QSPI_LINEAR_PADDR              + (32 << 20)},
117    { /* .start = */ OCM_HIGH_PADDR    , /* .end = */ OCM_HIGH_PADDR                 + (64 << 12)},
118    /* Programmable logic */
119    { /* .start = */ PL_M_AXI_GP0_PADDR, /* .end = */ PL_M_AXI_GP0_PADDR             + 0x40000000U},
120    { /* .start = */ PL_M_AXI_GP1_PADDR, /* .end = */ PL_M_AXI_GP1_PADDR             + 0x40000000U},
121};
122
123/* Handle a platform-reserved IRQ. */
124static inline void
125handleReservedIRQ(irq_t irq)
126{
127#ifdef CONFIG_ARM_ENABLE_PMU_OVERFLOW_INTERRUPT
128    if (irq == KERNEL_PMU_IRQ) {
129        handleOverflowIRQ();
130    }
131#endif /* CONFIG_ARM_ENABLE_PMU_OVERFLOW_INTERRUPT */
132}
133
134#endif /* !__PLAT_MACHINE_HARDWARE_H */
135