1/* 2 * Copyright 2014, General Dynamics C4 Systems 3 * 4 * This software may be distributed and modified according to the terms of 5 * the GNU General Public License version 2. Note that NO WARRANTY is provided. 6 * See "LICENSE_GPLv2.txt" for details. 7 * 8 * @TAG(GD_GPL) 9 */ 10 11#ifndef __PLAT_MACHINE_DEVICES_H 12#define __PLAT_MACHINE_DEVICES_H 13 14/* These devices are used by the seL4 kernel. */ 15#define UART_PPTR 0xfff01000 16#define TIMER_PPTR 0xfff02000 17#define GIC_DISTRIBUTOR_PPTR 0xfff04000 18#define GIC_CONTROLLER_PPTR 0xfff05000 19#define ARM_DEBUG_MMAPPING_PPTR 0xfff06000 20 21#define GIC_PL390_CONTROLLER_PPTR GIC_CONTROLLER_PPTR 22#define GIC_PL390_DISTRIBUTOR_PPTR GIC_DISTRIBUTOR_PPTR 23 24#define GIC_DISTRIBUTOR_PADDR APCS_QGIC2_PADDR + 0x0000 25#define GIC_CONTROLLER0_PADDR APCS_QGIC2_PADDR + 0x2000 26 27#define UART_PADDR GSBI7_UART_DM_PADDR 28#define TIMER_PADDR APCS_TMR_PADDR 29 30/* Other devices on the SoC */ 31#define RPM_PADDR 0x00000000 /* RPM */ 32#define RPM_TIMERS_PADDR 0x00062000 /* RPM */ 33#define RPM_MSG_RAM_XPU_PADDR 0x00100000 /* RPM */ 34#define MPM_PADDR 0x00200000 /* RPM */ 35#define PA1_SSBI2_CFG_PADDR 0x00300000 /* RPM */ 36#define PA1_XPU_PADDR 0x00400000 /* RPM */ 37#define PA1_SSBI2_CMD_PADDR 0x00500000 /* RPM */ 38#define PA2_SSBI2_CFG_PADDR 0x00600000 /* RPM */ 39#define SEC_CTRL_PADDR 0x00700000 /* Security */ 40#define TLMM_PADDR 0x00800000 /* chip_core_top */ 41#define CLK_CTL_PADDR 0x00900000 /* Clock_Controller */ 42#define EBI1_CH0_PADDR 0x00A00000 /* LPDDR */ 43#define SYS_IMEM_PADDR 0x00B00000 /* chip_core_top */ 44#define PA2_SSBI2_CMD_PADDR 0x00C00000 /* RPM */ 45#define EBI1_CH1_PADDR 0x00D00000 /* LPDDR */ 46#define SFPB_WRAPPER_XPU_PADDR 0x00E00000 /* SFPB_Wrapper */ 47#define SFPB_WRAPPER_PADDR 0x00F00000 /* SFPB_Wrapper */ 48#define SPDM_PADDR 0x01000000 /* chip_core_top */ 49#define SPDM_SECURE_PADDR 0x01100000 /* chip_core_top */ 50#define SFPB_WRAPPER_MUTEX_PADDR 0x01200000 /* SFPB_Wrapper */ 51#define SFAB_PADDR 0x01300000 /* Fabrics */ 52#define AFAB_PADDR 0x01400000 /* Fabrics */ 53#define DAY_CFG_PADDR 0x01500000 /* Fabrics */ 54#define SFPB_WRAPPER_1x2_PADDR 0x01600000 /* SFPB_Wrapper */ 55#define SFPB_WRAPPER_2x1_PADDR 0x01800000 /* SFPB_Wrapper */ 56#define QDSS_DAPROM_PADDR 0x01A00000 /* Debug_Sub_System */ 57#define QDSS_ETB_PADDR 0x01A01000 /* Debug_Sub_System */ 58#define QDSS_CTI1_PADDR 0x01A02000 /* Debug_Sub_System */ 59#define QDSS_TPIU_PADDR 0x01A03000 /* Debug_Sub_System */ 60#define QDSS_TFUNNEL_PADDR 0x01A04000 /* Debug_Sub_System */ 61#define QDSS_ITM_PADDR 0x01A05000 /* Debug_Sub_System */ 62#define QDSS_STM_PADDR 0x01A06000 /* Debug_Sub_System */ 63#define QDSS_DAPM2VMT_PADDR 0x01A80000 /* Debug_Sub_System */ 64#define APCS_QGIC2_PADDR 0x02000000 /* KraitMP_Sub_System */ 65#define APCS_ACC_PADDR 0x02008000 /* KraitMP_Sub_System */ 66#define APCS_SAW2_PADDR 0x02009000 /* KraitMP_Sub_System */ 67#define APCS_TMR_PADDR 0x0200A000 /* KraitMP_Sub_System */ 68#define PCS_GLB_PADDR 0x02010000 /* KraitMP_Sub_System */ 69#define APCS_GCC_PADDR 0x02011000 /* KraitMP_Sub_System */ 70#define APCS_L2_GDHS_PADDR 0x02012000 /* KraitMP_Sub_System */ 71#define APCS_L2_MPU_PADDR 0x02013000 /* KraitMP_Sub_System */ 72#define CPU0_APCS_ACC_PADDR 0x02088000 /* KraitMP_Sub_System */ 73#define CPU0_APCS_SAW2_PADDR 0x02089000 /* KraitMP_Sub_System */ 74#define CPU0_APCS_TMR_PADDR 0x0208A000 /* KraitMP_Sub_System */ 75#define EXT_APCS_GLB_PADDR 0x02090000 /* KraitMP_Sub_System */ 76#define EXT_APCS_GCC_PADDR 0x02091000 /* KraitMP_Sub_System */ 77#define EXT_APCS_L2_GDHS_PADDR 0x02092000 /* KraitMP_Sub_System */ 78#define EXT_APCS_L2_MPU_PADDR 0x02093000 /* KraitMP_Sub_System */ 79#define CPU1_APCS_ACC_PADDR 0x02098000 /* KraitMP_Sub_System */ 80#define CPU1_APCS_SAW2_PADDR 0x02099000 /* KraitMP_Sub_System */ 81#define CPU1_APCS_TMR_PADDR 0x0209A000 /* KraitMP_Sub_System */ 82#define CPU2_APCS_ACC_PADDR 0x020A8000 /* KraitMP_Sub_System */ 83#define CPU2_APCS_SAW2_PADDR 0x020A9000 /* KraitMP_Sub_System */ 84#define CPU2_APCS_TMR_PADDR 0x020AA000 /* KraitMP_Sub_System */ 85#define CPU3_APCS_ACC_PADDR 0x020B8000 /* KraitMP_Sub_System */ 86#define CPU3_APCS_SAW2_PADDR 0x020B9000 /* KraitMP_Sub_System */ 87#define CPU3_APCS_TMR_PADDR 0x020BA000 /* KraitMP_Sub_System */ 88#define APCS_HSEL_PADDR 0x02100000 /* KraitMP_Sub_System */ 89#define RIVA_PADDR 0x03000000 /* RIVA */ 90#define MMSS_CC_PADDR 0x04000000 /* Multi_Media_Sub_System */ 91#define OXILI_PADDR 0x04300000 /* Multi_Media_Sub_System */ 92#define MFC_PADDR 0x04400000 /* Multi_Media_Sub_System */ 93#define VFE_PADDR 0x04500000 /* Multi_Media_Sub_System */ 94#define GEMINI_PADDR 0x04600000 /* Multi_Media_Sub_System */ 95#define MIPI_DSI_1_PADDR 0x04700000 /* Multi_Media_Sub_System */ 96#define CSID_PADDR 0x04800000 /* Multi_Media_Sub_System */ 97#define HDMI_TX_PADDR 0x04A00000 /* Multi_Media_Sub_System */ 98#define IMEM_MMSS_PADDR 0x04B00000 /* Multi_Media_Sub_System */ 99#define ROTATOR_PADDR 0x04E00000 /* Multi_Media_Sub_System */ 100#define TV_ENC_PADDR 0x04F00000 /* Multi_Media_Sub_System */ 101#define JPEGD_PADDR 0x05000000 /* Multi_Media_Sub_System */ 102#define MDP_PADDR 0x05100000 /* Multi_Media_Sub_System */ 103#define FABRIC_MMSS_PADDR 0x05200000 /* Fabrics */ 104#define VPE_PADDR 0x05300000 /* Multi_Media_Sub_System */ 105#define MSS_APU_PADDR 0x05400000 /* Multi_Media_Sub_System */ 106#define MMSS_SFPB_CFG_PADDR 0x05700000 /* Multi_Media_Sub_System */ 107#define MIPI_DSI_2_PADDR 0x05800000 /* Multi_Media_Sub_System */ 108#define VCAP_PADDR 0x05900000 /* Multi_Media_Sub_System */ 109#define SMMU_VCAP_PADDR 0x07200000 /* Multi_Media_Sub_System */ 110#define SMMU_JPEGD_PADDR 0x07300000 /* Multi_Media_Sub_System */ 111#define SMMU_VPE_PADDR 0x07400000 /* Multi_Media_Sub_System */ 112#define SMMU_MDP4_0_PADDR 0x07500000 /* Multi_Media_Sub_System */ 113#define SMMU_MDP4_1_PADDR 0x07600000 /* Multi_Media_Sub_System */ 114#define SMMU_ROTATOR_PADDR 0x07700000 /* Multi_Media_Sub_System */ 115#define SMMU_JPEG_PADDR 0x07800000 /* Multi_Media_Sub_System */ 116#define SMMU_VFE_PADDR 0x07900000 /* Multi_Media_Sub_System */ 117#define SMMU_SS1080P_0_PADDR 0x07A00000 /* Multi_Media_Sub_System */ 118#define SMMU_SS1080P_1_PADDR 0x07B00000 /* Multi_Media_Sub_System */ 119#define SMMU_GFX3D_PADDR 0x07C00000 /* Multi_Media_Sub_System */ 120#define SMMU_GFX3D1_PADDR 0x07D00000 /* Multi_Media_Sub_System */ 121#define SMMU_SFPB_CFG_DUMMY_PADDR 0x07F00000 /* Multi_Media_Sub_System */ 122#define GSS_A5_CSR_PADDR 0x10000000 /* GSS */ 123#define GSS_A5_SPM_PADDR 0x10001000 /* GSS */ 124#define GSS_A5_TIMERS_PADDR 0x10002000 /* GSS */ 125#define GSS_A5_SSBI_PADDR 0x10003000 /* GSS */ 126#define GSS_A5_QGIC2_PADDR 0x10008000 /* GSS */ 127#define NAV_PADDR 0x10100000 /* GSS */ 128#define CE3_CRYPTO4_PADDR 0x11000000 /* Security */ 129#define PPSS_PADDR 0x12080000 /* Daytona_SPS */ 130#define PPSS_SLP_TIMERS_PADDR 0x12081000 /* Daytona_SPS */ 131#define SIC_PADDR 0x120C0000 /* Daytona_SPS */ 132#define SIC_APU_PADDR 0x120C2000 /* Daytona_SPS */ 133#define SIC_NON_SECURE_PADDR 0x12100000 /* Daytona_SPS */ 134#define INTCTL0_PADDR 0x12100000 /* Daytona_SPS */ 135#define INTCTL1_PADDR 0x12100800 /* Daytona_SPS */ 136#define INTCTL2_PADDR 0x12101000 /* Daytona_SPS */ 137#define INTCTL3_PADDR 0x12101800 /* Daytona_SPS */ 138#define INTCTL4_PADDR 0x12102000 /* Daytona_SPS */ 139#define INTCTL5_PADDR 0x12102800 /* Daytona_SPS */ 140#define INTCTL6_PADDR 0x12103000 /* Daytona_SPS */ 141#define INTCTL7_PADDR 0x12103800 /* Daytona_SPS */ 142#define SDC2_PADDR 0x12140000 /* Daytona_SPS */ 143#define SDC2_DML_PADDR 0x12140800 /* Daytona_SPS */ 144#define SDC2_BAM_PADDR 0x12142000 /* Daytona_SPS */ 145#define SDC3_PADDR 0x12180000 /* Daytona_SPS */ 146#define SDC3_DML_PADDR 0x12180800 /* Daytona_SPS */ 147#define SDC3_BAM_PADDR 0x12182000 /* Daytona_SPS */ 148#define SDC4_PADDR 0x121C0000 /* Daytona_SPS */ 149#define SDC4_DML_PADDR 0x121C0800 /* Daytona_SPS */ 150#define SDC4_BAM_PADDR 0x121C2000 /* Daytona_SPS */ 151#define BAM_DMA_PADDR 0x12240000 /* Daytona_SPS */ 152#define BAM_DMA_BAM_PADDR 0x12244000 /* Daytona_SPS */ 153#define BAM_DMA_BAM_XPU_PADDR 0x12246000 /* Daytona_SPS */ 154#define SDC1_PADDR 0x12400000 /* Daytona_SPS */ 155#define SDC1_DML_PADDR 0x12400800 /* Daytona_SPS */ 156#define SDC1_BAM_PADDR 0x12402000 /* Daytona_SPS */ 157#define SPS_GSBI1_PADDR 0x12440000 /* Daytona_SPS */ 158#define SPS_UART1_DM_PADDR 0x12450000 /* Daytona_SPS */ 159#define SPS_QUP1_PADDR 0x12460000 /* Daytona_SPS */ 160#define SPS_GSBI2_PADDR 0x12480000 /* Daytona_SPS */ 161#define SPS_UART2_DM_PADDR 0x12490000 /* Daytona_SPS */ 162#define SPS_QUP2_PADDR 0x124A0000 /* Daytona_SPS */ 163#define USB1_HS_PADDR 0x12500000 /* Daytona_SPS */ 164#define USB1_HS_BAM_PADDR 0x12502000 /* Daytona_SPS */ 165#define USB2_HSIC_PADDR 0x12510000 /* Daytona_SPS */ 166#define USB3_HS_PADDR 0x12520000 /* Daytona_SPS */ 167#define USB3_HS_BAM_PADDR 0x12522000 /* Daytona_SPS */ 168#define USB4_HS_PADDR 0x12530000 /* Daytona_SPS */ 169#define USB4_HS_BAM_PADDR 0x12532000 /* Daytona_SPS */ 170#define CE2_CRYPTO4_PADDR 0x12560000 /* Security */ 171#define GSBI3_PADDR 0x16200000 /* GSBIs */ 172#define GSBI3_UART_DM_PADDR 0x16240000 /* GSBIs */ 173#define QUP3_PADDR 0x16280000 /* GSBIs */ 174#define GSBI4_PADDR 0x16300000 /* GSBIs */ 175#define GSBI4_UART_DM_PADDR 0x16340000 /* GSBIs */ 176#define QUP4_PADDR 0x16380000 /* GSBIs */ 177#define GSBI6_PADDR 0x16500000 /* GSBIs */ 178#define GSBI6_UART_DM_PADDR 0x16540000 /* GSBIs */ 179#define QUP6_PADDR 0x16580000 /* GSBIs */ 180#define GSBI7_PADDR 0x16600000 /* GSBIs */ 181#define GSBI7_UART_DM_PADDR 0x16640000 /* GSBIs */ 182#define QUP7_PADDR 0x16680000 /* GSBIs */ 183#define LPASS_XPU_PADDR 0x17000000 /* chip_core_top_XPUs */ 184#define KPSS_XPU_PADDR 0x17100000 /* chip_core_top_XPUs */ 185#define GSS_XPU_PADDR 0x17200000 /* chip_core_top_XPUs */ 186#define CFPB2_XPU_CFG_PADDR 0x17300000 /* chip_core_top_Peripherals */ 187#define CSYSFPB2_PADDR 0x17400000 /* chip_core_top_Peripherals */ 188#define CE3_XPU_CFG_PADDR 0x17500000 /* chip_core_top_XPUs */ 189#define CSYSFPB_SPL_PADDR 0x17F00000 /* chip_core_top_Peripherals */ 190#define USB1_FS_PADDR 0x18000000 /* chip_core_top_Peripherals */ 191#define TSIF_PADDR 0x18200000 /* chip_core_top_Peripherals */ 192#define TSPP_PADDR 0x18202000 /* chip_core_top_Peripherals */ 193#define TSIF_BAM_PADDR 0x18204000 /* chip_core_top_Peripherals */ 194#define ADM3_0_PADDR 0x18300000 /* chip_core_top_Peripherals */ 195#define CE1_CRYPTO4_PADDR 0x18500000 /* Security */ 196#define TSSC_PADDR 0x18600000 /* chip_core_top_Peripherals */ 197#define TSSC_SSBI_PADDR 0x18600000 /* chip_core_top_Peripherals */ 198#define MSM_PDM_PADDR 0x18700000 /* chip_core_top_Peripherals */ 199#define CSYSFPB_MST_PADDR 0x18D00000 /* chip_core_top_Peripherals */ 200#define CFPB1_XPU_CFG_PADDR 0x18E00000 /* chip_core_top_Peripherals */ 201#define CSYSFPB1_PADDR 0x18F00000 /* chip_core_top_Peripherals */ 202#define GSBI5_PADDR 0x1A200000 /* GSBIs */ 203#define GSBI5_UART_DM_PADDR 0x1A240000 /* GSBIs */ 204#define QUP5_PADDR 0x1A280000 /* GSBIs */ 205#define PMEM_PADDR 0x1A300000 /* chip_core_top_Peripherals */ 206#define MSM_TCSR_PADDR 0x1A400000 /* chip_core_top_Peripherals */ 207#define PRNG_PADDR 0x1A500000 /* chip_core_top_Peripherals */ 208#define DIM_D00_REG_PADDR 0x1A700000 /* LPDDR */ 209#define DIM_BD0_REG_PADDR 0x1A780000 /* EBI1_DIM */ 210#define DIM_D01_REG_PADDR 0x1A800000 /* LPDDR */ 211#define DIM_D02_REG_PADDR 0x1A900000 /* LPDDR */ 212#define DIM_D03_REG_PADDR 0x1AA00000 /* LPDDR */ 213#define DIM_C00_REG_PADDR 0x1AB00000 /* LPDDR */ 214#define DIM_BC0_REG_PADDR 0x1AB40000 /* EBI1_DIM */ 215#define DIM_C01_REG_PADDR 0x1AB80000 /* EBI1_DIM */ 216#define DIM_D10_REG_PADDR 0x1AC00000 /* LPDDR */ 217#define DIM_BD1_REG_PADDR 0x1AC80000 /* EBI1_DIM */ 218#define DIM_D11_REG_PADDR 0x1AD00000 /* LPDDR */ 219#define DIM_D12_REG_PADDR 0x1AE00000 /* LPDDR */ 220#define DIM_D13_REG_PADDR 0x1AF00000 /* LPDDR */ 221#define DIM_C10_REG_PADDR 0x1B000000 /* LPDDR */ 222#define DIM_BC1_REG_PADDR 0x1B040000 /* EBI1_DIM */ 223#define DIM_C11_REG_PADDR 0x1B080000 /* EBI1_DIM */ 224#define CFPB0_XPU_CFG_PADDR 0x1B100000 /* chip_core_top_Peripherals */ 225#define CSYSFPB0_PADDR 0x1B200000 /* chip_core_top_Peripherals */ 226#define SATA_XPU_CFG_PADDR 0x1B300000 /* chip_core_top_XPUs */ 227#define SATA_PHY_PADDR 0x1B400000 /* SATA */ 228#define PCIE20_PADDR 0x1B500000 /* PCIE20 */ 229#define PCIE20_ELBI_PADDR 0x1B502000 /* PCIE20 */ 230#define PCIE20_PARF_PADDR 0x1B600000 /* PCIE20 */ 231#define LPASS_CSR_PADDR 0x28000000 /* LP_Audio_Sub_System */ 232#define LPASS_M2VMT_PADDR 0x28002000 /* LP_Audio_Sub_System */ 233#define LPASS_M2VMT_Q6SS_PADDR 0x28003000 /* LP_Audio_Sub_System */ 234#define LPASS_AHBTM_PADDR 0x2800A000 /* LP_Audio_Sub_System */ 235#define LPASS_SLIMBUS_PADDR 0x28080000 /* LP_Audio_Sub_System */ 236#define LPASS_BAM_LITE_PADDR 0x28084000 /* LP_Audio_Sub_System */ 237#define LPA_IF_PADDR 0x28100000 /* LP_Audio_Sub_System */ 238#define MIDI_PADDR 0x28200000 /* LP_Audio_Sub_System */ 239#define LPASS_QDSP6SS_PUB_PADDR 0x28800000 /* LP_Audio_Sub_System */ 240#define LPASS_QDSP6SS_CSR_PADDR 0x28880000 /* LP_Audio_Sub_System */ 241#define LPASS_QDSP6SS_L2VIC_PADDR 0x28890000 /* LP_Audio_Sub_System */ 242#define LPASS_QDSP6SS_SAW_PADDR 0x288B0000 /* LP_Audio_Sub_System */ 243#define SATA_PADDR 0x29000000 /* SATA */ 244 245#endif /* !__PLAT_MACHINE_DEVICES_H */ 246