1(* riscv - generated by L3 - Mon Jul 03 10:14:12 2017 *) 2 3structure riscv :> riscv = 4struct 5 6structure Map = MutableMap 7 8(* ------------------------------------------------------------------------- 9 Type declarations 10 ------------------------------------------------------------------------- *) 11 12datatype accessType = Read | Write 13 14datatype fetchType = Instruction | Data 15 16datatype Architecture = RV32I | RV64I | RV128I 17 18datatype Privilege = User | Supervisor | Hypervisor | Machine 19 20datatype VM_Mode = Mbare | Mbb | Mbbid | Sv32 | Sv39 | Sv48 | Sv57 | Sv64 21 22datatype ExtStatus = Off | Initial | Clean | Dirty 23 24datatype Interrupt = Software | Timer 25 26datatype ExceptionType 27 = Fetch_Misaligned | Fetch_Fault | Illegal_Instr | Breakpoint 28 | Load_Fault | AMO_Misaligned | Store_AMO_Fault | UMode_Env_Call 29 | SMode_Env_Call | HMode_Env_Call | MMode_Env_Call 30 31type mcpuid = 32 { ArchBase: BitsN.nbit, I: bool, M: bool, S: bool, U: bool, 33 mcpuid'rst: BitsN.nbit } 34 35type mimpid = { RVImpl: BitsN.nbit, RVSource: BitsN.nbit } 36 37type mstatus = 38 { MFS: BitsN.nbit, MIE: bool, MIE1: bool, MIE2: bool, MIE3: bool, 39 MMPRV: bool, MPRV: BitsN.nbit, MPRV1: BitsN.nbit, MPRV2: BitsN.nbit, 40 MPRV3: BitsN.nbit, MSD: bool, MXS: BitsN.nbit, VM: BitsN.nbit, 41 mstatus'rst: BitsN.nbit } 42 43type mtdeleg = { Exc_deleg: BitsN.nbit, Intr_deleg: BitsN.nbit } 44 45type mip = 46 { HSIP: bool, HTIP: bool, MSIP: bool, MTIP: bool, SSIP: bool, 47 STIP: bool, mip'rst: BitsN.nbit } 48 49type mie = 50 { HSIE: bool, HTIE: bool, MSIE: bool, MTIE: bool, SSIE: bool, 51 STIE: bool, mie'rst: BitsN.nbit } 52 53type mcause = { EC: BitsN.nbit, Int: bool, mcause'rst: BitsN.nbit } 54 55type MachineCSR = 56 { mbadaddr: BitsN.nbit, mbase: BitsN.nbit, mbound: BitsN.nbit, 57 mcause: mcause, mcpuid: mcpuid, mdbase: BitsN.nbit, 58 mdbound: BitsN.nbit, mepc: BitsN.nbit, mfromhost: BitsN.nbit, 59 mhartid: BitsN.nbit, mibase: BitsN.nbit, mibound: BitsN.nbit, 60 mie: mie, mimpid: mimpid, mip: mip, mscratch: BitsN.nbit, 61 mstatus: mstatus, mtdeleg: mtdeleg, mtime_delta: BitsN.nbit, 62 mtimecmp: BitsN.nbit, mtohost: BitsN.nbit, mtvec: BitsN.nbit } 63 64type HypervisorCSR = 65 { hbadaddr: BitsN.nbit, hcause: mcause, hepc: BitsN.nbit, 66 hscratch: BitsN.nbit, hstatus: mstatus, htdeleg: mtdeleg, 67 htime_delta: BitsN.nbit, htimecmp: BitsN.nbit, htvec: BitsN.nbit } 68 69type sstatus = 70 { SFS: BitsN.nbit, SIE: bool, SMPRV: bool, SPIE: bool, SPS: bool, 71 SSD: bool, SXS: BitsN.nbit, sstatus'rst: BitsN.nbit } 72 73type sip = { SSIP: bool, STIP: bool, sip'rst: BitsN.nbit } 74 75type sie = { SSIE: bool, STIE: bool, sie'rst: BitsN.nbit } 76 77type SupervisorCSR = 78 { sasid: BitsN.nbit, sbadaddr: BitsN.nbit, scause: mcause, 79 sepc: BitsN.nbit, sptbr: BitsN.nbit, sscratch: BitsN.nbit, 80 stime_delta: BitsN.nbit, stimecmp: BitsN.nbit, stvec: BitsN.nbit } 81 82type FPCSR = 83 { DZ: bool, FRM: BitsN.nbit, NV: bool, NX: bool, OF: bool, UF: bool, 84 fpcsr'rst: BitsN.nbit } 85 86type UserCSR = 87 { cycle_delta: BitsN.nbit, fpcsr: FPCSR, instret_delta: BitsN.nbit, 88 time_delta: BitsN.nbit } 89 90type SynchronousTrap = { badaddr: BitsN.nbit option, trap: ExceptionType } 91 92datatype TransferControl 93 = BranchTo of BitsN.nbit | Ereturn | Mrts | Trap of SynchronousTrap 94 95datatype Rounding = RNE | RTZ | RDN | RUP | RMM | RDYN 96 97type StateDelta = 98 { addr: BitsN.nbit option, data1: BitsN.nbit option, 99 data2: BitsN.nbit option, exc_taken: bool, fetch_exc: bool, 100 fp_data: BitsN.nbit option, pc: BitsN.nbit, rinstr: BitsN.nbit, 101 st_width: BitsN.nbit option } 102 103type SV_PTE = 104 { PTE_D: bool, PTE_PPNi: BitsN.nbit, PTE_R: bool, PTE_SW: BitsN.nbit, 105 PTE_T: BitsN.nbit, PTE_V: bool, sv_pte'rst: BitsN.nbit } 106 107type SV_Vaddr = 108 { Sv_PgOfs: BitsN.nbit, Sv_VPNi: BitsN.nbit, sv_vaddr'rst: BitsN.nbit } 109 110type TLBEntry = 111 { age: BitsN.nbit, asid: BitsN.nbit, global: bool, pAddr: BitsN.nbit, 112 pte: SV_PTE, pteAddr: BitsN.nbit, vAddr: BitsN.nbit, 113 vAddrMask: BitsN.nbit, vMatchMask: BitsN.nbit } 114 115datatype Internal 116 = FETCH_FAULT of BitsN.nbit | FETCH_MISALIGNED of BitsN.nbit 117 118datatype System 119 = CSRRC of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 120 | CSRRCI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 121 | CSRRS of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 122 | CSRRSI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 123 | CSRRW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 124 | CSRRWI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 125 | EBREAK 126 | ECALL 127 | ERET 128 | MRTS 129 | SFENCE_VM of BitsN.nbit 130 | WFI 131 132datatype FConv 133 = FCLASS_D of BitsN.nbit * BitsN.nbit 134 | FCLASS_S of BitsN.nbit * BitsN.nbit 135 | FCVT_D_L of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 136 | FCVT_D_LU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 137 | FCVT_D_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 138 | FCVT_D_W of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 139 | FCVT_D_WU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 140 | FCVT_LU_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 141 | FCVT_LU_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 142 | FCVT_L_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 143 | FCVT_L_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 144 | FCVT_S_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 145 | FCVT_S_L of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 146 | FCVT_S_LU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 147 | FCVT_S_W of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 148 | FCVT_S_WU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 149 | FCVT_WU_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 150 | FCVT_WU_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 151 | FCVT_W_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 152 | FCVT_W_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 153 | FMV_D_X of BitsN.nbit * BitsN.nbit 154 | FMV_S_X of BitsN.nbit * BitsN.nbit 155 | FMV_X_D of BitsN.nbit * BitsN.nbit 156 | FMV_X_S of BitsN.nbit * BitsN.nbit 157 | FSGNJN_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 158 | FSGNJN_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 159 | FSGNJX_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 160 | FSGNJX_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 161 | FSGNJ_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 162 | FSGNJ_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 163 164datatype FArith 165 = FADD_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 166 | FADD_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 167 | FDIV_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 168 | FDIV_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 169 | FEQ_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 170 | FEQ_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 171 | FLE_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 172 | FLE_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 173 | FLT_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 174 | FLT_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 175 | FMADD_D of 176 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 177 | FMADD_S of 178 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 179 | FMAX_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 180 | FMAX_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 181 | FMIN_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 182 | FMIN_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 183 | FMSUB_D of 184 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 185 | FMSUB_S of 186 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 187 | FMUL_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 188 | FMUL_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 189 | FNMADD_D of 190 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 191 | FNMADD_S of 192 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 193 | FNMSUB_D of 194 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 195 | FNMSUB_S of 196 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 197 | FSQRT_D of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 198 | FSQRT_S of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 199 | FSUB_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 200 | FSUB_S of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 201 202datatype FPStore 203 = FSD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 204 | FSW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 205 206datatype FPLoad 207 = FLD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 208 | FLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 209 210datatype AMO 211 = AMOADD_D of 212 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 213 | AMOADD_W of 214 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 215 | AMOAND_D of 216 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 217 | AMOAND_W of 218 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 219 | AMOMAXU_D of 220 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 221 | AMOMAXU_W of 222 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 223 | AMOMAX_D of 224 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 225 | AMOMAX_W of 226 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 227 | AMOMINU_D of 228 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 229 | AMOMINU_W of 230 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 231 | AMOMIN_D of 232 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 233 | AMOMIN_W of 234 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 235 | AMOOR_D of 236 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 237 | AMOOR_W of 238 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 239 | AMOSWAP_D of 240 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 241 | AMOSWAP_W of 242 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 243 | AMOXOR_D of 244 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 245 | AMOXOR_W of 246 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 247 | LR_D of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 248 | LR_W of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 249 | SC_D of 250 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 251 | SC_W of 252 BitsN.nbit * (BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit))) 253 254datatype Store 255 = SB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 256 | SD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 257 | SH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 258 | SW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 259 260datatype Load 261 = LB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 262 | LBU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 263 | LD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 264 | LH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 265 | LHU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 266 | LW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 267 | LWU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 268 269datatype Branch 270 = BEQ of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 271 | BGE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 272 | BGEU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 273 | BLT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 274 | BLTU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 275 | BNE of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 276 | JAL of BitsN.nbit * BitsN.nbit 277 | JALR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 278 279datatype MulDiv 280 = DIV of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 281 | DIVU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 282 | DIVUW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 283 | DIVW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 284 | MUL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 285 | MULH of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 286 | MULHSU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 287 | MULHU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 288 | MULW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 289 | REM of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 290 | REMU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 291 | REMUW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 292 | REMW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 293 294datatype Shift 295 = SLL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 296 | SLLI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 297 | SLLIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 298 | SLLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 299 | SRA of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 300 | SRAI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 301 | SRAIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 302 | SRAW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 303 | SRL of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 304 | SRLI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 305 | SRLIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 306 | SRLW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 307 308datatype ArithR 309 = ADD of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 310 | ADDW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 311 | AND of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 312 | OR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 313 | SLT of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 314 | SLTU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 315 | SUB of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 316 | SUBW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 317 | XOR of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 318 319datatype ArithI 320 = ADDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 321 | ADDIW of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 322 | ANDI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 323 | AUIPC of BitsN.nbit * BitsN.nbit 324 | LUI of BitsN.nbit * BitsN.nbit 325 | ORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 326 | SLTI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 327 | SLTIU of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 328 | XORI of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 329 330datatype instruction 331 = AMO of AMO 332 | ArithI of ArithI 333 | ArithR of ArithR 334 | Branch of Branch 335 | FArith of FArith 336 | FConv of FConv 337 | FENCE of BitsN.nbit * (BitsN.nbit * (BitsN.nbit * BitsN.nbit)) 338 | FENCE_I of BitsN.nbit * (BitsN.nbit * BitsN.nbit) 339 | FPLoad of FPLoad 340 | FPStore of FPStore 341 | Internal of Internal 342 | Load of Load 343 | MulDiv of MulDiv 344 | Shift of Shift 345 | Store of Store 346 | System of System 347 | UnknownInstruction 348 349datatype FetchResult = F_Error of instruction | F_Result of BitsN.nbit 350 351(* ------------------------------------------------------------------------- 352 Casting maps (for enumerated types) 353 ------------------------------------------------------------------------- *) 354 355structure Cast = 356struct 357fun natToaccessType x = 358 case Nat.toInt x of 359 0 => Read | 1 => Write | _ => raise Fail "natToaccessType" 360 361fun natTofetchType x = 362 case Nat.toInt x of 363 0 => Instruction | 1 => Data | _ => raise Fail "natTofetchType" 364 365fun natToArchitecture x = 366 case Nat.toInt x of 367 0 => RV32I 368 | 1 => RV64I 369 | 2 => RV128I 370 | _ => raise Fail "natToArchitecture" 371 372fun natToPrivilege x = 373 case Nat.toInt x of 374 0 => User 375 | 1 => Supervisor 376 | 2 => Hypervisor 377 | 3 => Machine 378 | _ => raise Fail "natToPrivilege" 379 380fun natToVM_Mode x = 381 case Nat.toInt x of 382 0 => Mbare 383 | 1 => Mbb 384 | 2 => Mbbid 385 | 3 => Sv32 386 | 4 => Sv39 387 | 5 => Sv48 388 | 6 => Sv57 389 | 7 => Sv64 390 | _ => raise Fail "natToVM_Mode" 391 392fun natToExtStatus x = 393 case Nat.toInt x of 394 0 => Off 395 | 1 => Initial 396 | 2 => Clean 397 | 3 => Dirty 398 | _ => raise Fail "natToExtStatus" 399 400fun natToInterrupt x = 401 case Nat.toInt x of 402 0 => Software | 1 => Timer | _ => raise Fail "natToInterrupt" 403 404fun natToExceptionType x = 405 case Nat.toInt x of 406 0 => Fetch_Misaligned 407 | 1 => Fetch_Fault 408 | 2 => Illegal_Instr 409 | 3 => Breakpoint 410 | 4 => Load_Fault 411 | 5 => AMO_Misaligned 412 | 6 => Store_AMO_Fault 413 | 7 => UMode_Env_Call 414 | 8 => SMode_Env_Call 415 | 9 => HMode_Env_Call 416 | 10 => MMode_Env_Call 417 | _ => raise Fail "natToExceptionType" 418 419fun natToRounding x = 420 case Nat.toInt x of 421 0 => RNE 422 | 1 => RTZ 423 | 2 => RDN 424 | 3 => RUP 425 | 4 => RMM 426 | 5 => RDYN 427 | _ => raise Fail "natToRounding" 428 429fun accessTypeToNat x = 430 case x of 431 Read => 0 | Write => 1 432 433fun fetchTypeToNat x = 434 case x of 435 Instruction => 0 | Data => 1 436 437fun ArchitectureToNat x = 438 case x of 439 RV32I => 0 | RV64I => 1 | RV128I => 2 440 441fun PrivilegeToNat x = 442 case x of 443 User => 0 | Supervisor => 1 | Hypervisor => 2 | Machine => 3 444 445fun VM_ModeToNat x = 446 case x of 447 Mbare => 0 448 | Mbb => 1 449 | Mbbid => 2 450 | Sv32 => 3 451 | Sv39 => 4 452 | Sv48 => 5 453 | Sv57 => 6 454 | Sv64 => 7 455 456fun ExtStatusToNat x = 457 case x of 458 Off => 0 | Initial => 1 | Clean => 2 | Dirty => 3 459 460fun InterruptToNat x = 461 case x of 462 Software => 0 | Timer => 1 463 464fun ExceptionTypeToNat x = 465 case x of 466 Fetch_Misaligned => 0 467 | Fetch_Fault => 1 468 | Illegal_Instr => 2 469 | Breakpoint => 3 470 | Load_Fault => 4 471 | AMO_Misaligned => 5 472 | Store_AMO_Fault => 6 473 | UMode_Env_Call => 7 474 | SMode_Env_Call => 8 475 | HMode_Env_Call => 9 476 | MMode_Env_Call => 10 477 478fun RoundingToNat x = 479 case x of 480 RNE => 0 | RTZ => 1 | RDN => 2 | RUP => 3 | RMM => 4 | RDYN => 5 481 482fun accessTypeToString x = 483 case x of 484 Read => "Read" | Write => "Write" 485 486fun fetchTypeToString x = 487 case x of 488 Instruction => "Instruction" | Data => "Data" 489 490fun ArchitectureToString x = 491 case x of 492 RV32I => "RV32I" | RV64I => "RV64I" | RV128I => "RV128I" 493 494fun PrivilegeToString x = 495 case x of 496 User => "User" 497 | Supervisor => "Supervisor" 498 | Hypervisor => "Hypervisor" 499 | Machine => "Machine" 500 501fun VM_ModeToString x = 502 case x of 503 Mbare => "Mbare" 504 | Mbb => "Mbb" 505 | Mbbid => "Mbbid" 506 | Sv32 => "Sv32" 507 | Sv39 => "Sv39" 508 | Sv48 => "Sv48" 509 | Sv57 => "Sv57" 510 | Sv64 => "Sv64" 511 512fun ExtStatusToString x = 513 case x of 514 Off => "Off" 515 | Initial => "Initial" 516 | Clean => "Clean" 517 | Dirty => "Dirty" 518 519fun InterruptToString x = 520 case x of 521 Software => "Software" | Timer => "Timer" 522 523fun ExceptionTypeToString x = 524 case x of 525 Fetch_Misaligned => "Fetch_Misaligned" 526 | Fetch_Fault => "Fetch_Fault" 527 | Illegal_Instr => "Illegal_Instr" 528 | Breakpoint => "Breakpoint" 529 | Load_Fault => "Load_Fault" 530 | AMO_Misaligned => "AMO_Misaligned" 531 | Store_AMO_Fault => "Store_AMO_Fault" 532 | UMode_Env_Call => "UMode_Env_Call" 533 | SMode_Env_Call => "SMode_Env_Call" 534 | HMode_Env_Call => "HMode_Env_Call" 535 | MMode_Env_Call => "MMode_Env_Call" 536 537fun RoundingToString x = 538 case x of 539 RNE => "RNE" 540 | RTZ => "RTZ" 541 | RDN => "RDN" 542 | RUP => "RUP" 543 | RMM => "RMM" 544 | RDYN => "RDYN" 545 546fun stringToaccessType x = 547 case x of 548 "Read" => Read 549 | "Write" => Write 550 | _ => raise Fail "stringToaccessType" 551 552fun stringTofetchType x = 553 case x of 554 "Instruction" => Instruction 555 | "Data" => Data 556 | _ => raise Fail "stringTofetchType" 557 558fun stringToArchitecture x = 559 case x of 560 "RV32I" => RV32I 561 | "RV64I" => RV64I 562 | "RV128I" => RV128I 563 | _ => raise Fail "stringToArchitecture" 564 565fun stringToPrivilege x = 566 case x of 567 "User" => User 568 | "Supervisor" => Supervisor 569 | "Hypervisor" => Hypervisor 570 | "Machine" => Machine 571 | _ => raise Fail "stringToPrivilege" 572 573fun stringToVM_Mode x = 574 case x of 575 "Mbare" => Mbare 576 | "Mbb" => Mbb 577 | "Mbbid" => Mbbid 578 | "Sv32" => Sv32 579 | "Sv39" => Sv39 580 | "Sv48" => Sv48 581 | "Sv57" => Sv57 582 | "Sv64" => Sv64 583 | _ => raise Fail "stringToVM_Mode" 584 585fun stringToExtStatus x = 586 case x of 587 "Off" => Off 588 | "Initial" => Initial 589 | "Clean" => Clean 590 | "Dirty" => Dirty 591 | _ => raise Fail "stringToExtStatus" 592 593fun stringToInterrupt x = 594 case x of 595 "Software" => Software 596 | "Timer" => Timer 597 | _ => raise Fail "stringToInterrupt" 598 599fun stringToExceptionType x = 600 case x of 601 "Fetch_Misaligned" => Fetch_Misaligned 602 | "Fetch_Fault" => Fetch_Fault 603 | "Illegal_Instr" => Illegal_Instr 604 | "Breakpoint" => Breakpoint 605 | "Load_Fault" => Load_Fault 606 | "AMO_Misaligned" => AMO_Misaligned 607 | "Store_AMO_Fault" => Store_AMO_Fault 608 | "UMode_Env_Call" => UMode_Env_Call 609 | "SMode_Env_Call" => SMode_Env_Call 610 | "HMode_Env_Call" => HMode_Env_Call 611 | "MMode_Env_Call" => MMode_Env_Call 612 | _ => raise Fail "stringToExceptionType" 613 614fun stringToRounding x = 615 case x of 616 "RNE" => RNE 617 | "RTZ" => RTZ 618 | "RDN" => RDN 619 | "RUP" => RUP 620 | "RMM" => RMM 621 | "RDYN" => RDYN 622 | _ => raise Fail "stringToRounding" 623end 624 625(* ------------------------------------------------------------------------- 626 Record update functions 627 ------------------------------------------------------------------------- *) 628 629fun mcpuid_ArchBase_rupd ({ArchBase, I, M, S, U, mcpuid'rst} 630 : mcpuid, x') = 631 {ArchBase = x', I = I, M = M, S = S, U = U, mcpuid'rst = mcpuid'rst} 632 : mcpuid 633 634fun mcpuid_I_rupd ({ArchBase, I, M, S, U, mcpuid'rst}: mcpuid, x') = 635 {ArchBase = ArchBase, I = x', M = M, S = S, U = U, 636 mcpuid'rst = mcpuid'rst}: mcpuid 637 638fun mcpuid_M_rupd ({ArchBase, I, M, S, U, mcpuid'rst}: mcpuid, x') = 639 {ArchBase = ArchBase, I = I, M = x', S = S, U = U, 640 mcpuid'rst = mcpuid'rst}: mcpuid 641 642fun mcpuid_S_rupd ({ArchBase, I, M, S, U, mcpuid'rst}: mcpuid, x') = 643 {ArchBase = ArchBase, I = I, M = M, S = x', U = U, 644 mcpuid'rst = mcpuid'rst}: mcpuid 645 646fun mcpuid_U_rupd ({ArchBase, I, M, S, U, mcpuid'rst}: mcpuid, x') = 647 {ArchBase = ArchBase, I = I, M = M, S = S, U = x', 648 mcpuid'rst = mcpuid'rst}: mcpuid 649 650fun mcpuid_mcpuid'rst_rupd ({ArchBase, I, M, S, U, mcpuid'rst} 651 : mcpuid, x') = 652 {ArchBase = ArchBase, I = I, M = M, S = S, U = U, mcpuid'rst = x'} 653 : mcpuid 654 655fun mimpid_RVImpl_rupd ({RVImpl, RVSource}: mimpid, x') = 656 {RVImpl = x', RVSource = RVSource}: mimpid 657 658fun mimpid_RVSource_rupd ({RVImpl, RVSource}: mimpid, x') = 659 {RVImpl = RVImpl, RVSource = x'}: mimpid 660 661fun mstatus_MFS_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 662 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 663 {MFS = x', MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 664 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 665 MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} 666 : mstatus 667 668fun mstatus_MIE_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 669 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 670 {MFS = MFS, MIE = x', MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 671 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 672 MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} 673 : mstatus 674 675fun mstatus_MIE1_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 676 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 677 {MFS = MFS, MIE = MIE, MIE1 = x', MIE2 = MIE2, MIE3 = MIE3, 678 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 679 MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} 680 : mstatus 681 682fun mstatus_MIE2_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 683 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 684 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = x', MIE3 = MIE3, 685 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 686 MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} 687 : mstatus 688 689fun mstatus_MIE3_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 690 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 691 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = x', 692 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 693 MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} 694 : mstatus 695 696fun mstatus_MMPRV_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 697 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 698 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 699 MMPRV = x', MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, MPRV3 = MPRV3, 700 MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus 701 702fun mstatus_MPRV_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 703 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 704 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 705 MMPRV = MMPRV, MPRV = x', MPRV1 = MPRV1, MPRV2 = MPRV2, MPRV3 = MPRV3, 706 MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus 707 708fun mstatus_MPRV1_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 709 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 710 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 711 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = x', MPRV2 = MPRV2, MPRV3 = MPRV3, 712 MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus 713 714fun mstatus_MPRV2_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 715 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 716 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 717 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = x', MPRV3 = MPRV3, 718 MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus 719 720fun mstatus_MPRV3_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 721 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 722 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 723 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, MPRV3 = x', 724 MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = mstatus'rst}: mstatus 725 726fun mstatus_MSD_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 727 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 728 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 729 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 730 MPRV3 = MPRV3, MSD = x', MXS = MXS, VM = VM, mstatus'rst = mstatus'rst} 731 : mstatus 732 733fun mstatus_MXS_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 734 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 735 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 736 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 737 MPRV3 = MPRV3, MSD = MSD, MXS = x', VM = VM, mstatus'rst = mstatus'rst} 738 : mstatus 739 740fun mstatus_VM_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, MPRV1, 741 MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 742 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 743 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 744 MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = x', mstatus'rst = mstatus'rst} 745 : mstatus 746 747fun mstatus_mstatus'rst_rupd ({MFS, MIE, MIE1, MIE2, MIE3, MMPRV, MPRV, 748 MPRV1, MPRV2, MPRV3, MSD, MXS, VM, mstatus'rst}: mstatus, x') = 749 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 750 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 751 MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, mstatus'rst = x'} 752 : mstatus 753 754fun mtdeleg_Exc_deleg_rupd ({Exc_deleg, Intr_deleg}: mtdeleg, x') = 755 {Exc_deleg = x', Intr_deleg = Intr_deleg}: mtdeleg 756 757fun mtdeleg_Intr_deleg_rupd ({Exc_deleg, Intr_deleg}: mtdeleg, x') = 758 {Exc_deleg = Exc_deleg, Intr_deleg = x'}: mtdeleg 759 760fun mip_HSIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} 761 : mip, x') = 762 {HSIP = x', HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, 763 STIP = STIP, mip'rst = mip'rst}: mip 764 765fun mip_HTIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} 766 : mip, x') = 767 {HSIP = HSIP, HTIP = x', MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, 768 STIP = STIP, mip'rst = mip'rst}: mip 769 770fun mip_MSIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} 771 : mip, x') = 772 {HSIP = HSIP, HTIP = HTIP, MSIP = x', MTIP = MTIP, SSIP = SSIP, 773 STIP = STIP, mip'rst = mip'rst}: mip 774 775fun mip_MTIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} 776 : mip, x') = 777 {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = x', SSIP = SSIP, 778 STIP = STIP, mip'rst = mip'rst}: mip 779 780fun mip_SSIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} 781 : mip, x') = 782 {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = x', 783 STIP = STIP, mip'rst = mip'rst}: mip 784 785fun mip_STIP_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} 786 : mip, x') = 787 {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, 788 STIP = x', mip'rst = mip'rst}: mip 789 790fun mip_mip'rst_rupd ({HSIP, HTIP, MSIP, MTIP, SSIP, STIP, mip'rst} 791 : mip, x') = 792 {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, 793 STIP = STIP, mip'rst = x'}: mip 794 795fun mie_HSIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} 796 : mie, x') = 797 {HSIE = x', HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, 798 STIE = STIE, mie'rst = mie'rst}: mie 799 800fun mie_HTIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} 801 : mie, x') = 802 {HSIE = HSIE, HTIE = x', MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, 803 STIE = STIE, mie'rst = mie'rst}: mie 804 805fun mie_MSIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} 806 : mie, x') = 807 {HSIE = HSIE, HTIE = HTIE, MSIE = x', MTIE = MTIE, SSIE = SSIE, 808 STIE = STIE, mie'rst = mie'rst}: mie 809 810fun mie_MTIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} 811 : mie, x') = 812 {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = x', SSIE = SSIE, 813 STIE = STIE, mie'rst = mie'rst}: mie 814 815fun mie_SSIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} 816 : mie, x') = 817 {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = x', 818 STIE = STIE, mie'rst = mie'rst}: mie 819 820fun mie_STIE_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} 821 : mie, x') = 822 {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, 823 STIE = x', mie'rst = mie'rst}: mie 824 825fun mie_mie'rst_rupd ({HSIE, HTIE, MSIE, MTIE, SSIE, STIE, mie'rst} 826 : mie, x') = 827 {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, 828 STIE = STIE, mie'rst = x'}: mie 829 830fun mcause_EC_rupd ({EC, Int, mcause'rst}: mcause, x') = 831 {EC = x', Int = Int, mcause'rst = mcause'rst}: mcause 832 833fun mcause_Int_rupd ({EC, Int, mcause'rst}: mcause, x') = 834 {EC = EC, Int = x', mcause'rst = mcause'rst}: mcause 835 836fun mcause_mcause'rst_rupd ({EC, Int, mcause'rst}: mcause, x') = 837 {EC = EC, Int = Int, mcause'rst = x'}: mcause 838 839fun MachineCSR_mbadaddr_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 840 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 841 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 842 mtohost, mtvec}: MachineCSR, x') = 843 {mbadaddr = x', mbase = mbase, mbound = mbound, mcause = mcause, 844 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 845 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 846 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 847 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 848 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 849 mtvec = mtvec}: MachineCSR 850 851fun MachineCSR_mbase_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 852 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 853 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 854 mtohost, mtvec}: MachineCSR, x') = 855 {mbadaddr = mbadaddr, mbase = x', mbound = mbound, mcause = mcause, 856 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 857 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 858 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 859 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 860 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 861 mtvec = mtvec}: MachineCSR 862 863fun MachineCSR_mbound_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 864 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 865 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 866 mtohost, mtvec}: MachineCSR, x') = 867 {mbadaddr = mbadaddr, mbase = mbase, mbound = x', mcause = mcause, 868 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 869 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 870 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 871 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 872 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 873 mtvec = mtvec}: MachineCSR 874 875fun MachineCSR_mcause_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 876 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 877 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 878 mtohost, mtvec}: MachineCSR, x') = 879 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = x', 880 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 881 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 882 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 883 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 884 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 885 mtvec = mtvec}: MachineCSR 886 887fun MachineCSR_mcpuid_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 888 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 889 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 890 mtohost, mtvec}: MachineCSR, x') = 891 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 892 mcpuid = x', mdbase = mdbase, mdbound = mdbound, mepc = mepc, 893 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 894 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 895 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 896 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 897 mtvec = mtvec}: MachineCSR 898 899fun MachineCSR_mdbase_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 900 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 901 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 902 mtohost, mtvec}: MachineCSR, x') = 903 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 904 mcpuid = mcpuid, mdbase = x', mdbound = mdbound, mepc = mepc, 905 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 906 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 907 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 908 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 909 mtvec = mtvec}: MachineCSR 910 911fun MachineCSR_mdbound_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 912 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 913 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 914 mtohost, mtvec}: MachineCSR, x') = 915 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 916 mcpuid = mcpuid, mdbase = mdbase, mdbound = x', mepc = mepc, 917 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 918 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 919 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 920 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 921 mtvec = mtvec}: MachineCSR 922 923fun MachineCSR_mepc_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 924 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 925 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 926 mtohost, mtvec}: MachineCSR, x') = 927 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 928 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = x', 929 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 930 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 931 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 932 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 933 mtvec = mtvec}: MachineCSR 934 935fun MachineCSR_mfromhost_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 936 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 937 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 938 mtohost, mtvec}: MachineCSR, x') = 939 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 940 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 941 mfromhost = x', mhartid = mhartid, mibase = mibase, mibound = mibound, 942 mie = mie, mimpid = mimpid, mip = mip, mscratch = mscratch, 943 mstatus = mstatus, mtdeleg = mtdeleg, mtime_delta = mtime_delta, 944 mtimecmp = mtimecmp, mtohost = mtohost, mtvec = mtvec}: MachineCSR 945 946fun MachineCSR_mhartid_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 947 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 948 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 949 mtohost, mtvec}: MachineCSR, x') = 950 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 951 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 952 mfromhost = mfromhost, mhartid = x', mibase = mibase, 953 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 954 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 955 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 956 mtvec = mtvec}: MachineCSR 957 958fun MachineCSR_mibase_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 959 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 960 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 961 mtohost, mtvec}: MachineCSR, x') = 962 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 963 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 964 mfromhost = mfromhost, mhartid = mhartid, mibase = x', 965 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 966 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 967 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 968 mtvec = mtvec}: MachineCSR 969 970fun MachineCSR_mibound_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 971 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 972 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 973 mtohost, mtvec}: MachineCSR, x') = 974 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 975 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 976 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 977 mibound = x', mie = mie, mimpid = mimpid, mip = mip, 978 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 979 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 980 mtvec = mtvec}: MachineCSR 981 982fun MachineCSR_mie_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, mdbase, 983 mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, mimpid, mip, 984 mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, mtohost, mtvec} 985 : MachineCSR, x') = 986 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 987 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 988 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 989 mibound = mibound, mie = x', mimpid = mimpid, mip = mip, 990 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 991 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 992 mtvec = mtvec}: MachineCSR 993 994fun MachineCSR_mimpid_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 995 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 996 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 997 mtohost, mtvec}: MachineCSR, x') = 998 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 999 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1000 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1001 mibound = mibound, mie = mie, mimpid = x', mip = mip, 1002 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 1003 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 1004 mtvec = mtvec}: MachineCSR 1005 1006fun MachineCSR_mip_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, mdbase, 1007 mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, mimpid, mip, 1008 mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, mtohost, mtvec} 1009 : MachineCSR, x') = 1010 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 1011 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1012 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1013 mibound = mibound, mie = mie, mimpid = mimpid, mip = x', 1014 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 1015 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 1016 mtvec = mtvec}: MachineCSR 1017 1018fun MachineCSR_mscratch_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 1019 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 1020 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 1021 mtohost, mtvec}: MachineCSR, x') = 1022 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 1023 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1024 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1025 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 1026 mscratch = x', mstatus = mstatus, mtdeleg = mtdeleg, 1027 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 1028 mtvec = mtvec}: MachineCSR 1029 1030fun MachineCSR_mstatus_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 1031 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 1032 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 1033 mtohost, mtvec}: MachineCSR, x') = 1034 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 1035 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1036 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1037 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 1038 mscratch = mscratch, mstatus = x', mtdeleg = mtdeleg, 1039 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 1040 mtvec = mtvec}: MachineCSR 1041 1042fun MachineCSR_mtdeleg_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 1043 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 1044 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 1045 mtohost, mtvec}: MachineCSR, x') = 1046 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 1047 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1048 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1049 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 1050 mscratch = mscratch, mstatus = mstatus, mtdeleg = x', 1051 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 1052 mtvec = mtvec}: MachineCSR 1053 1054fun MachineCSR_mtime_delta_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 1055 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 1056 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 1057 mtohost, mtvec}: MachineCSR, x') = 1058 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 1059 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1060 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1061 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 1062 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 1063 mtime_delta = x', mtimecmp = mtimecmp, mtohost = mtohost, mtvec = mtvec} 1064 : MachineCSR 1065 1066fun MachineCSR_mtimecmp_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 1067 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 1068 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 1069 mtohost, mtvec}: MachineCSR, x') = 1070 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 1071 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1072 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1073 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 1074 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 1075 mtime_delta = mtime_delta, mtimecmp = x', mtohost = mtohost, 1076 mtvec = mtvec}: MachineCSR 1077 1078fun MachineCSR_mtohost_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 1079 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 1080 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 1081 mtohost, mtvec}: MachineCSR, x') = 1082 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 1083 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1084 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1085 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 1086 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 1087 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = x', 1088 mtvec = mtvec}: MachineCSR 1089 1090fun MachineCSR_mtvec_rupd ({mbadaddr, mbase, mbound, mcause, mcpuid, 1091 mdbase, mdbound, mepc, mfromhost, mhartid, mibase, mibound, mie, 1092 mimpid, mip, mscratch, mstatus, mtdeleg, mtime_delta, mtimecmp, 1093 mtohost, mtvec}: MachineCSR, x') = 1094 {mbadaddr = mbadaddr, mbase = mbase, mbound = mbound, mcause = mcause, 1095 mcpuid = mcpuid, mdbase = mdbase, mdbound = mdbound, mepc = mepc, 1096 mfromhost = mfromhost, mhartid = mhartid, mibase = mibase, 1097 mibound = mibound, mie = mie, mimpid = mimpid, mip = mip, 1098 mscratch = mscratch, mstatus = mstatus, mtdeleg = mtdeleg, 1099 mtime_delta = mtime_delta, mtimecmp = mtimecmp, mtohost = mtohost, 1100 mtvec = x'}: MachineCSR 1101 1102fun HypervisorCSR_hbadaddr_rupd ({hbadaddr, hcause, hepc, hscratch, 1103 hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1104 {hbadaddr = x', hcause = hcause, hepc = hepc, hscratch = hscratch, 1105 hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, 1106 htimecmp = htimecmp, htvec = htvec}: HypervisorCSR 1107 1108fun HypervisorCSR_hcause_rupd ({hbadaddr, hcause, hepc, hscratch, hstatus, 1109 htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1110 {hbadaddr = hbadaddr, hcause = x', hepc = hepc, hscratch = hscratch, 1111 hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, 1112 htimecmp = htimecmp, htvec = htvec}: HypervisorCSR 1113 1114fun HypervisorCSR_hepc_rupd ({hbadaddr, hcause, hepc, hscratch, hstatus, 1115 htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1116 {hbadaddr = hbadaddr, hcause = hcause, hepc = x', hscratch = hscratch, 1117 hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, 1118 htimecmp = htimecmp, htvec = htvec}: HypervisorCSR 1119 1120fun HypervisorCSR_hscratch_rupd ({hbadaddr, hcause, hepc, hscratch, 1121 hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1122 {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = x', 1123 hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, 1124 htimecmp = htimecmp, htvec = htvec}: HypervisorCSR 1125 1126fun HypervisorCSR_hstatus_rupd ({hbadaddr, hcause, hepc, hscratch, 1127 hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1128 {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, 1129 hstatus = x', htdeleg = htdeleg, htime_delta = htime_delta, 1130 htimecmp = htimecmp, htvec = htvec}: HypervisorCSR 1131 1132fun HypervisorCSR_htdeleg_rupd ({hbadaddr, hcause, hepc, hscratch, 1133 hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1134 {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, 1135 hstatus = hstatus, htdeleg = x', htime_delta = htime_delta, 1136 htimecmp = htimecmp, htvec = htvec}: HypervisorCSR 1137 1138fun HypervisorCSR_htime_delta_rupd ({hbadaddr, hcause, hepc, hscratch, 1139 hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1140 {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, 1141 hstatus = hstatus, htdeleg = htdeleg, htime_delta = x', 1142 htimecmp = htimecmp, htvec = htvec}: HypervisorCSR 1143 1144fun HypervisorCSR_htimecmp_rupd ({hbadaddr, hcause, hepc, hscratch, 1145 hstatus, htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1146 {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, 1147 hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, 1148 htimecmp = x', htvec = htvec}: HypervisorCSR 1149 1150fun HypervisorCSR_htvec_rupd ({hbadaddr, hcause, hepc, hscratch, hstatus, 1151 htdeleg, htime_delta, htimecmp, htvec}: HypervisorCSR, x') = 1152 {hbadaddr = hbadaddr, hcause = hcause, hepc = hepc, hscratch = hscratch, 1153 hstatus = hstatus, htdeleg = htdeleg, htime_delta = htime_delta, 1154 htimecmp = htimecmp, htvec = x'}: HypervisorCSR 1155 1156fun sstatus_SFS_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} 1157 : sstatus, x') = 1158 {SFS = x', SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = SSD, 1159 SXS = SXS, sstatus'rst = sstatus'rst}: sstatus 1160 1161fun sstatus_SIE_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} 1162 : sstatus, x') = 1163 {SFS = SFS, SIE = x', SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = SSD, 1164 SXS = SXS, sstatus'rst = sstatus'rst}: sstatus 1165 1166fun sstatus_SMPRV_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} 1167 : sstatus, x') = 1168 {SFS = SFS, SIE = SIE, SMPRV = x', SPIE = SPIE, SPS = SPS, SSD = SSD, 1169 SXS = SXS, sstatus'rst = sstatus'rst}: sstatus 1170 1171fun sstatus_SPIE_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} 1172 : sstatus, x') = 1173 {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = x', SPS = SPS, SSD = SSD, 1174 SXS = SXS, sstatus'rst = sstatus'rst}: sstatus 1175 1176fun sstatus_SPS_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} 1177 : sstatus, x') = 1178 {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = x', SSD = SSD, 1179 SXS = SXS, sstatus'rst = sstatus'rst}: sstatus 1180 1181fun sstatus_SSD_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} 1182 : sstatus, x') = 1183 {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = x', 1184 SXS = SXS, sstatus'rst = sstatus'rst}: sstatus 1185 1186fun sstatus_SXS_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, sstatus'rst} 1187 : sstatus, x') = 1188 {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = SSD, 1189 SXS = x', sstatus'rst = sstatus'rst}: sstatus 1190 1191fun sstatus_sstatus'rst_rupd ({SFS, SIE, SMPRV, SPIE, SPS, SSD, SXS, 1192 sstatus'rst}: sstatus, x') = 1193 {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, SSD = SSD, 1194 SXS = SXS, sstatus'rst = x'}: sstatus 1195 1196fun sip_SSIP_rupd ({SSIP, STIP, sip'rst}: sip, x') = 1197 {SSIP = x', STIP = STIP, sip'rst = sip'rst}: sip 1198 1199fun sip_STIP_rupd ({SSIP, STIP, sip'rst}: sip, x') = 1200 {SSIP = SSIP, STIP = x', sip'rst = sip'rst}: sip 1201 1202fun sip_sip'rst_rupd ({SSIP, STIP, sip'rst}: sip, x') = 1203 {SSIP = SSIP, STIP = STIP, sip'rst = x'}: sip 1204 1205fun sie_SSIE_rupd ({SSIE, STIE, sie'rst}: sie, x') = 1206 {SSIE = x', STIE = STIE, sie'rst = sie'rst}: sie 1207 1208fun sie_STIE_rupd ({SSIE, STIE, sie'rst}: sie, x') = 1209 {SSIE = SSIE, STIE = x', sie'rst = sie'rst}: sie 1210 1211fun sie_sie'rst_rupd ({SSIE, STIE, sie'rst}: sie, x') = 1212 {SSIE = SSIE, STIE = STIE, sie'rst = x'}: sie 1213 1214fun SupervisorCSR_sasid_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1215 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1216 {sasid = x', sbadaddr = sbadaddr, scause = scause, sepc = sepc, 1217 sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, 1218 stimecmp = stimecmp, stvec = stvec}: SupervisorCSR 1219 1220fun SupervisorCSR_sbadaddr_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1221 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1222 {sasid = sasid, sbadaddr = x', scause = scause, sepc = sepc, 1223 sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, 1224 stimecmp = stimecmp, stvec = stvec}: SupervisorCSR 1225 1226fun SupervisorCSR_scause_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1227 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1228 {sasid = sasid, sbadaddr = sbadaddr, scause = x', sepc = sepc, 1229 sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, 1230 stimecmp = stimecmp, stvec = stvec}: SupervisorCSR 1231 1232fun SupervisorCSR_sepc_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1233 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1234 {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = x', 1235 sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, 1236 stimecmp = stimecmp, stvec = stvec}: SupervisorCSR 1237 1238fun SupervisorCSR_sptbr_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1239 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1240 {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, 1241 sptbr = x', sscratch = sscratch, stime_delta = stime_delta, 1242 stimecmp = stimecmp, stvec = stvec}: SupervisorCSR 1243 1244fun SupervisorCSR_sscratch_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1245 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1246 {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, 1247 sptbr = sptbr, sscratch = x', stime_delta = stime_delta, 1248 stimecmp = stimecmp, stvec = stvec}: SupervisorCSR 1249 1250fun SupervisorCSR_stime_delta_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1251 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1252 {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, 1253 sptbr = sptbr, sscratch = sscratch, stime_delta = x', 1254 stimecmp = stimecmp, stvec = stvec}: SupervisorCSR 1255 1256fun SupervisorCSR_stimecmp_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1257 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1258 {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, 1259 sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, 1260 stimecmp = x', stvec = stvec}: SupervisorCSR 1261 1262fun SupervisorCSR_stvec_rupd ({sasid, sbadaddr, scause, sepc, sptbr, 1263 sscratch, stime_delta, stimecmp, stvec}: SupervisorCSR, x') = 1264 {sasid = sasid, sbadaddr = sbadaddr, scause = scause, sepc = sepc, 1265 sptbr = sptbr, sscratch = sscratch, stime_delta = stime_delta, 1266 stimecmp = stimecmp, stvec = x'}: SupervisorCSR 1267 1268fun FPCSR_DZ_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = 1269 {DZ = x', FRM = FRM, NV = NV, NX = NX, OF = OF, UF = UF, 1270 fpcsr'rst = fpcsr'rst}: FPCSR 1271 1272fun FPCSR_FRM_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = 1273 {DZ = DZ, FRM = x', NV = NV, NX = NX, OF = OF, UF = UF, 1274 fpcsr'rst = fpcsr'rst}: FPCSR 1275 1276fun FPCSR_NV_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = 1277 {DZ = DZ, FRM = FRM, NV = x', NX = NX, OF = OF, UF = UF, 1278 fpcsr'rst = fpcsr'rst}: FPCSR 1279 1280fun FPCSR_NX_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = 1281 {DZ = DZ, FRM = FRM, NV = NV, NX = x', OF = OF, UF = UF, 1282 fpcsr'rst = fpcsr'rst}: FPCSR 1283 1284fun FPCSR_OF_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = 1285 {DZ = DZ, FRM = FRM, NV = NV, NX = NX, OF = x', UF = UF, 1286 fpcsr'rst = fpcsr'rst}: FPCSR 1287 1288fun FPCSR_UF_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst}: FPCSR, x') = 1289 {DZ = DZ, FRM = FRM, NV = NV, NX = NX, OF = OF, UF = x', 1290 fpcsr'rst = fpcsr'rst}: FPCSR 1291 1292fun FPCSR_fpcsr'rst_rupd ({DZ, FRM, NV, NX, OF, UF, fpcsr'rst} 1293 : FPCSR, x') = 1294 {DZ = DZ, FRM = FRM, NV = NV, NX = NX, OF = OF, UF = UF, fpcsr'rst = x'} 1295 : FPCSR 1296 1297fun UserCSR_cycle_delta_rupd ({cycle_delta, fpcsr, instret_delta, 1298 time_delta}: UserCSR, x') = 1299 {cycle_delta = x', fpcsr = fpcsr, instret_delta = instret_delta, 1300 time_delta = time_delta}: UserCSR 1301 1302fun UserCSR_fpcsr_rupd ({cycle_delta, fpcsr, instret_delta, time_delta} 1303 : UserCSR, x') = 1304 {cycle_delta = cycle_delta, fpcsr = x', instret_delta = instret_delta, 1305 time_delta = time_delta}: UserCSR 1306 1307fun UserCSR_instret_delta_rupd ({cycle_delta, fpcsr, instret_delta, 1308 time_delta}: UserCSR, x') = 1309 {cycle_delta = cycle_delta, fpcsr = fpcsr, instret_delta = x', 1310 time_delta = time_delta}: UserCSR 1311 1312fun UserCSR_time_delta_rupd ({cycle_delta, fpcsr, instret_delta, 1313 time_delta}: UserCSR, x') = 1314 {cycle_delta = cycle_delta, fpcsr = fpcsr, 1315 instret_delta = instret_delta, time_delta = x'}: UserCSR 1316 1317fun SynchronousTrap_badaddr_rupd ({badaddr, trap}: SynchronousTrap, x') = 1318 {badaddr = x', trap = trap}: SynchronousTrap 1319 1320fun SynchronousTrap_trap_rupd ({badaddr, trap}: SynchronousTrap, x') = 1321 {badaddr = badaddr, trap = x'}: SynchronousTrap 1322 1323fun StateDelta_addr_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1324 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1325 {addr = x', data1 = data1, data2 = data2, exc_taken = exc_taken, 1326 fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, 1327 st_width = st_width}: StateDelta 1328 1329fun StateDelta_data1_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1330 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1331 {addr = addr, data1 = x', data2 = data2, exc_taken = exc_taken, 1332 fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, 1333 st_width = st_width}: StateDelta 1334 1335fun StateDelta_data2_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1336 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1337 {addr = addr, data1 = data1, data2 = x', exc_taken = exc_taken, 1338 fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, 1339 st_width = st_width}: StateDelta 1340 1341fun StateDelta_exc_taken_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1342 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1343 {addr = addr, data1 = data1, data2 = data2, exc_taken = x', 1344 fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, 1345 st_width = st_width}: StateDelta 1346 1347fun StateDelta_fetch_exc_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1348 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1349 {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, 1350 fetch_exc = x', fp_data = fp_data, pc = pc, rinstr = rinstr, 1351 st_width = st_width}: StateDelta 1352 1353fun StateDelta_fp_data_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1354 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1355 {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, 1356 fetch_exc = fetch_exc, fp_data = x', pc = pc, rinstr = rinstr, 1357 st_width = st_width}: StateDelta 1358 1359fun StateDelta_pc_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1360 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1361 {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, 1362 fetch_exc = fetch_exc, fp_data = fp_data, pc = x', rinstr = rinstr, 1363 st_width = st_width}: StateDelta 1364 1365fun StateDelta_rinstr_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1366 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1367 {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, 1368 fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = x', 1369 st_width = st_width}: StateDelta 1370 1371fun StateDelta_st_width_rupd ({addr, data1, data2, exc_taken, fetch_exc, 1372 fp_data, pc, rinstr, st_width}: StateDelta, x') = 1373 {addr = addr, data1 = data1, data2 = data2, exc_taken = exc_taken, 1374 fetch_exc = fetch_exc, fp_data = fp_data, pc = pc, rinstr = rinstr, 1375 st_width = x'}: StateDelta 1376 1377fun SV_PTE_PTE_D_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, 1378 sv_pte'rst}: SV_PTE, x') = 1379 {PTE_D = x', PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, 1380 PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE 1381 1382fun SV_PTE_PTE_PPNi_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, 1383 sv_pte'rst}: SV_PTE, x') = 1384 {PTE_D = PTE_D, PTE_PPNi = x', PTE_R = PTE_R, PTE_SW = PTE_SW, 1385 PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE 1386 1387fun SV_PTE_PTE_R_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, 1388 sv_pte'rst}: SV_PTE, x') = 1389 {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = x', PTE_SW = PTE_SW, 1390 PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE 1391 1392fun SV_PTE_PTE_SW_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, 1393 sv_pte'rst}: SV_PTE, x') = 1394 {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = x', 1395 PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE 1396 1397fun SV_PTE_PTE_T_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, 1398 sv_pte'rst}: SV_PTE, x') = 1399 {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, 1400 PTE_T = x', PTE_V = PTE_V, sv_pte'rst = sv_pte'rst}: SV_PTE 1401 1402fun SV_PTE_PTE_V_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, 1403 sv_pte'rst}: SV_PTE, x') = 1404 {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, 1405 PTE_T = PTE_T, PTE_V = x', sv_pte'rst = sv_pte'rst}: SV_PTE 1406 1407fun SV_PTE_sv_pte'rst_rupd ({PTE_D, PTE_PPNi, PTE_R, PTE_SW, PTE_T, PTE_V, 1408 sv_pte'rst}: SV_PTE, x') = 1409 {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, 1410 PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = x'}: SV_PTE 1411 1412fun SV_Vaddr_Sv_PgOfs_rupd ({Sv_PgOfs, Sv_VPNi, sv_vaddr'rst} 1413 : SV_Vaddr, x') = 1414 {Sv_PgOfs = x', Sv_VPNi = Sv_VPNi, sv_vaddr'rst = sv_vaddr'rst} 1415 : SV_Vaddr 1416 1417fun SV_Vaddr_Sv_VPNi_rupd ({Sv_PgOfs, Sv_VPNi, sv_vaddr'rst} 1418 : SV_Vaddr, x') = 1419 {Sv_PgOfs = Sv_PgOfs, Sv_VPNi = x', sv_vaddr'rst = sv_vaddr'rst} 1420 : SV_Vaddr 1421 1422fun SV_Vaddr_sv_vaddr'rst_rupd ({Sv_PgOfs, Sv_VPNi, sv_vaddr'rst} 1423 : SV_Vaddr, x') = 1424 {Sv_PgOfs = Sv_PgOfs, Sv_VPNi = Sv_VPNi, sv_vaddr'rst = x'}: SV_Vaddr 1425 1426fun TLBEntry_age_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, 1427 vAddrMask, vMatchMask}: TLBEntry, x') = 1428 {age = x', asid = asid, global = global, pAddr = pAddr, pte = pte, 1429 pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, 1430 vMatchMask = vMatchMask}: TLBEntry 1431 1432fun TLBEntry_asid_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, 1433 vAddrMask, vMatchMask}: TLBEntry, x') = 1434 {age = age, asid = x', global = global, pAddr = pAddr, pte = pte, 1435 pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, 1436 vMatchMask = vMatchMask}: TLBEntry 1437 1438fun TLBEntry_global_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, 1439 vAddrMask, vMatchMask}: TLBEntry, x') = 1440 {age = age, asid = asid, global = x', pAddr = pAddr, pte = pte, 1441 pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, 1442 vMatchMask = vMatchMask}: TLBEntry 1443 1444fun TLBEntry_pAddr_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, 1445 vAddrMask, vMatchMask}: TLBEntry, x') = 1446 {age = age, asid = asid, global = global, pAddr = x', pte = pte, 1447 pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, 1448 vMatchMask = vMatchMask}: TLBEntry 1449 1450fun TLBEntry_pte_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, 1451 vAddrMask, vMatchMask}: TLBEntry, x') = 1452 {age = age, asid = asid, global = global, pAddr = pAddr, pte = x', 1453 pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, 1454 vMatchMask = vMatchMask}: TLBEntry 1455 1456fun TLBEntry_pteAddr_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, 1457 vAddrMask, vMatchMask}: TLBEntry, x') = 1458 {age = age, asid = asid, global = global, pAddr = pAddr, pte = pte, 1459 pteAddr = x', vAddr = vAddr, vAddrMask = vAddrMask, 1460 vMatchMask = vMatchMask}: TLBEntry 1461 1462fun TLBEntry_vAddr_rupd ({age, asid, global, pAddr, pte, pteAddr, vAddr, 1463 vAddrMask, vMatchMask}: TLBEntry, x') = 1464 {age = age, asid = asid, global = global, pAddr = pAddr, pte = pte, 1465 pteAddr = pteAddr, vAddr = x', vAddrMask = vAddrMask, 1466 vMatchMask = vMatchMask}: TLBEntry 1467 1468fun TLBEntry_vAddrMask_rupd ({age, asid, global, pAddr, pte, pteAddr, 1469 vAddr, vAddrMask, vMatchMask}: TLBEntry, x') = 1470 {age = age, asid = asid, global = global, pAddr = pAddr, pte = pte, 1471 pteAddr = pteAddr, vAddr = vAddr, vAddrMask = x', 1472 vMatchMask = vMatchMask}: TLBEntry 1473 1474fun TLBEntry_vMatchMask_rupd ({age, asid, global, pAddr, pte, pteAddr, 1475 vAddr, vAddrMask, vMatchMask}: TLBEntry, x') = 1476 {age = age, asid = asid, global = global, pAddr = pAddr, pte = pte, 1477 pteAddr = pteAddr, vAddr = vAddr, vAddrMask = vAddrMask, 1478 vMatchMask = x'}: TLBEntry 1479 1480(* ------------------------------------------------------------------------- 1481 Exceptions 1482 ------------------------------------------------------------------------- *) 1483 1484exception INTERNAL_ERROR of string 1485 1486exception UNDEFINED of string 1487 1488(* ------------------------------------------------------------------------- 1489 Global variables (state) 1490 ------------------------------------------------------------------------- *) 1491 1492val MEM8 = ref (Map.mkMap(SOME 18446744073709551616,BitsN.B(0x0,8))) 1493 : (BitsN.nbit Map.map) ref 1494 1495val c_ExitCode = ref (Map.mkMap(SOME 256,BitsN.B(0x0,64))) 1496 : (BitsN.nbit Map.map) ref 1497 1498val c_HCSR = ref 1499 (Map.mkMap 1500 (SOME 256, 1501 {hbadaddr = BitsN.B(0x0,64), 1502 hcause = 1503 {EC = BitsN.B(0x0,4), Int = false, mcause'rst = BitsN.B(0x0,59)}, 1504 hepc = BitsN.B(0x0,64), hscratch = BitsN.B(0x0,64), 1505 hstatus = 1506 {MFS = BitsN.B(0x0,2), MIE = false, MIE1 = false, MIE2 = false, 1507 MIE3 = false, MMPRV = false, MPRV = BitsN.B(0x0,2), 1508 MPRV1 = BitsN.B(0x0,2), MPRV2 = BitsN.B(0x0,2), 1509 MPRV3 = BitsN.B(0x0,2), MSD = false, MXS = BitsN.B(0x0,2), 1510 VM = BitsN.B(0x0,5), mstatus'rst = BitsN.B(0x0,41)}, 1511 htdeleg = 1512 {Exc_deleg = BitsN.B(0x0,16), Intr_deleg = BitsN.B(0x0,48)}, 1513 htime_delta = BitsN.B(0x0,64), htimecmp = BitsN.B(0x0,64), 1514 htvec = BitsN.B(0x0,64)})): (HypervisorCSR Map.map) ref 1515 1516val c_MCSR = ref 1517 (Map.mkMap 1518 (SOME 256, 1519 {mbadaddr = BitsN.B(0x0,64), mbase = BitsN.B(0x0,64), 1520 mbound = BitsN.B(0x0,64), 1521 mcause = 1522 {EC = BitsN.B(0x0,4), Int = false, mcause'rst = BitsN.B(0x0,59)}, 1523 mcpuid = 1524 {ArchBase = BitsN.B(0x0,2), I = false, M = false, S = false, 1525 U = false, mcpuid'rst = BitsN.B(0x0,58)}, 1526 mdbase = BitsN.B(0x0,64), mdbound = BitsN.B(0x0,64), 1527 mepc = BitsN.B(0x0,64), mfromhost = BitsN.B(0x0,64), 1528 mhartid = BitsN.B(0x0,64), mibase = BitsN.B(0x0,64), 1529 mibound = BitsN.B(0x0,64), 1530 mie = 1531 {HSIE = false, HTIE = false, MSIE = false, MTIE = false, 1532 SSIE = false, STIE = false, mie'rst = BitsN.B(0x0,58)}, 1533 mimpid = {RVImpl = BitsN.B(0x0,48), RVSource = BitsN.B(0x0,16)}, 1534 mip = 1535 {HSIP = false, HTIP = false, MSIP = false, MTIP = false, 1536 SSIP = false, STIP = false, mip'rst = BitsN.B(0x0,58)}, 1537 mscratch = BitsN.B(0x0,64), 1538 mstatus = 1539 {MFS = BitsN.B(0x0,2), MIE = false, MIE1 = false, MIE2 = false, 1540 MIE3 = false, MMPRV = false, MPRV = BitsN.B(0x0,2), 1541 MPRV1 = BitsN.B(0x0,2), MPRV2 = BitsN.B(0x0,2), 1542 MPRV3 = BitsN.B(0x0,2), MSD = false, MXS = BitsN.B(0x0,2), 1543 VM = BitsN.B(0x0,5), mstatus'rst = BitsN.B(0x0,41)}, 1544 mtdeleg = 1545 {Exc_deleg = BitsN.B(0x0,16), Intr_deleg = BitsN.B(0x0,48)}, 1546 mtime_delta = BitsN.B(0x0,64), mtimecmp = BitsN.B(0x0,64), 1547 mtohost = BitsN.B(0x0,64), mtvec = BitsN.B(0x0,64)})) 1548 : (MachineCSR Map.map) ref 1549 1550val c_NextFetch = ref (Map.mkMap(SOME 256,NONE)) 1551 : ((TransferControl option) Map.map) ref 1552 1553val c_PC = ref (Map.mkMap(SOME 256,BitsN.B(0x0,64))) 1554 : (BitsN.nbit Map.map) ref 1555 1556val c_ReserveLoad = ref (Map.mkMap(SOME 256,NONE)) 1557 : ((BitsN.nbit option) Map.map) ref 1558 1559val c_SCSR = ref 1560 (Map.mkMap 1561 (SOME 256, 1562 {sasid = BitsN.B(0x0,64), sbadaddr = BitsN.B(0x0,64), 1563 scause = 1564 {EC = BitsN.B(0x0,4), Int = false, mcause'rst = BitsN.B(0x0,59)}, 1565 sepc = BitsN.B(0x0,64), sptbr = BitsN.B(0x0,64), 1566 sscratch = BitsN.B(0x0,64), stime_delta = BitsN.B(0x0,64), 1567 stimecmp = BitsN.B(0x0,64), stvec = BitsN.B(0x0,64)})) 1568 : (SupervisorCSR Map.map) ref 1569 1570val c_UCSR = ref 1571 (Map.mkMap 1572 (SOME 256, 1573 {cycle_delta = BitsN.B(0x0,64), 1574 fpcsr = 1575 {DZ = false, FRM = BitsN.B(0x0,3), NV = false, NX = false, 1576 OF = false, UF = false, fpcsr'rst = BitsN.B(0x0,24)}, 1577 instret_delta = BitsN.B(0x0,64), time_delta = BitsN.B(0x0,64)})) 1578 : (UserCSR Map.map) ref 1579 1580val c_cycles = ref (Map.mkMap(SOME 256,BitsN.B(0x0,64))) 1581 : (BitsN.nbit Map.map) ref 1582 1583val c_fpr = ref (Map.mkMap(SOME 256,Map.mkMap(SOME 32,BitsN.B(0x0,64)))) 1584 : ((BitsN.nbit Map.map) Map.map) ref 1585 1586val c_gpr = ref (Map.mkMap(SOME 256,Map.mkMap(SOME 32,BitsN.B(0x0,64)))) 1587 : ((BitsN.nbit Map.map) Map.map) ref 1588 1589val c_instret = ref (Map.mkMap(SOME 256,BitsN.B(0x0,64))) 1590 : (BitsN.nbit Map.map) ref 1591 1592val c_tlb = ref (Map.mkMap(SOME 256,Map.mkMap(SOME 16,NONE))) 1593 : (((TLBEntry option) Map.map) Map.map) ref 1594 1595val c_update = ref 1596 (Map.mkMap 1597 (SOME 256, 1598 {addr = NONE, data1 = NONE, data2 = NONE, exc_taken = false, 1599 fetch_exc = false, fp_data = NONE, pc = BitsN.B(0x0,64), 1600 rinstr = BitsN.B(0x0,32), st_width = NONE})) 1601 : (StateDelta Map.map) ref 1602 1603val clock = ref (BitsN.B(0x0,64)): BitsN.nbit ref 1604 1605val done = ref (false): bool ref 1606 1607val log = ref ([]): ((Nat.nat * string) list) ref 1608 1609val procID = ref (BitsN.B(0x0,8)): BitsN.nbit ref 1610 1611val totalCore = ref (0): Nat.nat ref 1612 1613(* ------------------------------------------------------------------------- 1614 Main specification 1615 ------------------------------------------------------------------------- *) 1616 1617local 1618 fun tuple'32 [t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16, 1619 t17,t18,t19,t20,t21,t22,t23,t24,t25,t26,t27,t28,t29,t30, 1620 t31] = 1621 (t0, 1622 (t1, 1623 (t2, 1624 (t3, 1625 (t4, 1626 (t5, 1627 (t6, 1628 (t7, 1629 (t8, 1630 (t9, 1631 (t10, 1632 (t11, 1633 (t12, 1634 (t13, 1635 (t14, 1636 (t15, 1637 (t16, 1638 (t17, 1639 (t18, 1640 (t19, 1641 (t20, 1642 (t21, 1643 (t22, 1644 (t23, 1645 (t24,(t25,(t26,(t27,(t28,(t29,(t30,t31))))))))))))))))))))))))))))))) 1646 | tuple'32 (_: bool list) = raise Fail "tuple'32" 1647in 1648 val boolify'32 = tuple'32 o BitsN.toList 1649end 1650 1651val ASID_SIZE = 6 1652 1653val PAGESIZE_BITS = 12 1654 1655val LEVEL_BITS = 9 1656 1657val BYTE = BitsN.B(0x0,3) 1658 1659val HALFWORD = BitsN.B(0x1,3) 1660 1661val WORD = BitsN.B(0x3,3) 1662 1663val DOUBLEWORD = BitsN.B(0x7,3) 1664 1665fun archBase a = 1666 case a of 1667 RV32I => BitsN.B(0x0,2) 1668 | RV64I => BitsN.B(0x2,2) 1669 | RV128I => BitsN.B(0x3,2); 1670 1671fun architecture ab = 1672 case ab of 1673 BitsN.B(0x0,_) => RV32I 1674 | BitsN.B(0x2,_) => RV64I 1675 | BitsN.B(0x3,_) => RV128I 1676 | _ => 1677 raise UNDEFINED 1678 ("Unknown architecture: " ^ (Nat.toString(BitsN.toNat ab))); 1679 1680fun archName a = 1681 case a of RV32I => "RV32I" | RV64I => "RV64I" | RV128I => "RV128I"; 1682 1683fun privLevel p = 1684 case p of 1685 User => BitsN.B(0x0,2) 1686 | Supervisor => BitsN.B(0x1,2) 1687 | Hypervisor => BitsN.B(0x2,2) 1688 | Machine => BitsN.B(0x3,2); 1689 1690fun privilege p = 1691 case p of 1692 BitsN.B(0x0,_) => User 1693 | BitsN.B(0x1,_) => Supervisor 1694 | BitsN.B(0x2,_) => Hypervisor 1695 | BitsN.B(0x3,_) => Machine 1696 | _ => raise General.Bind; 1697 1698fun privName p = 1699 case p of 1700 User => "U" 1701 | Supervisor => "S" 1702 | Hypervisor => "H" 1703 | Machine => "M"; 1704 1705fun vmType vm = 1706 case vm of 1707 BitsN.B(0x0,_) => Mbare 1708 | BitsN.B(0x1,_) => Mbb 1709 | BitsN.B(0x2,_) => Mbbid 1710 | BitsN.B(0x8,_) => Sv32 1711 | BitsN.B(0x9,_) => Sv39 1712 | BitsN.B(0xA,_) => Sv48 1713 | BitsN.B(0xB,_) => Sv57 1714 | BitsN.B(0xC,_) => Sv64 1715 | _ => 1716 raise UNDEFINED 1717 ("Unknown address translation mode: " 1718 ^ 1719 (Nat.toString(BitsN.toNat vm))); 1720 1721fun isValidVM vm = 1722 case vm of 1723 BitsN.B(0x0,_) => true 1724 | BitsN.B(0x1,_) => true 1725 | BitsN.B(0x2,_) => true 1726 | BitsN.B(0x8,_) => true 1727 | BitsN.B(0x9,_) => true 1728 | BitsN.B(0xA,_) => true 1729 | BitsN.B(0xB,_) => true 1730 | BitsN.B(0xC,_) => true 1731 | _ => false; 1732 1733fun vmMode vm = 1734 case vm of 1735 Mbare => BitsN.B(0x0,5) 1736 | Mbb => BitsN.B(0x1,5) 1737 | Mbbid => BitsN.B(0x2,5) 1738 | Sv32 => BitsN.B(0x8,5) 1739 | Sv39 => BitsN.B(0x9,5) 1740 | Sv48 => BitsN.B(0xA,5) 1741 | Sv57 => BitsN.B(0xB,5) 1742 | Sv64 => BitsN.B(0xC,5); 1743 1744fun vmModeName vm = 1745 case vm of 1746 Mbare => "Mbare" 1747 | Mbb => "Mbb" 1748 | Mbbid => "Mbbid" 1749 | Sv32 => "Sv32" 1750 | Sv39 => "Sv39" 1751 | Sv48 => "Sv48" 1752 | Sv57 => "Sv57" 1753 | Sv64 => "Sv64"; 1754 1755fun ext_status e = 1756 case e of 1757 Off => BitsN.B(0x0,2) 1758 | Initial => BitsN.B(0x1,2) 1759 | Clean => BitsN.B(0x2,2) 1760 | Dirty => BitsN.B(0x3,2); 1761 1762fun extStatus e = 1763 case e of 1764 BitsN.B(0x0,_) => Off 1765 | BitsN.B(0x1,_) => Initial 1766 | BitsN.B(0x2,_) => Clean 1767 | BitsN.B(0x3,_) => Dirty 1768 | _ => raise General.Bind; 1769 1770fun extStatusName e = 1771 case e of 1772 Off => "Off" 1773 | Initial => "Initial" 1774 | Clean => "Clean" 1775 | Dirty => "Dirty"; 1776 1777fun interruptIndex i = 1778 case i of Software => BitsN.B(0x0,4) | Timer => BitsN.B(0x1,4); 1779 1780fun excCode e = 1781 case e of 1782 Fetch_Misaligned => BitsN.B(0x0,4) 1783 | Fetch_Fault => BitsN.B(0x1,4) 1784 | Illegal_Instr => BitsN.B(0x2,4) 1785 | Breakpoint => BitsN.B(0x3,4) 1786 | Load_Fault => BitsN.B(0x5,4) 1787 | AMO_Misaligned => BitsN.B(0x6,4) 1788 | Store_AMO_Fault => BitsN.B(0x7,4) 1789 | UMode_Env_Call => BitsN.B(0x8,4) 1790 | SMode_Env_Call => BitsN.B(0x9,4) 1791 | HMode_Env_Call => BitsN.B(0xA,4) 1792 | MMode_Env_Call => BitsN.B(0xB,4); 1793 1794fun excType e = 1795 case e of 1796 BitsN.B(0x0,_) => Fetch_Misaligned 1797 | BitsN.B(0x1,_) => Fetch_Fault 1798 | BitsN.B(0x2,_) => Illegal_Instr 1799 | BitsN.B(0x3,_) => Breakpoint 1800 | BitsN.B(0x5,_) => Load_Fault 1801 | BitsN.B(0x6,_) => AMO_Misaligned 1802 | BitsN.B(0x7,_) => Store_AMO_Fault 1803 | BitsN.B(0x8,_) => UMode_Env_Call 1804 | BitsN.B(0x9,_) => SMode_Env_Call 1805 | BitsN.B(0xA,_) => HMode_Env_Call 1806 | BitsN.B(0xB,_) => MMode_Env_Call 1807 | _ => 1808 raise UNDEFINED 1809 ("Unknown exception: " ^ (Nat.toString(BitsN.toNat e))); 1810 1811fun excName e = 1812 case e of 1813 Fetch_Misaligned => "MISALIGNED_FETCH" 1814 | Fetch_Fault => "FAULT_FETCH" 1815 | Illegal_Instr => "ILLEGAL_INSTRUCTION" 1816 | Breakpoint => "BREAKPOINT" 1817 | Load_Fault => "FAULT_LOAD" 1818 | AMO_Misaligned => "MISALIGNED_AMO" 1819 | Store_AMO_Fault => "FAULT_STORE_AMO" 1820 | UMode_Env_Call => "U-EnvCall" 1821 | SMode_Env_Call => "S-EnvCall" 1822 | HMode_Env_Call => "H-EnvCall" 1823 | MMode_Env_Call => "M-EnvCall"; 1824 1825fun rec'mcpuid x = 1826 {ArchBase = BitsN.bits(63,62) x, I = BitsN.bit(x,8), 1827 M = BitsN.bit(x,12), S = BitsN.bit(x,18), U = BitsN.bit(x,20), 1828 mcpuid'rst = 1829 BitsN.concat 1830 [BitsN.bits(7,0) x,BitsN.bits(11,9) x,BitsN.bits(17,13) x, 1831 BitsN.bits(19,19) x,BitsN.bits(61,21) x]}; 1832 1833fun reg'mcpuid x = 1834 case x of 1835 {ArchBase = ArchBase, I = I, M = M, S = S, U = U, 1836 mcpuid'rst = mcpuid'rst} => 1837 BitsN.concat 1838 [ArchBase,BitsN.bits(40,0) mcpuid'rst,BitsN.fromBit U, 1839 BitsN.bits(41,41) mcpuid'rst,BitsN.fromBit S, 1840 BitsN.bits(46,42) mcpuid'rst,BitsN.fromBit M, 1841 BitsN.bits(49,47) mcpuid'rst,BitsN.fromBit I, 1842 BitsN.bits(57,50) mcpuid'rst]; 1843 1844fun write'rec'mcpuid (_,x) = reg'mcpuid x; 1845 1846fun write'reg'mcpuid (_,x) = rec'mcpuid x; 1847 1848fun rec'mimpid x = 1849 {RVImpl = BitsN.bits(63,16) x, RVSource = BitsN.bits(15,0) x}; 1850 1851fun reg'mimpid x = 1852 case x of 1853 {RVImpl = RVImpl, RVSource = RVSource} => BitsN.@@(RVImpl,RVSource); 1854 1855fun write'rec'mimpid (_,x) = reg'mimpid x; 1856 1857fun write'reg'mimpid (_,x) = rec'mimpid x; 1858 1859fun rec'mstatus x = 1860 {MFS = BitsN.bits(13,12) x, MIE = BitsN.bit(x,0), MIE1 = BitsN.bit(x,3), 1861 MIE2 = BitsN.bit(x,6), MIE3 = BitsN.bit(x,9), MMPRV = BitsN.bit(x,16), 1862 MPRV = BitsN.bits(2,1) x, MPRV1 = BitsN.bits(5,4) x, 1863 MPRV2 = BitsN.bits(8,7) x, MPRV3 = BitsN.bits(11,10) x, 1864 MSD = BitsN.bit(x,63), MXS = BitsN.bits(15,14) x, 1865 VM = BitsN.bits(21,17) x, mstatus'rst = BitsN.bits(62,22) x}; 1866 1867fun reg'mstatus x = 1868 case x of 1869 {MFS = MFS, MIE = MIE, MIE1 = MIE1, MIE2 = MIE2, MIE3 = MIE3, 1870 MMPRV = MMPRV, MPRV = MPRV, MPRV1 = MPRV1, MPRV2 = MPRV2, 1871 MPRV3 = MPRV3, MSD = MSD, MXS = MXS, VM = VM, 1872 mstatus'rst = mstatus'rst} => 1873 BitsN.concat 1874 [BitsN.fromBit MSD,mstatus'rst,VM,BitsN.fromBit MMPRV,MXS,MFS, 1875 MPRV3,BitsN.fromBit MIE3,MPRV2,BitsN.fromBit MIE2,MPRV1, 1876 BitsN.fromBit MIE1,MPRV,BitsN.fromBit MIE]; 1877 1878fun write'rec'mstatus (_,x) = reg'mstatus x; 1879 1880fun write'reg'mstatus (_,x) = rec'mstatus x; 1881 1882fun rec'mtdeleg x = 1883 {Exc_deleg = BitsN.bits(15,0) x, Intr_deleg = BitsN.bits(63,16) x}; 1884 1885fun reg'mtdeleg x = 1886 case x of 1887 {Exc_deleg = Exc_deleg, Intr_deleg = Intr_deleg} => 1888 BitsN.@@(Intr_deleg,Exc_deleg); 1889 1890fun write'rec'mtdeleg (_,x) = reg'mtdeleg x; 1891 1892fun write'reg'mtdeleg (_,x) = rec'mtdeleg x; 1893 1894fun rec'mip x = 1895 {HSIP = BitsN.bit(x,2), HTIP = BitsN.bit(x,6), MSIP = BitsN.bit(x,3), 1896 MTIP = BitsN.bit(x,7), SSIP = BitsN.bit(x,1), STIP = BitsN.bit(x,5), 1897 mip'rst = 1898 BitsN.concat[BitsN.bits(0,0) x,BitsN.bits(4,4) x,BitsN.bits(63,8) x]}; 1899 1900fun reg'mip x = 1901 case x of 1902 {HSIP = HSIP, HTIP = HTIP, MSIP = MSIP, MTIP = MTIP, SSIP = SSIP, 1903 STIP = STIP, mip'rst = mip'rst} => 1904 BitsN.concat 1905 [BitsN.bits(55,0) mip'rst,BitsN.fromBit MTIP,BitsN.fromBit HTIP, 1906 BitsN.fromBit STIP,BitsN.bits(56,56) mip'rst,BitsN.fromBit MSIP, 1907 BitsN.fromBit HSIP,BitsN.fromBit SSIP,BitsN.bits(57,57) mip'rst]; 1908 1909fun write'rec'mip (_,x) = reg'mip x; 1910 1911fun write'reg'mip (_,x) = rec'mip x; 1912 1913fun rec'mie x = 1914 {HSIE = BitsN.bit(x,2), HTIE = BitsN.bit(x,6), MSIE = BitsN.bit(x,3), 1915 MTIE = BitsN.bit(x,7), SSIE = BitsN.bit(x,1), STIE = BitsN.bit(x,5), 1916 mie'rst = 1917 BitsN.concat[BitsN.bits(0,0) x,BitsN.bits(4,4) x,BitsN.bits(63,8) x]}; 1918 1919fun reg'mie x = 1920 case x of 1921 {HSIE = HSIE, HTIE = HTIE, MSIE = MSIE, MTIE = MTIE, SSIE = SSIE, 1922 STIE = STIE, mie'rst = mie'rst} => 1923 BitsN.concat 1924 [BitsN.bits(55,0) mie'rst,BitsN.fromBit MTIE,BitsN.fromBit HTIE, 1925 BitsN.fromBit STIE,BitsN.bits(56,56) mie'rst,BitsN.fromBit MSIE, 1926 BitsN.fromBit HSIE,BitsN.fromBit SSIE,BitsN.bits(57,57) mie'rst]; 1927 1928fun write'rec'mie (_,x) = reg'mie x; 1929 1930fun write'reg'mie (_,x) = rec'mie x; 1931 1932fun rec'mcause x = 1933 {EC = BitsN.bits(3,0) x, Int = BitsN.bit(x,63), 1934 mcause'rst = BitsN.bits(62,4) x}; 1935 1936fun reg'mcause x = 1937 case x of 1938 {EC = EC, Int = Int, mcause'rst = mcause'rst} => 1939 BitsN.concat[BitsN.fromBit Int,mcause'rst,EC]; 1940 1941fun write'rec'mcause (_,x) = reg'mcause x; 1942 1943fun write'reg'mcause (_,x) = rec'mcause x; 1944 1945fun rec'sstatus x = 1946 {SFS = BitsN.bits(13,12) x, SIE = BitsN.bit(x,0), 1947 SMPRV = BitsN.bit(x,16), SPIE = BitsN.bit(x,3), SPS = BitsN.bit(x,4), 1948 SSD = BitsN.bit(x,63), SXS = BitsN.bits(15,14) x, 1949 sstatus'rst = 1950 BitsN.concat 1951 [BitsN.bits(2,1) x,BitsN.bits(11,5) x,BitsN.bits(62,17) x]}; 1952 1953fun reg'sstatus x = 1954 case x of 1955 {SFS = SFS, SIE = SIE, SMPRV = SMPRV, SPIE = SPIE, SPS = SPS, 1956 SSD = SSD, SXS = SXS, sstatus'rst = sstatus'rst} => 1957 BitsN.concat 1958 [BitsN.fromBit SSD,BitsN.bits(45,0) sstatus'rst, 1959 BitsN.fromBit SMPRV,SXS,SFS,BitsN.bits(52,46) sstatus'rst, 1960 BitsN.fromBit SPS,BitsN.fromBit SPIE, 1961 BitsN.bits(54,53) sstatus'rst,BitsN.fromBit SIE]; 1962 1963fun write'rec'sstatus (_,x) = reg'sstatus x; 1964 1965fun write'reg'sstatus (_,x) = rec'sstatus x; 1966 1967fun rec'sip x = 1968 {SSIP = BitsN.bit(x,1), STIP = BitsN.bit(x,5), 1969 sip'rst = 1970 BitsN.concat[BitsN.bits(0,0) x,BitsN.bits(4,2) x,BitsN.bits(63,6) x]}; 1971 1972fun reg'sip x = 1973 case x of 1974 {SSIP = SSIP, STIP = STIP, sip'rst = sip'rst} => 1975 BitsN.concat 1976 [BitsN.bits(57,0) sip'rst,BitsN.fromBit STIP, 1977 BitsN.bits(60,58) sip'rst,BitsN.fromBit SSIP, 1978 BitsN.bits(61,61) sip'rst]; 1979 1980fun write'rec'sip (_,x) = reg'sip x; 1981 1982fun write'reg'sip (_,x) = rec'sip x; 1983 1984fun rec'sie x = 1985 {SSIE = BitsN.bit(x,1), STIE = BitsN.bit(x,5), 1986 sie'rst = 1987 BitsN.concat[BitsN.bits(0,0) x,BitsN.bits(4,2) x,BitsN.bits(63,6) x]}; 1988 1989fun reg'sie x = 1990 case x of 1991 {SSIE = SSIE, STIE = STIE, sie'rst = sie'rst} => 1992 BitsN.concat 1993 [BitsN.bits(57,0) sie'rst,BitsN.fromBit STIE, 1994 BitsN.bits(60,58) sie'rst,BitsN.fromBit SSIE, 1995 BitsN.bits(61,61) sie'rst]; 1996 1997fun write'rec'sie (_,x) = reg'sie x; 1998 1999fun write'reg'sie (_,x) = rec'sie x; 2000 2001fun rec'FPCSR x = 2002 {DZ = BitsN.bit(x,3), FRM = BitsN.bits(7,5) x, NV = BitsN.bit(x,4), 2003 NX = BitsN.bit(x,0), OF = BitsN.bit(x,2), UF = BitsN.bit(x,1), 2004 fpcsr'rst = BitsN.bits(31,8) x}; 2005 2006fun reg'FPCSR x = 2007 case x of 2008 {DZ = DZ, FRM = FRM, NV = NV, NX = NX, OF = OF, UF = UF, 2009 fpcsr'rst = fpcsr'rst} => 2010 BitsN.concat 2011 [fpcsr'rst,FRM,BitsN.fromBit NV,BitsN.fromBit DZ, 2012 BitsN.fromBit OF,BitsN.fromBit UF,BitsN.fromBit NX]; 2013 2014fun write'rec'FPCSR (_,x) = reg'FPCSR x; 2015 2016fun write'reg'FPCSR (_,x) = rec'FPCSR x; 2017 2018fun lift_mip_sip mip = 2019 let 2020 val sip = ref (rec'sip(BitsN.B(0x0,64))) 2021 in 2022 ( sip := (sip_STIP_rupd((!sip),#STIP(mip : mip))) 2023 ; sip := (sip_SSIP_rupd((!sip),#SSIP(mip : mip))) 2024 ; (!sip) 2025 ) 2026 end; 2027 2028fun lift_mie_sie mie = 2029 let 2030 val sie = ref (rec'sie(BitsN.B(0x0,64))) 2031 in 2032 ( sie := (sie_STIE_rupd((!sie),#STIE(mie : mie))) 2033 ; sie := (sie_SSIE_rupd((!sie),#SSIE(mie : mie))) 2034 ; (!sie) 2035 ) 2036 end; 2037 2038fun lower_sip_mip (sip,mip) = 2039 let 2040 val m = ref mip 2041 in 2042 ( m := (mip_STIP_rupd((!m),#STIP(sip : sip))) 2043 ; m := (mip_SSIP_rupd((!m),#SSIP(sip : sip))) 2044 ; (!m) 2045 ) 2046 end; 2047 2048fun lower_sie_mie (sie,mie) = 2049 let 2050 val m = ref mie 2051 in 2052 ( m := (mie_STIE_rupd((!m),#STIE(sie : sie))) 2053 ; m := (mie_SSIE_rupd((!m),#SSIE(sie : sie))) 2054 ; (!m) 2055 ) 2056 end; 2057 2058fun update_mstatus (orig,v) = 2059 let 2060 val mt = ref orig 2061 in 2062 ( mt := (mstatus_MIE_rupd((!mt),#MIE(v : mstatus))) 2063 ; mt := (mstatus_MPRV_rupd((!mt),#MPRV(v : mstatus))) 2064 ; mt := (mstatus_MIE1_rupd((!mt),#MIE1(v : mstatus))) 2065 ; mt := (mstatus_MPRV1_rupd((!mt),#MPRV1(v : mstatus))) 2066 ; mt := (mstatus_MIE2_rupd((!mt),#MIE2(v : mstatus))) 2067 ; mt := (mstatus_MPRV2_rupd((!mt),#MPRV2(v : mstatus))) 2068 ; mt := (mstatus_MIE3_rupd((!mt),#MIE3(v : mstatus))) 2069 ; mt := (mstatus_MPRV3_rupd((!mt),#MPRV3(v : mstatus))) 2070 ; if isValidVM(#VM(v : mstatus)) 2071 then mt := (mstatus_VM_rupd((!mt),#VM(v : mstatus))) 2072 else () 2073 ; mt := (mstatus_MMPRV_rupd((!mt),#MMPRV(v : mstatus))) 2074 ; mt := (mstatus_MFS_rupd((!mt),#MFS(v : mstatus))) 2075 ; mt := (mstatus_MXS_rupd((!mt),#MXS(v : mstatus))) 2076 ; mt := 2077 (mstatus_MSD_rupd 2078 ((!mt), 2079 ((extStatus(#MXS(v : mstatus))) = Dirty) orelse 2080 ((extStatus(#MFS(v : mstatus))) = Dirty))) 2081 ; (!mt) 2082 ) 2083 end; 2084 2085fun lift_mstatus_sstatus mst = 2086 let 2087 val st = ref (rec'sstatus(BitsN.B(0x0,64))) 2088 in 2089 ( st := (sstatus_SMPRV_rupd((!st),#MMPRV(mst : mstatus))) 2090 ; st := (sstatus_SXS_rupd((!st),#MXS(mst : mstatus))) 2091 ; st := (sstatus_SFS_rupd((!st),#MFS(mst : mstatus))) 2092 ; st := 2093 (sstatus_SSD_rupd 2094 ((!st), 2095 ((extStatus(#MXS(mst : mstatus))) = Dirty) orelse 2096 ((extStatus(#MFS(mst : mstatus))) = Dirty))) 2097 ; st := 2098 (sstatus_SPS_rupd 2099 ((!st),not((privilege(#MPRV1(mst : mstatus))) = User))) 2100 ; st := (sstatus_SPIE_rupd((!st),#MIE1(mst : mstatus))) 2101 ; st := (sstatus_SIE_rupd((!st),#MIE(mst : mstatus))) 2102 ; (!st) 2103 ) 2104 end; 2105 2106fun lower_sstatus_mstatus (sst,mst) = 2107 let 2108 val mt = ref (rec'mstatus(reg'mstatus mst)) 2109 in 2110 ( mt := (mstatus_MMPRV_rupd((!mt),#SMPRV(sst : sstatus))) 2111 ; mt := (mstatus_MXS_rupd((!mt),#SXS(sst : sstatus))) 2112 ; mt := (mstatus_MFS_rupd((!mt),#SFS(sst : sstatus))) 2113 ; mt := 2114 (mstatus_MPRV1_rupd 2115 ((!mt), 2116 privLevel(if #SPS(sst : sstatus) then Supervisor else User))) 2117 ; mt := (mstatus_MIE1_rupd((!mt),#SPIE(sst : sstatus))) 2118 ; mt := (mstatus_MIE_rupd((!mt),#SIE(sst : sstatus))) 2119 ; update_mstatus(mst,(!mt)) 2120 ) 2121 end; 2122 2123fun popPrivilegeStack mst = 2124 let 2125 val st = ref mst 2126 in 2127 ( st := (mstatus_MIE_rupd((!st),#MIE1(mst : mstatus))) 2128 ; st := (mstatus_MPRV_rupd((!st),#MPRV1(mst : mstatus))) 2129 ; st := (mstatus_MIE1_rupd((!st),#MIE2(mst : mstatus))) 2130 ; st := (mstatus_MPRV1_rupd((!st),#MPRV2(mst : mstatus))) 2131 ; st := (mstatus_MIE2_rupd((!st),true)) 2132 ; st := (mstatus_MPRV2_rupd((!st),privLevel User)) 2133 ; (!st) 2134 ) 2135 end; 2136 2137fun pushPrivilegeStack (mst,p) = 2138 let 2139 val st = ref mst 2140 in 2141 ( st := (mstatus_MIE2_rupd((!st),#MIE1(mst : mstatus))) 2142 ; st := (mstatus_MPRV2_rupd((!st),#MPRV1(mst : mstatus))) 2143 ; st := (mstatus_MIE1_rupd((!st),#MIE(mst : mstatus))) 2144 ; st := (mstatus_MPRV1_rupd((!st),#MPRV(mst : mstatus))) 2145 ; st := (mstatus_MIE_rupd((!st),false)) 2146 ; st := (mstatus_MPRV_rupd((!st),privLevel p)) 2147 ; (!st) 2148 ) 2149 end; 2150 2151fun scheduleCore id = 2152 if Nat.<(id,(!totalCore)) then procID := (BitsN.fromNat(id,8)) else (); 2153 2154fun gpr n = 2155 let 2156 val m = Map.copy(Map.lookup((!c_gpr),BitsN.toNat (!procID))) 2157 in 2158 Map.lookup(m,BitsN.toNat n) 2159 end; 2160 2161fun write'gpr (value,n) = 2162 let 2163 val m = ref (Map.copy(Map.lookup((!c_gpr),BitsN.toNat (!procID)))) 2164 in 2165 ( m := (Map.update((!m),BitsN.toNat n,value)) 2166 ; c_gpr := (Map.update((!c_gpr),BitsN.toNat (!procID),Map.copy (!m))) 2167 ) 2168 end; 2169 2170fun fcsr () = 2171 #fpcsr((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR); 2172 2173fun write'fcsr value = 2174 ( let 2175 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2176 in 2177 c_UCSR := 2178 (Map.update 2179 ((!c_UCSR),BitsN.toNat (!procID),UserCSR_fpcsr_rupd(x0,value))) 2180 end 2181 ; let 2182 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2183 val x1 = #mstatus(x0 : MachineCSR) 2184 in 2185 c_MCSR := 2186 (Map.update 2187 ((!c_MCSR),BitsN.toNat (!procID), 2188 MachineCSR_mstatus_rupd 2189 (x0,mstatus_MFS_rupd(x1,ext_status Dirty)))) 2190 end 2191 ; let 2192 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2193 val x1 = #mstatus(x0 : MachineCSR) 2194 in 2195 c_MCSR := 2196 (Map.update 2197 ((!c_MCSR),BitsN.toNat (!procID), 2198 MachineCSR_mstatus_rupd(x0,mstatus_MSD_rupd(x1,true)))) 2199 end 2200 ); 2201 2202fun fpr n = 2203 let 2204 val m = Map.copy(Map.lookup((!c_fpr),BitsN.toNat (!procID))) 2205 in 2206 Map.lookup(m,BitsN.toNat n) 2207 end; 2208 2209fun write'fpr (value,n) = 2210 let 2211 val m = ref (Map.copy(Map.lookup((!c_fpr),BitsN.toNat (!procID)))) 2212 in 2213 ( m := (Map.update((!m),BitsN.toNat n,value)) 2214 ; c_fpr := (Map.update((!c_fpr),BitsN.toNat (!procID),Map.copy (!m))) 2215 ) 2216 end; 2217 2218fun PC () = Map.lookup((!c_PC),BitsN.toNat (!procID)); 2219 2220fun write'PC value = 2221 c_PC := (Map.update((!c_PC),BitsN.toNat (!procID),value)); 2222 2223fun UCSR () = Map.lookup((!c_UCSR),BitsN.toNat (!procID)); 2224 2225fun write'UCSR value = 2226 c_UCSR := (Map.update((!c_UCSR),BitsN.toNat (!procID),value)); 2227 2228fun SCSR () = Map.lookup((!c_SCSR),BitsN.toNat (!procID)); 2229 2230fun write'SCSR value = 2231 c_SCSR := (Map.update((!c_SCSR),BitsN.toNat (!procID),value)); 2232 2233fun HCSR () = Map.lookup((!c_HCSR),BitsN.toNat (!procID)); 2234 2235fun write'HCSR value = 2236 c_HCSR := (Map.update((!c_HCSR),BitsN.toNat (!procID),value)); 2237 2238fun MCSR () = Map.lookup((!c_MCSR),BitsN.toNat (!procID)); 2239 2240fun write'MCSR value = 2241 c_MCSR := (Map.update((!c_MCSR),BitsN.toNat (!procID),value)); 2242 2243fun NextFetch () = Map.lookup((!c_NextFetch),BitsN.toNat (!procID)); 2244 2245fun write'NextFetch value = 2246 c_NextFetch := (Map.update((!c_NextFetch),BitsN.toNat (!procID),value)); 2247 2248fun ReserveLoad () = Map.lookup((!c_ReserveLoad),BitsN.toNat (!procID)); 2249 2250fun write'ReserveLoad value = 2251 c_ReserveLoad := 2252 (Map.update((!c_ReserveLoad),BitsN.toNat (!procID),value)); 2253 2254fun ExitCode () = Map.lookup((!c_ExitCode),BitsN.toNat (!procID)); 2255 2256fun write'ExitCode value = 2257 c_ExitCode := (Map.update((!c_ExitCode),BitsN.toNat (!procID),value)); 2258 2259fun curArch () = 2260 architecture(#ArchBase((#mcpuid((MCSR ()) : MachineCSR)) : mcpuid)); 2261 2262fun in32BitMode () = (curArch ()) = RV32I; 2263 2264fun curPrivilege () = 2265 privilege(#MPRV((#mstatus((MCSR ()) : MachineCSR)) : mstatus)); 2266 2267fun curEPC () = 2268 case curPrivilege () of 2269 User => raise INTERNAL_ERROR "No EPC in U-mode" 2270 | Supervisor => #sepc((SCSR ()) : SupervisorCSR) 2271 | Hypervisor => #hepc((HCSR ()) : HypervisorCSR) 2272 | Machine => #mepc((MCSR ()) : MachineCSR); 2273 2274fun sendIPI core = 2275 let 2276 val id = BitsN.fromNat(BitsN.toNat core,8) 2277 in 2278 if Nat.<(BitsN.toNat id,(!totalCore)) 2279 then let 2280 val x0 = Map.lookup((!c_MCSR),BitsN.toNat id) 2281 val x1 = #mip(x0 : MachineCSR) 2282 in 2283 c_MCSR := 2284 (Map.update 2285 ((!c_MCSR),BitsN.toNat id, 2286 MachineCSR_mip_rupd(x0,mip_MSIP_rupd(x1,true)))) 2287 end 2288 else () 2289 end; 2290 2291fun rnd_mode_static rnd = 2292 case rnd of 2293 BitsN.B(0x0,_) => Option.SOME RNE 2294 | BitsN.B(0x1,_) => Option.SOME RTZ 2295 | BitsN.B(0x2,_) => Option.SOME RDN 2296 | BitsN.B(0x3,_) => Option.SOME RUP 2297 | BitsN.B(0x4,_) => Option.SOME RMM 2298 | BitsN.B(0x7,_) => Option.SOME RDYN 2299 | _ => NONE; 2300 2301fun rnd_mode_dynamic rnd = 2302 case rnd of 2303 BitsN.B(0x0,_) => Option.SOME RNE 2304 | BitsN.B(0x1,_) => Option.SOME RTZ 2305 | BitsN.B(0x2,_) => Option.SOME RDN 2306 | BitsN.B(0x3,_) => Option.SOME RUP 2307 | BitsN.B(0x4,_) => Option.SOME RMM 2308 | _ => NONE; 2309 2310fun l3round rnd = 2311 case rnd of 2312 RNE => Option.SOME IEEEReal.TO_NEAREST 2313 | RTZ => Option.SOME IEEEReal.TO_ZERO 2314 | RDN => Option.SOME IEEEReal.TO_NEGINF 2315 | RUP => Option.SOME IEEEReal.TO_POSINF 2316 | RMM => NONE 2317 | RDYN => NONE; 2318 2319fun round rnd = 2320 case rnd_mode_static rnd of 2321 Option.SOME RDYN => 2322 (case rnd_mode_dynamic(#FRM((fcsr ()) : FPCSR)) of 2323 Option.SOME frm => l3round frm 2324 | NONE => NONE) 2325 | Option.SOME frm => l3round frm 2326 | NONE => NONE; 2327 2328val RV32_CanonicalNan = BitsN.B(0x7FC00000,32) 2329 2330val RV64_CanonicalNan = BitsN.B(0x7FF8000000000000,64) 2331 2332fun FP32_IsSignalingNan x = 2333 ((BitsN.bits(30,23) x) = (BitsN.B(0xFF,8))) andalso 2334 (((BitsN.bit(x,22)) = false) andalso 2335 (not((BitsN.bits(21,0) x) = (BitsN.B(0x0,22))))); 2336 2337fun FP64_IsSignalingNan x = 2338 ((BitsN.bits(62,52) x) = (BitsN.B(0x7FF,11))) andalso 2339 (((BitsN.bit(x,51)) = false) andalso 2340 (not((BitsN.bits(50,0) x) = (BitsN.B(0x0,51))))); 2341 2342fun FP32_Sign x = BitsN.bit(x,31); 2343 2344fun FP64_Sign x = BitsN.bit(x,63); 2345 2346fun setFP_Invalid () = 2347 let val x = fcsr () in write'fcsr(FPCSR_NV_rupd(x,true)) end; 2348 2349fun setFP_DivZero () = 2350 let val x = fcsr () in write'fcsr(FPCSR_DZ_rupd(x,true)) end; 2351 2352fun setFP_Overflow () = 2353 let val x = fcsr () in write'fcsr(FPCSR_OF_rupd(x,true)) end; 2354 2355fun setFP_Underflow () = 2356 let val x = fcsr () in write'fcsr(FPCSR_OF_rupd(x,true)) end; 2357 2358fun setFP_Inexact () = 2359 let val x = fcsr () in write'fcsr(FPCSR_OF_rupd(x,true)) end; 2360 2361fun csrRW csr = BitsN.bits(11,10) csr; 2362 2363fun csrPR csr = BitsN.bits(9,8) csr; 2364 2365fun check_CSR_access (rw,(pr,(p,a))) = 2366 ((a = Read) orelse (not(rw = (BitsN.B(0x3,2))))) andalso 2367 (BitsN.>=+(privLevel p,pr)); 2368 2369fun is_CSR_defined csr = 2370 ((BitsN.>=(csr,BitsN.B(0x1,12))) andalso (BitsN.<=(csr,BitsN.B(0x3,12)))) orelse 2371 (((BitsN.>=(csr,BitsN.B(0xC00,12))) andalso 2372 (BitsN.<=(csr,BitsN.B(0xC02,12)))) orelse 2373 (((BitsN.>=(csr,BitsN.B(0xC80,12))) andalso 2374 ((BitsN.<=(csr,BitsN.B(0xC82,12))) andalso (in32BitMode ()))) orelse 2375 (((BitsN.>=(csr,BitsN.B(0x100,12))) andalso 2376 (BitsN.<=(csr,BitsN.B(0x101,12)))) orelse 2377 ((csr = (BitsN.B(0x104,12))) orelse 2378 ((csr = (BitsN.B(0x121,12))) orelse 2379 ((csr = (BitsN.B(0xD01,12))) orelse 2380 (((csr = (BitsN.B(0xD81,12))) andalso (in32BitMode ())) orelse 2381 (((BitsN.>=(csr,BitsN.B(0x140,12))) andalso 2382 (BitsN.<=(csr,BitsN.B(0x141,12)))) orelse 2383 ((csr = (BitsN.B(0x144,12))) orelse 2384 (((BitsN.>=(csr,BitsN.B(0xD42,12))) andalso 2385 (BitsN.<=(csr,BitsN.B(0xD43,12)))) orelse 2386 (((BitsN.>=(csr,BitsN.B(0x180,12))) andalso 2387 (BitsN.<=(csr,BitsN.B(0x181,12)))) orelse 2388 (((BitsN.>=(csr,BitsN.B(0x900,12))) andalso 2389 (BitsN.<=(csr,BitsN.B(0x902,12)))) orelse 2390 (((BitsN.>=(csr,BitsN.B(0x980,12))) andalso 2391 ((BitsN.<=(csr,BitsN.B(0x982,12))) andalso 2392 (in32BitMode ()))) orelse 2393 (((BitsN.>=(csr,BitsN.B(0xF00,12))) andalso 2394 (BitsN.<=(csr,BitsN.B(0xF01,12)))) orelse 2395 ((csr = (BitsN.B(0xF10,12))) orelse 2396 (((BitsN.>=(csr,BitsN.B(0x300,12))) andalso 2397 (BitsN.<=(csr,BitsN.B(0x302,12)))) orelse 2398 ((csr = (BitsN.B(0x304,12))) orelse 2399 ((csr = (BitsN.B(0x321,12))) orelse 2400 ((csr = (BitsN.B(0x701,12))) orelse 2401 (((csr = (BitsN.B(0x741,12))) andalso 2402 (in32BitMode ())) orelse 2403 (((BitsN.>=(csr,BitsN.B(0x340,12))) andalso 2404 (BitsN.<=(csr,BitsN.B(0x344,12)))) orelse 2405 (((BitsN.>=(csr,BitsN.B(0x380,12))) andalso 2406 (BitsN.<=(csr,BitsN.B(0x385,12)))) orelse 2407 ((BitsN.>=(csr,BitsN.B(0xB01,12))) orelse 2408 (((csr = (BitsN.B(0xB81,12))) andalso 2409 (in32BitMode ())) orelse 2410 ((BitsN.>=(csr,BitsN.B(0x780,12))) andalso 2411 ((BitsN.<=(csr,BitsN.B(0x783,12))) andalso 2412 (not(csr = (BitsN.B(0x782,12)))))))))))))))))))))))))))))); 2413 2414fun CSRMap csr = 2415 case csr of 2416 BitsN.B(0x1,_) => 2417 BitsN.zeroExtend 64 2418 (BitsN.bits(4,0) 2419 (reg'FPCSR 2420 (#fpcsr 2421 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) 2422 | BitsN.B(0x2,_) => 2423 BitsN.zeroExtend 64 2424 (#FRM 2425 ((#fpcsr 2426 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) : 2427 FPCSR)) 2428 | BitsN.B(0x3,_) => 2429 BitsN.zeroExtend 64 2430 (BitsN.bits(7,0) 2431 (reg'FPCSR 2432 (#fpcsr 2433 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) 2434 | BitsN.B(0xC00,_) => 2435 BitsN.+ 2436 (Map.lookup((!c_cycles),BitsN.toNat (!procID)), 2437 #cycle_delta 2438 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) 2439 | BitsN.B(0xC01,_) => 2440 BitsN.+ 2441 ((!clock), 2442 #time_delta 2443 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) 2444 | BitsN.B(0xC02,_) => 2445 BitsN.+ 2446 (Map.lookup((!c_instret),BitsN.toNat (!procID)), 2447 #instret_delta 2448 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) 2449 | BitsN.B(0xC80,_) => 2450 BitsN.signExtend 64 2451 (BitsN.bits(63,32) 2452 (BitsN.+ 2453 (Map.lookup((!c_cycles),BitsN.toNat (!procID)), 2454 #cycle_delta 2455 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) 2456 | BitsN.B(0xC81,_) => 2457 BitsN.signExtend 64 2458 (BitsN.bits(63,32) 2459 (BitsN.+ 2460 ((!clock), 2461 #time_delta 2462 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) 2463 | BitsN.B(0xC82,_) => 2464 BitsN.signExtend 64 2465 (BitsN.bits(63,32) 2466 (BitsN.+ 2467 (Map.lookup((!c_instret),BitsN.toNat (!procID)), 2468 #instret_delta 2469 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) 2470 | BitsN.B(0x100,_) => 2471 reg'sstatus 2472 (lift_mstatus_sstatus 2473 (#mstatus 2474 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR))) 2475 | BitsN.B(0x101,_) => 2476 #stvec((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) 2477 | BitsN.B(0x104,_) => 2478 reg'sie 2479 (lift_mie_sie 2480 (#mie 2481 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR))) 2482 | BitsN.B(0x121,_) => 2483 #stimecmp 2484 ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) 2485 | BitsN.B(0xD01,_) => 2486 BitsN.+ 2487 ((!clock), 2488 #stime_delta 2489 ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR)) 2490 | BitsN.B(0xD81,_) => 2491 BitsN.signExtend 64 2492 (BitsN.bits(63,32) 2493 (BitsN.+ 2494 ((!clock), 2495 #stime_delta 2496 ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : 2497 SupervisorCSR)))) 2498 | BitsN.B(0x140,_) => 2499 #sscratch 2500 ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) 2501 | BitsN.B(0x141,_) => 2502 #sepc((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) 2503 | BitsN.B(0xD42,_) => 2504 reg'mcause 2505 (#scause 2506 ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR)) 2507 | BitsN.B(0xD43,_) => 2508 #sbadaddr 2509 ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) 2510 | BitsN.B(0x144,_) => 2511 reg'sip 2512 (lift_mip_sip 2513 (#mip 2514 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR))) 2515 | BitsN.B(0x180,_) => 2516 #sptbr((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) 2517 | BitsN.B(0x181,_) => 2518 #sasid((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR) 2519 | BitsN.B(0x900,_) => 2520 BitsN.+ 2521 (Map.lookup((!c_cycles),BitsN.toNat (!procID)), 2522 #cycle_delta 2523 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) 2524 | BitsN.B(0x901,_) => 2525 BitsN.+ 2526 ((!clock), 2527 #time_delta 2528 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) 2529 | BitsN.B(0x902,_) => 2530 BitsN.+ 2531 (Map.lookup((!c_instret),BitsN.toNat (!procID)), 2532 #instret_delta 2533 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)) 2534 | BitsN.B(0x980,_) => 2535 BitsN.signExtend 64 2536 (BitsN.bits(63,32) 2537 (BitsN.+ 2538 (Map.lookup((!c_cycles),BitsN.toNat (!procID)), 2539 #cycle_delta 2540 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) 2541 | BitsN.B(0x981,_) => 2542 BitsN.signExtend 64 2543 (BitsN.bits(63,32) 2544 (BitsN.+ 2545 ((!clock), 2546 #time_delta 2547 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) 2548 | BitsN.B(0x982,_) => 2549 BitsN.signExtend 64 2550 (BitsN.bits(63,32) 2551 (BitsN.+ 2552 (Map.lookup((!c_instret),BitsN.toNat (!procID)), 2553 #instret_delta 2554 ((Map.lookup((!c_UCSR),BitsN.toNat (!procID))) : UserCSR)))) 2555 | BitsN.B(0x200,_) => 2556 reg'mstatus 2557 (#hstatus 2558 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) 2559 | BitsN.B(0x201,_) => 2560 #htvec((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) 2561 | BitsN.B(0x202,_) => 2562 reg'mtdeleg 2563 (#htdeleg 2564 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) 2565 | BitsN.B(0x221,_) => 2566 #htimecmp 2567 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) 2568 | BitsN.B(0xE01,_) => 2569 BitsN.+ 2570 ((!clock), 2571 #htime_delta 2572 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) 2573 | BitsN.B(0xE81,_) => 2574 BitsN.signExtend 64 2575 (BitsN.bits(63,32) 2576 (BitsN.+ 2577 ((!clock), 2578 #htime_delta 2579 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : 2580 HypervisorCSR)))) 2581 | BitsN.B(0x240,_) => 2582 #hscratch 2583 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) 2584 | BitsN.B(0x241,_) => 2585 #hepc((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) 2586 | BitsN.B(0x242,_) => 2587 reg'mcause 2588 (#hcause 2589 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) 2590 | BitsN.B(0x243,_) => 2591 #hbadaddr 2592 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR) 2593 | BitsN.B(0xA01,_) => 2594 BitsN.+ 2595 ((!clock), 2596 #stime_delta 2597 ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : SupervisorCSR)) 2598 | BitsN.B(0xA81,_) => 2599 BitsN.signExtend 64 2600 (BitsN.bits(63,32) 2601 (BitsN.+ 2602 ((!clock), 2603 #stime_delta 2604 ((Map.lookup((!c_SCSR),BitsN.toNat (!procID))) : 2605 SupervisorCSR)))) 2606 | BitsN.B(0xF00,_) => 2607 reg'mcpuid 2608 (#mcpuid 2609 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) 2610 | BitsN.B(0xF01,_) => 2611 reg'mimpid 2612 (#mimpid 2613 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) 2614 | BitsN.B(0xF10,_) => 2615 #mhartid((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2616 | BitsN.B(0x300,_) => 2617 reg'mstatus 2618 (#mstatus 2619 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) 2620 | BitsN.B(0x301,_) => 2621 #mtvec((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2622 | BitsN.B(0x302,_) => 2623 reg'mtdeleg 2624 (#mtdeleg 2625 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) 2626 | BitsN.B(0x304,_) => 2627 reg'mie 2628 (#mie((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) 2629 | BitsN.B(0x321,_) => 2630 #mtimecmp((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2631 | BitsN.B(0x701,_) => 2632 BitsN.+ 2633 ((!clock), 2634 #mtime_delta 2635 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) 2636 | BitsN.B(0x741,_) => 2637 BitsN.signExtend 64 2638 (BitsN.bits(63,32) 2639 (BitsN.+ 2640 ((!clock), 2641 #mtime_delta 2642 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : 2643 MachineCSR)))) 2644 | BitsN.B(0x340,_) => 2645 #mscratch((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2646 | BitsN.B(0x341,_) => 2647 #mepc((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2648 | BitsN.B(0x342,_) => 2649 reg'mcause 2650 (#mcause 2651 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) 2652 | BitsN.B(0x343,_) => 2653 #mbadaddr((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2654 | BitsN.B(0x344,_) => 2655 reg'mip 2656 (#mip((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR)) 2657 | BitsN.B(0x380,_) => 2658 #mbase((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2659 | BitsN.B(0x381,_) => 2660 #mbound((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2661 | BitsN.B(0x382,_) => 2662 #mibase((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2663 | BitsN.B(0x383,_) => 2664 #mibound((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2665 | BitsN.B(0x384,_) => 2666 #mdbase((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2667 | BitsN.B(0x385,_) => 2668 #mdbound((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2669 | BitsN.B(0xB01,_) => 2670 BitsN.+ 2671 ((!clock), 2672 #htime_delta 2673 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : HypervisorCSR)) 2674 | BitsN.B(0xB81,_) => 2675 BitsN.signExtend 64 2676 (BitsN.bits(63,32) 2677 (BitsN.+ 2678 ((!clock), 2679 #htime_delta 2680 ((Map.lookup((!c_HCSR),BitsN.toNat (!procID))) : 2681 HypervisorCSR)))) 2682 | BitsN.B(0x780,_) => 2683 #mtohost((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2684 | BitsN.B(0x781,_) => 2685 #mfromhost 2686 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : MachineCSR) 2687 | BitsN.B(0x783,_) => BitsN.B(0x0,64) 2688 | _ => 2689 raise UNDEFINED ("unexpected CSR read at " ^ (BitsN.toHexString csr)); 2690 2691fun write'CSRMap (value,csr) = 2692 case csr of 2693 BitsN.B(0x1,_) => 2694 ( let 2695 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2696 val x1 = #fpcsr(x0 : UserCSR) 2697 val w = reg'FPCSR x1 2698 in 2699 c_UCSR := 2700 (Map.update 2701 ((!c_UCSR),BitsN.toNat (!procID), 2702 UserCSR_fpcsr_rupd 2703 (x0, 2704 write'reg'FPCSR 2705 (x1, 2706 BitsN.bitFieldInsert(4,0) (w,BitsN.bits(4,0) value))))) 2707 end 2708 ; let 2709 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2710 val x1 = #mstatus(x0 : MachineCSR) 2711 in 2712 c_MCSR := 2713 (Map.update 2714 ((!c_MCSR),BitsN.toNat (!procID), 2715 MachineCSR_mstatus_rupd 2716 (x0,mstatus_MFS_rupd(x1,ext_status Dirty)))) 2717 end 2718 ; let 2719 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2720 val x1 = #mstatus(x0 : MachineCSR) 2721 in 2722 c_MCSR := 2723 (Map.update 2724 ((!c_MCSR),BitsN.toNat (!procID), 2725 MachineCSR_mstatus_rupd(x0,mstatus_MSD_rupd(x1,true)))) 2726 end 2727 ) 2728 | BitsN.B(0x2,_) => 2729 ( let 2730 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2731 val x1 = #fpcsr(x0 : UserCSR) 2732 in 2733 c_UCSR := 2734 (Map.update 2735 ((!c_UCSR),BitsN.toNat (!procID), 2736 UserCSR_fpcsr_rupd 2737 (x0,FPCSR_FRM_rupd(x1,BitsN.bits(2,0) value)))) 2738 end 2739 ; let 2740 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2741 val x1 = #mstatus(x0 : MachineCSR) 2742 in 2743 c_MCSR := 2744 (Map.update 2745 ((!c_MCSR),BitsN.toNat (!procID), 2746 MachineCSR_mstatus_rupd 2747 (x0,mstatus_MFS_rupd(x1,ext_status Dirty)))) 2748 end 2749 ; let 2750 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2751 val x1 = #mstatus(x0 : MachineCSR) 2752 in 2753 c_MCSR := 2754 (Map.update 2755 ((!c_MCSR),BitsN.toNat (!procID), 2756 MachineCSR_mstatus_rupd(x0,mstatus_MSD_rupd(x1,true)))) 2757 end 2758 ) 2759 | BitsN.B(0x3,_) => 2760 ( let 2761 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2762 val x1 = #fpcsr(x0 : UserCSR) 2763 in 2764 c_UCSR := 2765 (Map.update 2766 ((!c_UCSR),BitsN.toNat (!procID), 2767 UserCSR_fpcsr_rupd 2768 (x0,write'reg'FPCSR(x1,BitsN.bits(31,0) value)))) 2769 end 2770 ; let 2771 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2772 val x1 = #mstatus(x0 : MachineCSR) 2773 in 2774 c_MCSR := 2775 (Map.update 2776 ((!c_MCSR),BitsN.toNat (!procID), 2777 MachineCSR_mstatus_rupd 2778 (x0,mstatus_MFS_rupd(x1,ext_status Dirty)))) 2779 end 2780 ; let 2781 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2782 val x1 = #mstatus(x0 : MachineCSR) 2783 in 2784 c_MCSR := 2785 (Map.update 2786 ((!c_MCSR),BitsN.toNat (!procID), 2787 MachineCSR_mstatus_rupd(x0,mstatus_MSD_rupd(x1,true)))) 2788 end 2789 ) 2790 | BitsN.B(0x100,_) => 2791 let 2792 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2793 in 2794 c_MCSR := 2795 (Map.update 2796 ((!c_MCSR),BitsN.toNat (!procID), 2797 MachineCSR_mstatus_rupd 2798 (x0, 2799 lower_sstatus_mstatus 2800 (rec'sstatus value, 2801 #mstatus 2802 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : 2803 MachineCSR))))) 2804 end 2805 | BitsN.B(0x101,_) => 2806 let 2807 val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) 2808 in 2809 c_SCSR := 2810 (Map.update 2811 ((!c_SCSR),BitsN.toNat (!procID), 2812 SupervisorCSR_stvec_rupd(x0,value))) 2813 end 2814 | BitsN.B(0x104,_) => 2815 let 2816 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2817 in 2818 c_MCSR := 2819 (Map.update 2820 ((!c_MCSR),BitsN.toNat (!procID), 2821 MachineCSR_mie_rupd 2822 (x0, 2823 lower_sie_mie 2824 (rec'sie value, 2825 #mie 2826 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : 2827 MachineCSR))))) 2828 end 2829 | BitsN.B(0x121,_) => 2830 ( let 2831 val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) 2832 in 2833 c_SCSR := 2834 (Map.update 2835 ((!c_SCSR),BitsN.toNat (!procID), 2836 SupervisorCSR_stimecmp_rupd(x0,value))) 2837 end 2838 ; let 2839 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2840 val x1 = #mip(x0 : MachineCSR) 2841 in 2842 c_MCSR := 2843 (Map.update 2844 ((!c_MCSR),BitsN.toNat (!procID), 2845 MachineCSR_mip_rupd(x0,mip_STIP_rupd(x1,false)))) 2846 end 2847 ) 2848 | BitsN.B(0x140,_) => 2849 let 2850 val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) 2851 in 2852 c_SCSR := 2853 (Map.update 2854 ((!c_SCSR),BitsN.toNat (!procID), 2855 SupervisorCSR_sscratch_rupd(x0,value))) 2856 end 2857 | BitsN.B(0x141,_) => 2858 let 2859 val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) 2860 in 2861 c_SCSR := 2862 (Map.update 2863 ((!c_SCSR),BitsN.toNat (!procID), 2864 SupervisorCSR_sepc_rupd 2865 (x0,BitsN.&&(value,BitsN.signExtend 64 (BitsN.B(0x4,3)))))) 2866 end 2867 | BitsN.B(0x144,_) => 2868 let 2869 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2870 in 2871 c_MCSR := 2872 (Map.update 2873 ((!c_MCSR),BitsN.toNat (!procID), 2874 MachineCSR_mip_rupd 2875 (x0, 2876 lower_sip_mip 2877 (rec'sip value, 2878 #mip 2879 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : 2880 MachineCSR))))) 2881 end 2882 | BitsN.B(0x180,_) => 2883 let 2884 val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) 2885 in 2886 c_SCSR := 2887 (Map.update 2888 ((!c_SCSR),BitsN.toNat (!procID), 2889 SupervisorCSR_sptbr_rupd(x0,value))) 2890 end 2891 | BitsN.B(0x181,_) => 2892 let 2893 val x0 = Map.lookup((!c_SCSR),BitsN.toNat (!procID)) 2894 in 2895 c_SCSR := 2896 (Map.update 2897 ((!c_SCSR),BitsN.toNat (!procID), 2898 SupervisorCSR_sasid_rupd(x0,value))) 2899 end 2900 | BitsN.B(0x900,_) => 2901 let 2902 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2903 in 2904 c_UCSR := 2905 (Map.update 2906 ((!c_UCSR),BitsN.toNat (!procID), 2907 UserCSR_cycle_delta_rupd 2908 (x0, 2909 BitsN.-(value,Map.lookup((!c_cycles),BitsN.toNat (!procID)))))) 2910 end 2911 | BitsN.B(0x901,_) => 2912 let 2913 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2914 in 2915 c_UCSR := 2916 (Map.update 2917 ((!c_UCSR),BitsN.toNat (!procID), 2918 UserCSR_time_delta_rupd(x0,BitsN.-(value,(!clock))))) 2919 end 2920 | BitsN.B(0x902,_) => 2921 let 2922 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2923 in 2924 c_UCSR := 2925 (Map.update 2926 ((!c_UCSR),BitsN.toNat (!procID), 2927 UserCSR_instret_delta_rupd 2928 (x0, 2929 BitsN.- 2930 (value,Map.lookup((!c_instret),BitsN.toNat (!procID)))))) 2931 end 2932 | BitsN.B(0x980,_) => 2933 let 2934 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2935 val w = #cycle_delta(x0 : UserCSR) 2936 in 2937 c_UCSR := 2938 (Map.update 2939 ((!c_UCSR),BitsN.toNat (!procID), 2940 UserCSR_cycle_delta_rupd 2941 (x0, 2942 BitsN.bitFieldInsert(63,32) 2943 (w, 2944 BitsN.<< 2945 (BitsN.- 2946 (BitsN.bits(31,0) value, 2947 BitsN.bits(63,32) 2948 (Map.lookup((!c_cycles),BitsN.toNat (!procID)))), 2949 32))))) 2950 end 2951 | BitsN.B(0x981,_) => 2952 let 2953 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2954 val w = #time_delta(x0 : UserCSR) 2955 in 2956 c_UCSR := 2957 (Map.update 2958 ((!c_UCSR),BitsN.toNat (!procID), 2959 UserCSR_time_delta_rupd 2960 (x0, 2961 BitsN.bitFieldInsert(63,32) 2962 (w, 2963 BitsN.<< 2964 (BitsN.- 2965 (BitsN.bits(31,0) value,BitsN.bits(63,32) (!clock)), 2966 32))))) 2967 end 2968 | BitsN.B(0x982,_) => 2969 let 2970 val x0 = Map.lookup((!c_UCSR),BitsN.toNat (!procID)) 2971 val w = #instret_delta(x0 : UserCSR) 2972 in 2973 c_UCSR := 2974 (Map.update 2975 ((!c_UCSR),BitsN.toNat (!procID), 2976 UserCSR_instret_delta_rupd 2977 (x0, 2978 BitsN.bitFieldInsert(63,32) 2979 (w, 2980 BitsN.<< 2981 (BitsN.- 2982 (BitsN.bits(31,0) value, 2983 BitsN.bits(63,32) 2984 (Map.lookup((!c_instret),BitsN.toNat (!procID)))), 2985 32))))) 2986 end 2987 | BitsN.B(0x300,_) => 2988 let 2989 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 2990 in 2991 c_MCSR := 2992 (Map.update 2993 ((!c_MCSR),BitsN.toNat (!procID), 2994 MachineCSR_mstatus_rupd 2995 (x0, 2996 update_mstatus 2997 (#mstatus 2998 ((Map.lookup((!c_MCSR),BitsN.toNat (!procID))) : 2999 MachineCSR),rec'mstatus value)))) 3000 end 3001 | BitsN.B(0x301,_) => 3002 let 3003 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3004 in 3005 c_MCSR := 3006 (Map.update 3007 ((!c_MCSR),BitsN.toNat (!procID),MachineCSR_mtvec_rupd(x0,value))) 3008 end 3009 | BitsN.B(0x302,_) => 3010 let 3011 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3012 in 3013 c_MCSR := 3014 (Map.update 3015 ((!c_MCSR),BitsN.toNat (!procID), 3016 MachineCSR_mtdeleg_rupd(x0,rec'mtdeleg value))) 3017 end 3018 | BitsN.B(0x304,_) => 3019 let 3020 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3021 in 3022 c_MCSR := 3023 (Map.update 3024 ((!c_MCSR),BitsN.toNat (!procID), 3025 MachineCSR_mie_rupd(x0,rec'mie value))) 3026 end 3027 | BitsN.B(0x321,_) => 3028 ( let 3029 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3030 in 3031 c_MCSR := 3032 (Map.update 3033 ((!c_MCSR),BitsN.toNat (!procID), 3034 MachineCSR_mtimecmp_rupd(x0,value))) 3035 end 3036 ; let 3037 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3038 val x1 = #mip(x0 : MachineCSR) 3039 in 3040 c_MCSR := 3041 (Map.update 3042 ((!c_MCSR),BitsN.toNat (!procID), 3043 MachineCSR_mip_rupd(x0,mip_MTIP_rupd(x1,false)))) 3044 end 3045 ) 3046 | BitsN.B(0x701,_) => 3047 let 3048 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3049 in 3050 c_MCSR := 3051 (Map.update 3052 ((!c_MCSR),BitsN.toNat (!procID), 3053 MachineCSR_mtime_delta_rupd(x0,BitsN.-(value,(!clock))))) 3054 end 3055 | BitsN.B(0x741,_) => 3056 let 3057 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3058 val w = #mtime_delta(x0 : MachineCSR) 3059 in 3060 c_MCSR := 3061 (Map.update 3062 ((!c_MCSR),BitsN.toNat (!procID), 3063 MachineCSR_mtime_delta_rupd 3064 (x0, 3065 BitsN.bitFieldInsert(63,32) 3066 (w, 3067 BitsN.<< 3068 (BitsN.- 3069 (BitsN.bits(31,0) value,BitsN.bits(63,32) (!clock)), 3070 32))))) 3071 end 3072 | BitsN.B(0x340,_) => 3073 let 3074 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3075 in 3076 c_MCSR := 3077 (Map.update 3078 ((!c_MCSR),BitsN.toNat (!procID), 3079 MachineCSR_mscratch_rupd(x0,value))) 3080 end 3081 | BitsN.B(0x341,_) => 3082 let 3083 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3084 in 3085 c_MCSR := 3086 (Map.update 3087 ((!c_MCSR),BitsN.toNat (!procID), 3088 MachineCSR_mepc_rupd 3089 (x0,BitsN.&&(value,BitsN.signExtend 64 (BitsN.B(0x4,3)))))) 3090 end 3091 | BitsN.B(0x342,_) => 3092 let 3093 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3094 in 3095 c_MCSR := 3096 (Map.update 3097 ((!c_MCSR),BitsN.toNat (!procID), 3098 MachineCSR_mcause_rupd(x0,rec'mcause value))) 3099 end 3100 | BitsN.B(0x343,_) => 3101 let 3102 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3103 in 3104 c_MCSR := 3105 (Map.update 3106 ((!c_MCSR),BitsN.toNat (!procID), 3107 MachineCSR_mbadaddr_rupd(x0,value))) 3108 end 3109 | BitsN.B(0x344,_) => 3110 let 3111 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3112 in 3113 c_MCSR := 3114 (Map.update 3115 ((!c_MCSR),BitsN.toNat (!procID), 3116 MachineCSR_mip_rupd(x0,rec'mip value))) 3117 end 3118 | BitsN.B(0x380,_) => 3119 let 3120 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3121 in 3122 c_MCSR := 3123 (Map.update 3124 ((!c_MCSR),BitsN.toNat (!procID),MachineCSR_mbase_rupd(x0,value))) 3125 end 3126 | BitsN.B(0x381,_) => 3127 let 3128 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3129 in 3130 c_MCSR := 3131 (Map.update 3132 ((!c_MCSR),BitsN.toNat (!procID), 3133 MachineCSR_mbound_rupd(x0,value))) 3134 end 3135 | BitsN.B(0x382,_) => 3136 let 3137 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3138 in 3139 c_MCSR := 3140 (Map.update 3141 ((!c_MCSR),BitsN.toNat (!procID), 3142 MachineCSR_mibase_rupd(x0,value))) 3143 end 3144 | BitsN.B(0x383,_) => 3145 let 3146 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3147 in 3148 c_MCSR := 3149 (Map.update 3150 ((!c_MCSR),BitsN.toNat (!procID), 3151 MachineCSR_mibound_rupd(x0,value))) 3152 end 3153 | BitsN.B(0x384,_) => 3154 let 3155 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3156 in 3157 c_MCSR := 3158 (Map.update 3159 ((!c_MCSR),BitsN.toNat (!procID), 3160 MachineCSR_mdbase_rupd(x0,value))) 3161 end 3162 | BitsN.B(0x385,_) => 3163 let 3164 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3165 in 3166 c_MCSR := 3167 (Map.update 3168 ((!c_MCSR),BitsN.toNat (!procID), 3169 MachineCSR_mdbound_rupd(x0,value))) 3170 end 3171 | BitsN.B(0xB01,_) => 3172 let 3173 val x0 = Map.lookup((!c_HCSR),BitsN.toNat (!procID)) 3174 in 3175 c_HCSR := 3176 (Map.update 3177 ((!c_HCSR),BitsN.toNat (!procID), 3178 HypervisorCSR_htime_delta_rupd(x0,BitsN.-(value,(!clock))))) 3179 end 3180 | BitsN.B(0xB81,_) => 3181 let 3182 val x0 = Map.lookup((!c_HCSR),BitsN.toNat (!procID)) 3183 val w = #htime_delta(x0 : HypervisorCSR) 3184 in 3185 c_HCSR := 3186 (Map.update 3187 ((!c_HCSR),BitsN.toNat (!procID), 3188 HypervisorCSR_htime_delta_rupd 3189 (x0, 3190 BitsN.bitFieldInsert(63,32) 3191 (w, 3192 BitsN.<< 3193 (BitsN.- 3194 (BitsN.bits(31,0) value,BitsN.bits(63,32) (!clock)), 3195 32))))) 3196 end 3197 | BitsN.B(0x780,_) => 3198 let 3199 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3200 in 3201 c_MCSR := 3202 (Map.update 3203 ((!c_MCSR),BitsN.toNat (!procID), 3204 MachineCSR_mtohost_rupd(x0,value))) 3205 end 3206 | BitsN.B(0x781,_) => 3207 let 3208 val x0 = Map.lookup((!c_MCSR),BitsN.toNat (!procID)) 3209 in 3210 c_MCSR := 3211 (Map.update 3212 ((!c_MCSR),BitsN.toNat (!procID), 3213 MachineCSR_mfromhost_rupd(x0,value))) 3214 end 3215 | BitsN.B(0x783,_) => sendIPI value 3216 | _ => 3217 raise INTERNAL_ERROR 3218 ("unexpected CSR write to " ^ (BitsN.toHexString csr)); 3219 3220fun csrName csr = 3221 case csr of 3222 BitsN.B(0x1,_) => "fflags" 3223 | BitsN.B(0x2,_) => "frm" 3224 | BitsN.B(0x3,_) => "fcsr" 3225 | BitsN.B(0xC00,_) => "cycle" 3226 | BitsN.B(0xC01,_) => "time" 3227 | BitsN.B(0xC02,_) => "instret" 3228 | BitsN.B(0xC80,_) => "cycleh" 3229 | BitsN.B(0xC81,_) => "timeh" 3230 | BitsN.B(0xC82,_) => "instreth" 3231 | BitsN.B(0x100,_) => "sstatus" 3232 | BitsN.B(0x101,_) => "stvec" 3233 | BitsN.B(0x104,_) => "sie" 3234 | BitsN.B(0x121,_) => "stimecmp" 3235 | BitsN.B(0xD01,_) => "stime" 3236 | BitsN.B(0xD81,_) => "stimeh" 3237 | BitsN.B(0x140,_) => "sscratch" 3238 | BitsN.B(0x141,_) => "sepc" 3239 | BitsN.B(0xD42,_) => "scause" 3240 | BitsN.B(0xD43,_) => "sbadaddr" 3241 | BitsN.B(0x144,_) => "mip" 3242 | BitsN.B(0x180,_) => "sptbr" 3243 | BitsN.B(0x181,_) => "sasid" 3244 | BitsN.B(0x900,_) => "cycle" 3245 | BitsN.B(0x901,_) => "time" 3246 | BitsN.B(0x902,_) => "instret" 3247 | BitsN.B(0x980,_) => "cycleh" 3248 | BitsN.B(0x981,_) => "timeh" 3249 | BitsN.B(0x982,_) => "instreth" 3250 | BitsN.B(0x200,_) => "hstatus" 3251 | BitsN.B(0x201,_) => "htvec" 3252 | BitsN.B(0x202,_) => "htdeleg" 3253 | BitsN.B(0x221,_) => "htimecmp" 3254 | BitsN.B(0xE01,_) => "htime" 3255 | BitsN.B(0xE81,_) => "htimeh" 3256 | BitsN.B(0x240,_) => "hscratch" 3257 | BitsN.B(0x241,_) => "hepc" 3258 | BitsN.B(0x242,_) => "hcause" 3259 | BitsN.B(0x243,_) => "hbadaddr" 3260 | BitsN.B(0xA01,_) => "stime" 3261 | BitsN.B(0xA81,_) => "stimeh" 3262 | BitsN.B(0xF00,_) => "mcpuid" 3263 | BitsN.B(0xF01,_) => "mimpid" 3264 | BitsN.B(0xF10,_) => "mhartid" 3265 | BitsN.B(0x300,_) => "mstatus" 3266 | BitsN.B(0x301,_) => "mtvec" 3267 | BitsN.B(0x302,_) => "mtdeleg" 3268 | BitsN.B(0x304,_) => "mie" 3269 | BitsN.B(0x321,_) => "mtimecmp" 3270 | BitsN.B(0x701,_) => "mtime" 3271 | BitsN.B(0x741,_) => "mtimeh" 3272 | BitsN.B(0x340,_) => "mscratch" 3273 | BitsN.B(0x341,_) => "mepc" 3274 | BitsN.B(0x342,_) => "mcause" 3275 | BitsN.B(0x343,_) => "mbadaddr" 3276 | BitsN.B(0x344,_) => "mip" 3277 | BitsN.B(0x380,_) => "mbase" 3278 | BitsN.B(0x381,_) => "mbound" 3279 | BitsN.B(0x382,_) => "mibase" 3280 | BitsN.B(0x383,_) => "mibound" 3281 | BitsN.B(0x384,_) => "mdbase" 3282 | BitsN.B(0x385,_) => "mdbound" 3283 | BitsN.B(0xB01,_) => "htime" 3284 | BitsN.B(0xB81,_) => "htimeh" 3285 | BitsN.B(0x780,_) => "mtohost" 3286 | BitsN.B(0x781,_) => "mfromhost" 3287 | BitsN.B(0x783,_) => "send_ipi" 3288 | _ => "UNKNOWN"; 3289 3290fun Delta () = Map.lookup((!c_update),BitsN.toNat (!procID)); 3291 3292fun write'Delta value = 3293 c_update := (Map.update((!c_update),BitsN.toNat (!procID),value)); 3294 3295fun hex32 x = L3.padLeftString(#"0",(8,BitsN.toHexString x)); 3296 3297fun hex64 x = L3.padLeftString(#"0",(16,BitsN.toHexString x)); 3298 3299fun log_w_csr (csr,data) = 3300 String.concat["CSR (",csrName csr,") <- 0x",hex64 data]; 3301 3302fun reg r = 3303 if r = (BitsN.B(0x0,5)) 3304 then "$0" 3305 else if r = (BitsN.B(0x1,5)) 3306 then "ra" 3307 else if r = (BitsN.B(0x2,5)) 3308 then "sp" 3309 else if r = (BitsN.B(0x3,5)) 3310 then "gp" 3311 else if r = (BitsN.B(0x4,5)) 3312 then "tp" 3313 else if r = (BitsN.B(0x5,5)) 3314 then "t0" 3315 else if r = (BitsN.B(0x6,5)) 3316 then "t1" 3317 else if r = (BitsN.B(0x7,5)) 3318 then "t2" 3319 else if r = (BitsN.B(0x8,5)) 3320 then "fp" 3321 else if r = (BitsN.B(0x9,5)) 3322 then "s1" 3323 else if r = (BitsN.B(0xA,5)) 3324 then "a0" 3325 else if r = (BitsN.B(0xB,5)) 3326 then "a1" 3327 else if r = (BitsN.B(0xC,5)) 3328 then "a2" 3329 else if r = (BitsN.B(0xD,5)) 3330 then "a3" 3331 else if r = (BitsN.B(0xE,5)) 3332 then "a4" 3333 else if r = (BitsN.B(0xF,5)) 3334 then "a5" 3335 else if r = (BitsN.B(0x10,5)) 3336 then "a6" 3337 else if r = (BitsN.B(0x11,5)) 3338 then "a7" 3339 else if r = (BitsN.B(0x12,5)) 3340 then "s2" 3341 else if r = (BitsN.B(0x13,5)) 3342 then "s3" 3343 else if r = (BitsN.B(0x14,5)) 3344 then "s4" 3345 else if r = (BitsN.B(0x15,5)) 3346 then "s5" 3347 else if r = (BitsN.B(0x16,5)) 3348 then "s6" 3349 else if r = (BitsN.B(0x17,5)) 3350 then "s7" 3351 else if r = (BitsN.B(0x18,5)) 3352 then "s8" 3353 else if r = (BitsN.B(0x19,5)) 3354 then "s9" 3355 else if r = (BitsN.B(0x1A,5)) 3356 then "s10" 3357 else if r = (BitsN.B(0x1B,5)) 3358 then "s11" 3359 else if r = (BitsN.B(0x1C,5)) 3360 then "t3" 3361 else if r = (BitsN.B(0x1D,5)) 3362 then "t4" 3363 else if r = (BitsN.B(0x1E,5)) then "t5" else "t6"; 3364 3365fun fpreg r = 3366 if r = (BitsN.B(0x0,5)) 3367 then "fs0" 3368 else if r = (BitsN.B(0x1,5)) 3369 then "fs1" 3370 else if r = (BitsN.B(0x2,5)) 3371 then "fs2" 3372 else if r = (BitsN.B(0x3,5)) 3373 then "fs3" 3374 else if r = (BitsN.B(0x4,5)) 3375 then "fs4" 3376 else if r = (BitsN.B(0x5,5)) 3377 then "fs5" 3378 else if r = (BitsN.B(0x6,5)) 3379 then "fs6" 3380 else if r = (BitsN.B(0x7,5)) 3381 then "fs7" 3382 else if r = (BitsN.B(0x8,5)) 3383 then "fs8" 3384 else if r = (BitsN.B(0x9,5)) 3385 then "fs9" 3386 else if r = (BitsN.B(0xA,5)) 3387 then "fs10" 3388 else if r = (BitsN.B(0xB,5)) 3389 then "fs11" 3390 else if r = (BitsN.B(0xC,5)) 3391 then "fs12" 3392 else if r = (BitsN.B(0xD,5)) 3393 then "fs13" 3394 else if r = (BitsN.B(0xE,5)) 3395 then "fs14" 3396 else if r = (BitsN.B(0xF,5)) 3397 then "fs15" 3398 else if r = (BitsN.B(0x10,5)) 3399 then "fv0" 3400 else if r = (BitsN.B(0x11,5)) 3401 then "fv1" 3402 else if r = (BitsN.B(0x12,5)) 3403 then "fa0" 3404 else if r = (BitsN.B(0x13,5)) 3405 then "fa1" 3406 else if r = (BitsN.B(0x14,5)) 3407 then "fa2" 3408 else if r = (BitsN.B(0x15,5)) 3409 then "fa3" 3410 else if r = (BitsN.B(0x16,5)) 3411 then "fa4" 3412 else if r = (BitsN.B(0x17,5)) 3413 then "fa5" 3414 else if r = (BitsN.B(0x18,5)) 3415 then "fa6" 3416 else if r = (BitsN.B(0x19,5)) 3417 then "fa7" 3418 else if r = (BitsN.B(0x1A,5)) 3419 then "ft0" 3420 else if r = (BitsN.B(0x1B,5)) 3421 then "ft1" 3422 else if r = (BitsN.B(0x1C,5)) 3423 then "ft2" 3424 else if r = (BitsN.B(0x1D,5)) 3425 then "ft3" 3426 else if r = (BitsN.B(0x1E,5)) then "ft4" else "ft5"; 3427 3428fun log_w_gpr (r,data) = 3429 String.concat 3430 ["Reg ",reg r," (",Nat.toString(BitsN.toNat r),") <- 0x",hex64 data]; 3431 3432fun log_w_fprs (r,data) = 3433 String.concat 3434 ["FPR ",reg r," (",Nat.toString(BitsN.toNat r),") <- 0x",hex32 data]; 3435 3436fun log_w_fprd (r,data) = 3437 String.concat 3438 ["FPR ",reg r," (",Nat.toString(BitsN.toNat r),") <- 0x",hex64 data]; 3439 3440fun log_w_mem_mask (pAddrIdx,(vAddr,(mask,(data,(old,new))))) = 3441 String.concat 3442 ["MEM[0x",hex64(BitsN.fromNat(BitsN.toNat pAddrIdx,64)),"/", 3443 hex64 vAddr,"] <- (data: 0x",hex64 data,", mask: 0x",hex64 mask, 3444 ", old: 0x",hex64 old,", new: 0x",hex64 new,")"]; 3445 3446fun log_w_mem_mask_misaligned 3447 (pAddrIdx,(vAddr,(mask,(data,(align,(old,new)))))) = 3448 String.concat 3449 ["MEM[0x",hex64(BitsN.fromNat(BitsN.toNat pAddrIdx,64)),"/", 3450 hex64 vAddr,"/ misaligned@",Nat.toString align,"] <- (data: 0x", 3451 hex64 data,", mask: 0x",hex64 mask,", old: 0x",hex64 old,", new: 0x", 3452 hex64 new,")"]; 3453 3454fun log_w_mem (pAddrIdx,(vAddr,data)) = 3455 String.concat 3456 ["MEM[0x",hex64(BitsN.fromNat(BitsN.toNat pAddrIdx,64)),"/", 3457 hex64 vAddr,"] <- (data: 0x",hex64 data,")"]; 3458 3459fun log_r_mem (pAddrIdx,(vAddr,data)) = 3460 String.concat 3461 ["data <- MEM[0x", 3462 L3.padLeftString(#"0",(10,BitsN.toHexString pAddrIdx)),"/", 3463 hex64 vAddr,"]: 0x",hex64 data]; 3464 3465fun log_exc e = String.concat[" Exception ",excName e," raised!"]; 3466 3467fun log_tohost tohost = 3468 "-> host: " 3469 ^ 3470 (String.str((L3.chr o BitsN.toNat) (BitsN.bits(7,0) tohost))); 3471 3472fun clear_logs () = log := []; 3473 3474fun setTrap (e,badaddr) = 3475 let 3476 val trap = ref {badaddr = NONE, trap = AMO_Misaligned} 3477 in 3478 ( trap := (SynchronousTrap_trap_rupd((!trap),e)) 3479 ; trap := (SynchronousTrap_badaddr_rupd((!trap),badaddr)) 3480 ; write'NextFetch(Option.SOME(Trap (!trap))) 3481 ) 3482 end; 3483 3484fun signalException e = 3485 ( log := ((1,"signalling exception " ^ (excName e)) :: (!log)) 3486 ; setTrap(e,NONE) 3487 ; let 3488 val x = Delta () 3489 in 3490 write'Delta(StateDelta_exc_taken_rupd(x,true)) 3491 end 3492 ); 3493 3494fun signalAddressException (e,vAddr) = 3495 ( log := 3496 ((1, 3497 String.concat 3498 ["signalling address exception ",excName e," at ", 3499 BitsN.toHexString vAddr]) 3500 :: 3501 (!log)) 3502 ; setTrap(e,Option.SOME vAddr) 3503 ; let 3504 val x = Delta () 3505 in 3506 write'Delta(StateDelta_exc_taken_rupd(x,true)) 3507 end 3508 ); 3509 3510fun signalEnvCall () = 3511 let 3512 val e = 3513 case privilege(#MPRV((#mstatus((MCSR ()) : MachineCSR)) : mstatus)) of 3514 User => UMode_Env_Call 3515 | Supervisor => SMode_Env_Call 3516 | Hypervisor => HMode_Env_Call 3517 | Machine => MMode_Env_Call 3518 in 3519 signalException e 3520 end; 3521 3522fun checkDelegation (curPriv,(intr,ec)) = 3523 let 3524 val e = BitsN.toNat ec 3525 in 3526 case curPriv of 3527 User => raise INTERNAL_ERROR "No user-level delegation!" 3528 | Supervisor => 3529 raise INTERNAL_ERROR "No supervisor-level delegation!" 3530 | Hypervisor => 3531 if (intr andalso 3532 (BitsN.bit 3533 (#Intr_deleg 3534 ((#htdeleg((HCSR ()) : HypervisorCSR)) : mtdeleg),e))) orelse 3535 ((not intr) andalso 3536 (BitsN.bit 3537 (#Exc_deleg((#htdeleg((HCSR ()) : HypervisorCSR)) : mtdeleg), 3538 e))) 3539 then Supervisor 3540 else curPriv 3541 | Machine => 3542 if (intr andalso 3543 (BitsN.bit 3544 (#Intr_deleg((#mtdeleg((MCSR ()) : MachineCSR)) : mtdeleg),e))) orelse 3545 ((not intr) andalso 3546 (BitsN.bit 3547 (#Exc_deleg((#mtdeleg((MCSR ()) : MachineCSR)) : mtdeleg),e))) 3548 then checkDelegation(Hypervisor,(intr,ec)) 3549 else curPriv 3550 end; 3551 3552fun checkPrivInterrupt curPriv = 3553 let 3554 val ip = #mip((MCSR ()) : MachineCSR) 3555 val ie = #mie((MCSR ()) : MachineCSR) 3556 in 3557 case curPriv of 3558 User => raise INTERNAL_ERROR "No user-level interrupts!" 3559 | Supervisor => 3560 if (#STIP(ip : mip)) andalso (#STIE(ie : mie)) 3561 then Option.SOME(Timer,curPriv) 3562 else if (#SSIP(ip : mip)) andalso (#SSIE(ie : mie)) 3563 then Option.SOME(Software,curPriv) 3564 else NONE 3565 | Hypervisor => 3566 if (#HTIP(ip : mip)) andalso (#HTIE(ie : mie)) 3567 then Option.SOME(Timer,curPriv) 3568 else if (#HSIP(ip : mip)) andalso (#HSIE(ie : mie)) 3569 then Option.SOME(Software,curPriv) 3570 else NONE 3571 | Machine => 3572 if (#MTIP(ip : mip)) andalso (#MTIE(ie : mie)) 3573 then Option.SOME(Timer,curPriv) 3574 else if (#MSIP(ip : mip)) andalso (#MSIE(ie : mie)) 3575 then Option.SOME(Software,curPriv) 3576 else NONE 3577 end; 3578 3579fun checkInterrupts () = 3580 let 3581 val curIE = #MIE((#mstatus((MCSR ()) : MachineCSR)) : mstatus) 3582 val p = curPrivilege () 3583 in 3584 case p of 3585 User => 3586 (case checkPrivInterrupt Machine of 3587 NONE => 3588 (case checkPrivInterrupt Hypervisor of 3589 NONE => 3590 if (p = User) orelse curIE 3591 then checkPrivInterrupt Supervisor 3592 else NONE 3593 | i => i) 3594 | i => i) 3595 | Supervisor => 3596 (case checkPrivInterrupt Machine of 3597 NONE => 3598 (case checkPrivInterrupt Hypervisor of 3599 NONE => 3600 if (p = User) orelse curIE 3601 then checkPrivInterrupt Supervisor 3602 else NONE 3603 | i => i) 3604 | i => i) 3605 | Hypervisor => 3606 (case checkPrivInterrupt Machine of 3607 NONE => if curIE then checkPrivInterrupt Hypervisor else NONE 3608 | i => i) 3609 | Machine => if curIE then checkPrivInterrupt Machine else NONE 3610 end; 3611 3612fun takeTrap (intr,(ec,(epc,(badaddr,toPriv)))) = 3613 let 3614 val fromP = curPrivilege () 3615 in 3616 ( log := 3617 ((1, 3618 String.concat 3619 ["trapping from ",privName fromP," to ",privName toPriv, 3620 " at pc ",BitsN.toHexString epc, 3621 if intr then " [intr] " else " [exc] ", 3622 Nat.toString(BitsN.toNat ec)]) 3623 :: 3624 (!log)) 3625 ; write'ReserveLoad NONE 3626 ; let 3627 val x = MCSR () 3628 val x0 = #mstatus(x : MachineCSR) 3629 in 3630 write'MCSR 3631 (MachineCSR_mstatus_rupd(x,mstatus_MMPRV_rupd(x0,false))) 3632 end 3633 ; let 3634 val x = MCSR () 3635 in 3636 write'MCSR 3637 (MachineCSR_mstatus_rupd 3638 (x, 3639 pushPrivilegeStack(#mstatus((MCSR ()) : MachineCSR),toPriv))) 3640 end 3641 ; case toPriv of 3642 User => raise INTERNAL_ERROR "Illegal trap to U-mode" 3643 | Supervisor => 3644 ( let 3645 val x = SCSR () 3646 val x0 = #scause(x : SupervisorCSR) 3647 in 3648 write'SCSR 3649 (SupervisorCSR_scause_rupd(x,mcause_Int_rupd(x0,intr))) 3650 end 3651 ; let 3652 val x = SCSR () 3653 val x0 = #scause(x : SupervisorCSR) 3654 in 3655 write'SCSR 3656 (SupervisorCSR_scause_rupd(x,mcause_EC_rupd(x0,ec))) 3657 end 3658 ; let 3659 val x = SCSR () 3660 in 3661 write'SCSR(SupervisorCSR_sepc_rupd(x,epc)) 3662 end 3663 ; if Option.isSome badaddr 3664 then let 3665 val x = SCSR () 3666 in 3667 write'SCSR 3668 (SupervisorCSR_sbadaddr_rupd(x,Option.valOf badaddr)) 3669 end 3670 else () 3671 ; write'PC(#stvec((SCSR ()) : SupervisorCSR)) 3672 ) 3673 | Hypervisor => raise INTERNAL_ERROR "Unsupported trap to H-mode" 3674 | Machine => 3675 ( let 3676 val x = MCSR () 3677 val x0 = #mcause(x : MachineCSR) 3678 in 3679 write'MCSR 3680 (MachineCSR_mcause_rupd(x,mcause_Int_rupd(x0,intr))) 3681 end 3682 ; let 3683 val x = MCSR () 3684 val x0 = #mcause(x : MachineCSR) 3685 in 3686 write'MCSR(MachineCSR_mcause_rupd(x,mcause_EC_rupd(x0,ec))) 3687 end 3688 ; let 3689 val x = MCSR () 3690 in 3691 write'MCSR(MachineCSR_mepc_rupd(x,epc)) 3692 end 3693 ; if Option.isSome badaddr 3694 then let 3695 val x = MCSR () 3696 in 3697 write'MCSR 3698 (MachineCSR_mbadaddr_rupd(x,Option.valOf badaddr)) 3699 end 3700 else () 3701 ; write'PC 3702 (BitsN.+ 3703 (#mtvec((MCSR ()) : MachineCSR), 3704 BitsN.* 3705 (BitsN.fromNat(BitsN.toNat(privLevel fromP),64), 3706 BitsN.B(0x40,64)))) 3707 ) 3708 ) 3709 end; 3710 3711fun CSR n = CSRMap n; 3712 3713fun write'CSR (value,n) = 3714 ( write'CSRMap(value,n); log := ((2,log_w_csr(n,value)) :: (!log)) ); 3715 3716fun writeCSR (csr,val') = 3717 ( write'CSR(val',csr) 3718 ; let 3719 val x = Delta () 3720 in 3721 write'Delta 3722 (StateDelta_addr_rupd(x,Option.SOME(BitsN.zeroExtend 64 csr))) 3723 end 3724 ; let 3725 val x = Delta () 3726 in 3727 write'Delta(StateDelta_data2_rupd(x,Option.SOME(CSR csr))) 3728 end 3729 ); 3730 3731fun GPR n = if n = (BitsN.B(0x0,5)) then BitsN.B(0x0,64) else gpr n; 3732 3733fun write'GPR (value,n) = 3734 if not(n = (BitsN.B(0x0,5))) 3735 then ( write'gpr(value,n); log := ((2,log_w_gpr(n,value)) :: (!log)) ) 3736 else (); 3737 3738fun FPRS n = BitsN.bits(31,0) (fpr n); 3739 3740fun write'FPRS (value,n) = 3741 ( let 3742 val w = fpr n 3743 in 3744 write'fpr(BitsN.bitFieldInsert(31,0) (w,value),n) 3745 end 3746 ; log := ((2,log_w_fprs(n,value)) :: (!log)) 3747 ); 3748 3749fun FPRD n = fpr n; 3750 3751fun write'FPRD (value,n) = 3752 ( write'fpr(value,n); log := ((2,log_w_fprd(n,value)) :: (!log)) ); 3753 3754fun writeFPRS (rd,val') = 3755 ( write'FPRS(val',rd) 3756 ; let 3757 val x = MCSR () 3758 val x0 = #mstatus(x : MachineCSR) 3759 in 3760 write'MCSR 3761 (MachineCSR_mstatus_rupd(x,mstatus_MFS_rupd(x0,ext_status Dirty))) 3762 end 3763 ; let 3764 val x = MCSR () 3765 val x0 = #mstatus(x : MachineCSR) 3766 in 3767 write'MCSR(MachineCSR_mstatus_rupd(x,mstatus_MSD_rupd(x0,true))) 3768 end 3769 ; let 3770 val x = Delta () 3771 in 3772 write'Delta 3773 (StateDelta_data1_rupd(x,Option.SOME(BitsN.zeroExtend 64 val'))) 3774 end 3775 ); 3776 3777fun writeFPRD (rd,val') = 3778 ( write'FPRD(val',rd) 3779 ; let 3780 val x = MCSR () 3781 val x0 = #mstatus(x : MachineCSR) 3782 in 3783 write'MCSR 3784 (MachineCSR_mstatus_rupd(x,mstatus_MFS_rupd(x0,ext_status Dirty))) 3785 end 3786 ; let 3787 val x = MCSR () 3788 val x0 = #mstatus(x : MachineCSR) 3789 in 3790 write'MCSR(MachineCSR_mstatus_rupd(x,mstatus_MSD_rupd(x0,true))) 3791 end 3792 ; let 3793 val x = Delta () 3794 in 3795 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 3796 end 3797 ); 3798 3799fun MEM a = 3800 let 3801 val b = BitsN.<<(BitsN.fromNat(BitsN.toNat a,64),3) 3802 in 3803 BitsN.concat 3804 [Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x7,64)))), 3805 Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x6,64)))), 3806 Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x5,64)))), 3807 Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x4,64)))), 3808 Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x3,64)))), 3809 Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x2,64)))), 3810 Map.lookup((!MEM8),BitsN.toNat(BitsN.+(b,BitsN.B(0x1,64)))), 3811 Map.lookup((!MEM8),BitsN.toNat b)] 3812 end; 3813 3814fun write'MEM (val',a) = 3815 let 3816 val b = BitsN.<<(BitsN.fromNat(BitsN.toNat a,64),3) 3817 in 3818 ( let 3819 val x = BitsN.+(b,BitsN.B(0x7,64)) 3820 in 3821 MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(63,56) val')) 3822 end 3823 ; let 3824 val x = BitsN.+(b,BitsN.B(0x6,64)) 3825 in 3826 MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(55,48) val')) 3827 end 3828 ; let 3829 val x = BitsN.+(b,BitsN.B(0x5,64)) 3830 in 3831 MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(47,40) val')) 3832 end 3833 ; let 3834 val x = BitsN.+(b,BitsN.B(0x4,64)) 3835 in 3836 MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(39,32) val')) 3837 end 3838 ; let 3839 val x = BitsN.+(b,BitsN.B(0x3,64)) 3840 in 3841 MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(31,24) val')) 3842 end 3843 ; let 3844 val x = BitsN.+(b,BitsN.B(0x2,64)) 3845 in 3846 MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(23,16) val')) 3847 end 3848 ; let 3849 val x = BitsN.+(b,BitsN.B(0x1,64)) 3850 in 3851 MEM8 := (Map.update((!MEM8),BitsN.toNat x,BitsN.bits(15,8) val')) 3852 end 3853 ; MEM8 := (Map.update((!MEM8),BitsN.toNat b,BitsN.bits(7,0) val')) 3854 ) 3855 end; 3856 3857fun rawReadData pAddr = 3858 let 3859 val pAddrIdx = BitsN.bits(63,3) pAddr 3860 val align = BitsN.toNat(BitsN.bits(2,0) pAddr) 3861 in 3862 if align = 0 3863 then let 3864 val data = MEM pAddrIdx 3865 in 3866 ( log := ((3,log_r_mem(pAddrIdx,(pAddr,data))) :: (!log)) 3867 ; data 3868 ) 3869 end 3870 else let 3871 val dw0 = MEM pAddrIdx 3872 val dw1 = MEM(BitsN.+(pAddrIdx,BitsN.B(0x1,61))) 3873 val ddw = BitsN.>>(BitsN.@@(dw1,dw0),Nat.*(align,8)) 3874 val data = BitsN.bits(63,0) ddw 3875 in 3876 ( log := ((3,log_r_mem(pAddrIdx,(pAddr,dw0))) :: (!log)) 3877 ; log := 3878 ((3,log_r_mem(BitsN.+(pAddrIdx,BitsN.B(0x1,61)),(pAddr,dw1))) 3879 :: 3880 (!log)) 3881 ; log := ((3,log_r_mem(pAddrIdx,(pAddr,data))) :: (!log)) 3882 ; data 3883 ) 3884 end 3885 end; 3886 3887fun rawWriteData (pAddr,(data,nbytes)) = 3888 let 3889 val mask = 3890 BitsN.- 3891 (BitsN.<<(BitsN.zeroExtend 64 (BitsN.B(0x1,1)),Nat.*(nbytes,8)), 3892 BitsN.B(0x1,64)) 3893 val pAddrIdx = BitsN.bits(63,3) pAddr 3894 val align = BitsN.toNat(BitsN.bits(2,0) pAddr) 3895 val old = MEM pAddrIdx 3896 in 3897 ( log := ((3,log_r_mem(pAddrIdx,(pAddr,old))) :: (!log)) 3898 ; if align = 0 3899 then let 3900 val new = 3901 BitsN.||(BitsN.&&(old,BitsN.~ mask),BitsN.&&(data,mask)) 3902 in 3903 ( write'MEM(new,pAddrIdx) 3904 ; log := 3905 ((3, 3906 log_w_mem_mask 3907 (pAddrIdx,(pAddr,(mask,(data,(old,new)))))) 3908 :: 3909 (!log)) 3910 ) 3911 end 3912 else if Nat.<=(Nat.+(align,nbytes),Nat.div(BitsN.size mask,8)) 3913 then let 3914 val new = 3915 BitsN.|| 3916 (BitsN.&&(old,BitsN.~(BitsN.<<(mask,Nat.*(align,8)))), 3917 BitsN.<<(BitsN.&&(data,mask),Nat.*(align,8))) 3918 in 3919 ( write'MEM(new,pAddrIdx) 3920 ; log := 3921 ((3, 3922 log_w_mem_mask_misaligned 3923 (pAddrIdx,(pAddr,(mask,(data,(align,(old,new))))))) 3924 :: 3925 (!log)) 3926 ) 3927 end 3928 else let 3929 val dw_old = 3930 BitsN.@@(MEM(BitsN.+(pAddrIdx,BitsN.B(0x1,61))),old) 3931 val dw_data = 3932 BitsN.<<(BitsN.zeroExtend 128 data,Nat.*(align,8)) 3933 val dw_mask = 3934 BitsN.<<(BitsN.zeroExtend 128 mask,Nat.*(align,8)) 3935 val dw_new = 3936 BitsN.|| 3937 (BitsN.&&(dw_old,BitsN.~ dw_mask), 3938 BitsN.&&(dw_data,dw_mask)) 3939 in 3940 ( let 3941 val x = BitsN.+(pAddrIdx,BitsN.B(0x1,61)) 3942 in 3943 write'MEM 3944 (BitsN.resize 64 3945 (BitsN.bits 3946 (Nat.-(Nat.*(2,BitsN.size data),1), 3947 BitsN.size data) 3948 dw_new),x) 3949 end 3950 ; write'MEM 3951 (BitsN.resize 64 3952 (BitsN.bits(Nat.-(BitsN.size data,1),0) dw_new), 3953 pAddrIdx) 3954 ) 3955 end 3956 ) 3957 end; 3958 3959fun rawReadInst pAddr = 3960 let 3961 val pAddrIdx = BitsN.bits(63,3) pAddr 3962 val data = MEM pAddrIdx 3963 in 3964 ( log := ((3,log_r_mem(pAddrIdx,(pAddr,data))) :: (!log)) 3965 ; if BitsN.bit(pAddr,2) 3966 then BitsN.bits(63,32) data 3967 else BitsN.bits(31,0) data 3968 ) 3969 end; 3970 3971fun rawWriteMem (pAddr,data) = 3972 let 3973 val pAddrIdx = BitsN.bits(63,3) pAddr 3974 in 3975 ( write'MEM(data,pAddrIdx) 3976 ; log := ((3,log_w_mem(pAddrIdx,(pAddr,data))) :: (!log)) 3977 ) 3978 end; 3979 3980fun checkMemPermission (ft,(ac,(priv,perm))) = 3981 case perm of 3982 BitsN.B(0x0,_) => 3983 raise INTERNAL_ERROR "Checking perm on Page-Table pointer!" 3984 | BitsN.B(0x1,_) => 3985 raise INTERNAL_ERROR "Checking perm on Page-Table pointer!" 3986 | BitsN.B(0x2,_) => 3987 if priv = User 3988 then not(ac = Write) 3989 else (ac = Read) andalso (ft = Data) 3990 | BitsN.B(0x3,_) => if priv = User then true else not(ft = Instruction) 3991 | BitsN.B(0x4,_) => (ac = Read) andalso (ft = Data) 3992 | BitsN.B(0x5,_) => not(ft = Instruction) 3993 | BitsN.B(0x6,_) => not(ac = Write) 3994 | BitsN.B(0x7,_) => true 3995 | BitsN.B(0x8,_) => 3996 (not(priv = User)) andalso ((ac = Read) andalso (ft = Data)) 3997 | BitsN.B(0x9,_) => (not(priv = User)) andalso (not(ft = Instruction)) 3998 | BitsN.B(0xA,_) => (not(priv = User)) andalso (not(ac = Write)) 3999 | BitsN.B(0xB,_) => not(priv = User) 4000 | BitsN.B(0xC,_) => 4001 (not(priv = User)) andalso ((ac = Read) andalso (ft = Data)) 4002 | BitsN.B(0xD,_) => (not(priv = User)) andalso (not(ft = Instruction)) 4003 | BitsN.B(0xE,_) => (not(priv = User)) andalso (not(ac = Write)) 4004 | BitsN.B(0xF,_) => not(priv = User) 4005 | _ => raise General.Bind; 4006 4007fun isGlobal perm = (BitsN.bits(3,2) perm) = (BitsN.B(0x3,2)); 4008 4009fun rec'SV_PTE x = 4010 {PTE_D = BitsN.bit(x,6), PTE_PPNi = BitsN.bits(47,10) x, 4011 PTE_R = BitsN.bit(x,5), PTE_SW = BitsN.bits(9,7) x, 4012 PTE_T = BitsN.bits(4,1) x, PTE_V = BitsN.bit(x,0), 4013 sv_pte'rst = BitsN.bits(63,48) x}; 4014 4015fun reg'SV_PTE x = 4016 case x of 4017 {PTE_D = PTE_D, PTE_PPNi = PTE_PPNi, PTE_R = PTE_R, PTE_SW = PTE_SW, 4018 PTE_T = PTE_T, PTE_V = PTE_V, sv_pte'rst = sv_pte'rst} => 4019 BitsN.concat 4020 [sv_pte'rst,PTE_PPNi,PTE_SW,BitsN.fromBit PTE_D, 4021 BitsN.fromBit PTE_R,PTE_T,BitsN.fromBit PTE_V]; 4022 4023fun write'rec'SV_PTE (_,x) = reg'SV_PTE x; 4024 4025fun write'reg'SV_PTE (_,x) = rec'SV_PTE x; 4026 4027fun rec'SV_Vaddr x = 4028 {Sv_PgOfs = BitsN.bits(11,0) x, Sv_VPNi = BitsN.bits(47,12) x, 4029 sv_vaddr'rst = BitsN.bits(63,48) x}; 4030 4031fun reg'SV_Vaddr x = 4032 case x of 4033 {Sv_PgOfs = Sv_PgOfs, Sv_VPNi = Sv_VPNi, sv_vaddr'rst = sv_vaddr'rst} => 4034 BitsN.concat[sv_vaddr'rst,Sv_VPNi,Sv_PgOfs]; 4035 4036fun write'rec'SV_Vaddr (_,x) = reg'SV_Vaddr x; 4037 4038fun write'reg'SV_Vaddr (_,x) = rec'SV_Vaddr x; 4039 4040fun walk64 (vAddr,(ft,(ac,(priv,(ptb,level))))) = 4041 let 4042 val va = rec'SV_Vaddr vAddr 4043 val pt_ofs = 4044 BitsN.<< 4045 (BitsN.zeroExtend 64 4046 (BitsN.bits(Nat.-(LEVEL_BITS,1),0) 4047 (BitsN.>>+(#Sv_VPNi(va : SV_Vaddr),Nat.*(level,LEVEL_BITS)))), 4048 3) 4049 val pte_addr = BitsN.+(ptb,pt_ofs) 4050 val pte = rec'SV_PTE(rawReadData pte_addr) 4051 in 4052 ( log := 4053 ((4, 4054 String.concat 4055 ["translate(vaddr=0x", 4056 L3.padLeftString(#"0",(16,BitsN.toHexString vAddr)), 4057 "): level=",Nat.toString level," pt_base=0x", 4058 L3.padLeftString(#"0",(16,BitsN.toHexString ptb))," pt_ofs=", 4059 Nat.toString(BitsN.toNat pt_ofs)," pte_addr=0x", 4060 L3.padLeftString(#"0",(16,BitsN.toHexString pte_addr)), 4061 " pte=0x", 4062 L3.padLeftString(#"0",(16,BitsN.toHexString(reg'SV_PTE pte)))]) 4063 :: 4064 (!log)) 4065 ; if not(#PTE_V(pte : SV_PTE)) 4066 then ( log := ((4,"addr_translate: invalid PTE") :: (!log)) 4067 ; NONE 4068 ) 4069 else if ((#PTE_T(pte : SV_PTE)) = (BitsN.B(0x0,4))) orelse 4070 ((#PTE_T(pte : SV_PTE)) = (BitsN.B(0x1,4))) 4071 then if level = 0 4072 then ( log := 4073 ((4,"last-level pt contains a pointer PTE!") 4074 :: 4075 (!log)) 4076 ; NONE 4077 ) 4078 else walk64 4079 (vAddr, 4080 (ft, 4081 (ac, 4082 (priv, 4083 (BitsN.zeroExtend 64 4084 (BitsN.<< 4085 (#PTE_PPNi(pte : SV_PTE),PAGESIZE_BITS)), 4086 Nat.-(level,1)))))) 4087 else if not(checkMemPermission(ft,(ac,(priv,#PTE_T(pte : SV_PTE))))) 4088 then ( log := ((4,"PTE permission check failure!") :: (!log)) 4089 ; NONE 4090 ) 4091 else let 4092 val pte_w = ref pte 4093 in 4094 let 4095 val old_r = #PTE_R(pte : SV_PTE) 4096 val old_d = #PTE_D(pte : SV_PTE) 4097 in 4098 ( pte_w := (SV_PTE_PTE_R_rupd((!pte_w),true)) 4099 ; if ac = Write 4100 then pte_w := (SV_PTE_PTE_D_rupd((!pte_w),true)) 4101 else () 4102 ; if (not(old_r = (#PTE_R((!pte_w) : SV_PTE)))) orelse 4103 (not(old_d = (#PTE_D((!pte_w) : SV_PTE)))) 4104 then rawWriteData(pte_addr,(reg'SV_PTE (!pte_w),8)) 4105 else () 4106 ; let 4107 val ppn = 4108 if Nat.>(level,0) 4109 then BitsN.|| 4110 (BitsN.zeroExtend 38 4111 (BitsN.<< 4112 (BitsN.>>+ 4113 (#PTE_PPNi(pte : SV_PTE), 4114 Nat.*(level,LEVEL_BITS)), 4115 Nat.*(level,LEVEL_BITS))), 4116 BitsN.zeroExtend 38 4117 (BitsN.&& 4118 (#Sv_VPNi(va : SV_Vaddr), 4119 BitsN.- 4120 (BitsN.<< 4121 (BitsN.B(0x1,36), 4122 Nat.*(level,LEVEL_BITS)), 4123 BitsN.B(0x1,36))))) 4124 else #PTE_PPNi(pte : SV_PTE) 4125 in 4126 Option.SOME 4127 (BitsN.zeroExtend 64 4128 (BitsN.@@(ppn,#Sv_PgOfs(va : SV_Vaddr))), 4129 ((!pte_w), 4130 (level,(isGlobal(#PTE_T(pte : SV_PTE)),pte_addr)))) 4131 end 4132 ) 4133 end 4134 end 4135 ) 4136 end; 4137 4138fun curASID () = 4139 BitsN.bits(Nat.-(ASID_SIZE,1),0) (#sasid((SCSR ()) : SupervisorCSR)); 4140 4141fun mkTLBEntry (asid,(global,(vAddr,(pAddr,(pte,(i,pteAddr)))))) = 4142 let 4143 val ent = ref {age = BitsN.B(0x0,64), asid = BitsN.B(0x0,6), 4144 global = false, pAddr = BitsN.B(0x0,64), 4145 pte = 4146 {PTE_D = false, PTE_PPNi = BitsN.B(0x0,38), PTE_R = false, 4147 PTE_SW = BitsN.B(0x0,3), PTE_T = BitsN.B(0x0,4), PTE_V = false, 4148 sv_pte'rst = BitsN.B(0x0,16)}, pteAddr = BitsN.B(0x0,64), 4149 vAddr = BitsN.B(0x0,64), vAddrMask = BitsN.B(0x0,64), 4150 vMatchMask = BitsN.B(0x0,64)} 4151 in 4152 ( ent := (TLBEntry_asid_rupd((!ent),asid)) 4153 ; ent := (TLBEntry_global_rupd((!ent),global)) 4154 ; ent := (TLBEntry_pte_rupd((!ent),pte)) 4155 ; ent := (TLBEntry_pteAddr_rupd((!ent),pteAddr)) 4156 ; ent := 4157 (TLBEntry_vAddrMask_rupd 4158 ((!ent), 4159 BitsN.- 4160 (BitsN.<< 4161 (BitsN.B(0x1,64),Nat.+(Nat.*(LEVEL_BITS,i),PAGESIZE_BITS)), 4162 BitsN.B(0x1,64)))) 4163 ; ent := 4164 (TLBEntry_vMatchMask_rupd 4165 ((!ent), 4166 BitsN.?? 4167 (BitsN.signExtend 64 (BitsN.B(0x1,1)), 4168 #vAddrMask((!ent) : TLBEntry)))) 4169 ; ent := 4170 (TLBEntry_vAddr_rupd 4171 ((!ent),BitsN.&&(vAddr,#vMatchMask((!ent) : TLBEntry)))) 4172 ; ent := 4173 (TLBEntry_pAddr_rupd 4174 ((!ent), 4175 BitsN.<< 4176 (BitsN.>>(pAddr,Nat.+(PAGESIZE_BITS,Nat.*(LEVEL_BITS,i))), 4177 Nat.+(PAGESIZE_BITS,Nat.*(LEVEL_BITS,i))))) 4178 ; ent := 4179 (TLBEntry_age_rupd 4180 ((!ent),Map.lookup((!c_cycles),BitsN.toNat (!procID)))) 4181 ; (!ent) 4182 ) 4183 end; 4184 4185val TLBEntries = 16 4186 4187fun lookupTLB (asid,(vAddr,tlb)) = 4188 let 4189 val ent = ref NONE 4190 in 4191 ( L3.for 4192 (0,Nat.-(TLBEntries,1), 4193 fn i => 4194 case Map.lookup(tlb,BitsN.toNat(BitsN.fromNat(i,4))) of 4195 Option.SOME e => 4196 (if ((!ent) = NONE) andalso 4197 (((#global(e : TLBEntry)) orelse 4198 ((#asid(e : TLBEntry)) = asid)) andalso 4199 ((#vAddr(e : TLBEntry)) = 4200 (BitsN.&&(vAddr,#vMatchMask(e : TLBEntry))))) 4201 then ent := (Option.SOME(e,BitsN.fromNat(i,4))) 4202 else ()) 4203 | NONE => ()) 4204 ; (!ent) 4205 ) 4206 end; 4207 4208fun addToTLB (asid,(vAddr,(pAddr,(pte,(pteAddr,(i,(global,curTLB))))))) = 4209 let 4210 val ent = ref (mkTLBEntry 4211 (asid,(global,(vAddr,(pAddr,(pte,(i,pteAddr))))))) 4212 in 4213 let 4214 val tlb = ref (Map.copy curTLB) 4215 in 4216 let 4217 val oldest = ref (BitsN.signExtend 64 (BitsN.B(0x1,1))) 4218 in 4219 let 4220 val addIdx = ref 0 4221 in 4222 let 4223 val added = ref false 4224 in 4225 ( L3.for 4226 (0,Nat.-(TLBEntries,1), 4227 fn i => 4228 case Map.lookup((!tlb),BitsN.toNat(BitsN.fromNat(i,4))) of 4229 Option.SOME e => 4230 (if BitsN.<+(#age(e : TLBEntry),(!oldest)) 4231 then ( oldest := (#age(e : TLBEntry)) 4232 ; addIdx := i 4233 ) 4234 else ()) 4235 | NONE => 4236 if not (!added) 4237 then ( let 4238 val x = BitsN.fromNat(i,4) 4239 in 4240 tlb := 4241 (Map.update 4242 ((!tlb),BitsN.toNat x, 4243 Option.SOME (!ent))) 4244 end 4245 ; added := true 4246 ) 4247 else ()) 4248 ; if not (!added) 4249 then let 4250 val x = BitsN.fromNat((!addIdx),4) 4251 in 4252 tlb := 4253 (Map.update 4254 ((!tlb),BitsN.toNat x,Option.SOME (!ent))) 4255 end 4256 else () 4257 ; (!tlb) 4258 ) 4259 end 4260 end 4261 end 4262 end 4263 end; 4264 4265fun flushTLB (asid,(addr,curTLB)) = 4266 let 4267 val tlb = ref (Map.copy curTLB) 4268 in 4269 ( L3.for 4270 (0,Nat.-(TLBEntries,1), 4271 fn i => 4272 case (Map.lookup((!tlb),BitsN.toNat(BitsN.fromNat(i,4))),addr) of 4273 (Option.SOME e,Option.SOME va) => 4274 (if ((asid = (BitsN.B(0x0,6))) orelse 4275 ((asid = (#asid(e : TLBEntry))) andalso 4276 (not(#global(e : TLBEntry))))) andalso 4277 ((#vAddr(e : TLBEntry)) = 4278 (BitsN.&&(va,#vMatchMask(e : TLBEntry)))) 4279 then let 4280 val x = BitsN.fromNat(i,4) 4281 in 4282 tlb := (Map.update((!tlb),BitsN.toNat x,NONE)) 4283 end 4284 else ()) 4285 | (Option.SOME e,NONE) => 4286 (if (asid = (BitsN.B(0x0,6))) orelse 4287 ((asid = (#asid(e : TLBEntry))) andalso 4288 (not(#global(e : TLBEntry)))) 4289 then let 4290 val x = BitsN.fromNat(i,4) 4291 in 4292 tlb := (Map.update((!tlb),BitsN.toNat x,NONE)) 4293 end 4294 else ()) 4295 | (NONE,_) => ()) 4296 ; (!tlb) 4297 ) 4298 end; 4299 4300fun TLB () = Map.lookup((!c_tlb),BitsN.toNat (!procID)); 4301 4302fun write'TLB value = 4303 c_tlb := (Map.update((!c_tlb),BitsN.toNat (!procID),Map.copy value)); 4304 4305fun translate64 (vAddr,(ft,(ac,(priv,level)))) = 4306 let 4307 val asid = curASID () 4308 in 4309 case lookupTLB(asid,(vAddr,TLB ())) of 4310 Option.SOME(e,idx) => 4311 (if checkMemPermission 4312 (ft,(ac,(priv,#PTE_T((#pte(e : TLBEntry)) : SV_PTE)))) 4313 then ( log := ((4,"TLB hit!") :: (!log)) 4314 ; if (ac = Write) andalso 4315 (not(#PTE_D((#pte(e : TLBEntry)) : SV_PTE))) 4316 then let 4317 val ent = ref e 4318 in 4319 ( let 4320 val x0 = #pte((!ent) : TLBEntry) 4321 in 4322 ent := 4323 (TLBEntry_pte_rupd 4324 ((!ent),SV_PTE_PTE_D_rupd(x0,true))) 4325 end 4326 ; rawWriteData 4327 (#pteAddr((!ent) : TLBEntry), 4328 (reg'SV_PTE(#pte((!ent) : TLBEntry)),8)) 4329 ; let 4330 val tlb = ref (Map.copy(TLB ())) 4331 in 4332 ( let 4333 val x = idx 4334 in 4335 tlb := 4336 (Map.update 4337 ((!tlb),BitsN.toNat x, 4338 Option.SOME (!ent))) 4339 end 4340 ; write'TLB (!tlb) 4341 ) 4342 end 4343 ) 4344 end 4345 else () 4346 ; Option.SOME 4347 (BitsN.|| 4348 (#pAddr(e : TLBEntry), 4349 BitsN.&&(vAddr,#vAddrMask(e : TLBEntry)))) 4350 ) 4351 else ( log := ((4,"TLB permission check failure") :: (!log)) 4352 ; NONE 4353 )) 4354 | NONE => 4355 ( log := ((4,"TLB miss!") :: (!log)) 4356 ; case walk64 4357 (vAddr, 4358 (ft,(ac,(priv,(#sptbr((SCSR ()) : SupervisorCSR),level))))) of 4359 Option.SOME(pAddr,(pte,(i,(global,pteAddr)))) => 4360 ( write'TLB 4361 (addToTLB 4362 (asid, 4363 (vAddr,(pAddr,(pte,(pteAddr,(i,(global,TLB ())))))))) 4364 ; Option.SOME pAddr 4365 ) 4366 | NONE => NONE 4367 ) 4368 end; 4369 4370fun translateAddr (vAddr,(ft,ac)) = 4371 let 4372 val priv = 4373 privilege 4374 (if (#MMPRV((#mstatus((MCSR ()) : MachineCSR)) : mstatus)) andalso 4375 (ft = Data) 4376 then #MPRV1((#mstatus((MCSR ()) : MachineCSR)) : mstatus) 4377 else #MPRV((#mstatus((MCSR ()) : MachineCSR)) : mstatus)) 4378 in 4379 case (vmType(#VM((#mstatus((MCSR ()) : MachineCSR)) : mstatus)),priv) of 4380 (Mbare,_) => Option.SOME vAddr 4381 | (_,Machine) => Option.SOME vAddr 4382 | (Sv39,_) => translate64(vAddr,(ft,(ac,(priv,2)))) 4383 | (Sv48,_) => translate64(vAddr,(ft,(ac,(priv,3)))) 4384 | _ => NONE 4385 end; 4386 4387fun matchLoadReservation vAddr = 4388 (Option.isSome(ReserveLoad ())) andalso 4389 ((Option.valOf(ReserveLoad ())) = vAddr); 4390 4391fun branchTo newPC = 4392 ( write'NextFetch(Option.SOME(BranchTo newPC)) 4393 ; let 4394 val x = Delta () 4395 in 4396 write'Delta(StateDelta_addr_rupd(x,Option.SOME newPC)) 4397 end 4398 ); 4399 4400fun dfn'ADDI (rd,(rs1,imm)) = 4401 ( write'GPR(BitsN.+(GPR rs1,BitsN.signExtend 64 imm),rd) 4402 ; let 4403 val x = Delta () 4404 in 4405 write'Delta 4406 (StateDelta_data1_rupd 4407 (x,Option.SOME(BitsN.+(GPR rs1,BitsN.signExtend 64 imm)))) 4408 end 4409 ); 4410 4411fun dfn'ADDIW (rd,(rs1,imm)) = 4412 if in32BitMode () 4413 then signalException Illegal_Instr 4414 else let 4415 val temp = BitsN.+(GPR rs1,BitsN.signExtend 64 imm) 4416 in 4417 ( write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) temp),rd) 4418 ; let 4419 val x = Delta () 4420 in 4421 write'Delta 4422 (StateDelta_data1_rupd 4423 (x, 4424 Option.SOME 4425 (BitsN.signExtend 64 (BitsN.bits(31,0) temp)))) 4426 end 4427 ) 4428 end; 4429 4430fun dfn'SLTI (rd,(rs1,imm)) = 4431 let 4432 val v1 = 4433 if in32BitMode () 4434 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 4435 else GPR rs1 4436 in 4437 ( write'GPR 4438 (BitsN.fromBool 64 (BitsN.<(v1,BitsN.signExtend 64 imm)),rd) 4439 ; let 4440 val x = Delta () 4441 in 4442 write'Delta 4443 (StateDelta_data1_rupd 4444 (x, 4445 Option.SOME 4446 (BitsN.fromBool 64 (BitsN.<(v1,BitsN.signExtend 64 imm))))) 4447 end 4448 ) 4449 end; 4450 4451fun dfn'SLTIU (rd,(rs1,imm)) = 4452 let 4453 val v1 = 4454 if in32BitMode () 4455 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 4456 else GPR rs1 4457 in 4458 ( write'GPR 4459 (BitsN.fromBool 64 (BitsN.<+(v1,BitsN.signExtend 64 imm)),rd) 4460 ; let 4461 val x = Delta () 4462 in 4463 write'Delta 4464 (StateDelta_data1_rupd 4465 (x, 4466 Option.SOME 4467 (BitsN.fromBool 64 (BitsN.<+(v1,BitsN.signExtend 64 imm))))) 4468 end 4469 ) 4470 end; 4471 4472fun dfn'ANDI (rd,(rs1,imm)) = 4473 ( write'GPR(BitsN.&&(GPR rs1,BitsN.signExtend 64 imm),rd) 4474 ; let 4475 val x = Delta () 4476 in 4477 write'Delta 4478 (StateDelta_data1_rupd 4479 (x,Option.SOME(BitsN.&&(GPR rs1,BitsN.signExtend 64 imm)))) 4480 end 4481 ); 4482 4483fun dfn'ORI (rd,(rs1,imm)) = 4484 ( write'GPR(BitsN.||(GPR rs1,BitsN.signExtend 64 imm),rd) 4485 ; let 4486 val x = Delta () 4487 in 4488 write'Delta 4489 (StateDelta_data1_rupd 4490 (x,Option.SOME(BitsN.||(GPR rs1,BitsN.signExtend 64 imm)))) 4491 end 4492 ); 4493 4494fun dfn'XORI (rd,(rs1,imm)) = 4495 ( write'GPR(BitsN.??(GPR rs1,BitsN.signExtend 64 imm),rd) 4496 ; let 4497 val x = Delta () 4498 in 4499 write'Delta 4500 (StateDelta_data1_rupd 4501 (x,Option.SOME(BitsN.??(GPR rs1,BitsN.signExtend 64 imm)))) 4502 end 4503 ); 4504 4505fun dfn'SLLI (rd,(rs1,imm)) = 4506 if (in32BitMode ()) andalso (BitsN.bit(imm,5)) 4507 then signalException Illegal_Instr 4508 else ( write'GPR(BitsN.<<(GPR rs1,BitsN.toNat imm),rd) 4509 ; let 4510 val x = Delta () 4511 in 4512 write'Delta 4513 (StateDelta_data1_rupd 4514 (x,Option.SOME(BitsN.<<(GPR rs1,BitsN.toNat imm)))) 4515 end 4516 ); 4517 4518fun dfn'SRLI (rd,(rs1,imm)) = 4519 if (in32BitMode ()) andalso (BitsN.bit(imm,5)) 4520 then signalException Illegal_Instr 4521 else let 4522 val v1 = 4523 if in32BitMode () 4524 then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs1)) 4525 else GPR rs1 4526 in 4527 ( write'GPR(BitsN.>>+(v1,BitsN.toNat imm),rd) 4528 ; let 4529 val x = Delta () 4530 in 4531 write'Delta 4532 (StateDelta_data1_rupd 4533 (x,Option.SOME(BitsN.>>+(v1,BitsN.toNat imm)))) 4534 end 4535 ) 4536 end; 4537 4538fun dfn'SRAI (rd,(rs1,imm)) = 4539 if (in32BitMode ()) andalso (BitsN.bit(imm,5)) 4540 then signalException Illegal_Instr 4541 else let 4542 val v1 = 4543 if in32BitMode () 4544 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 4545 else GPR rs1 4546 in 4547 ( write'GPR(BitsN.>>(v1,BitsN.toNat imm),rd) 4548 ; let 4549 val x = Delta () 4550 in 4551 write'Delta 4552 (StateDelta_data1_rupd 4553 (x,Option.SOME(BitsN.>>(v1,BitsN.toNat imm)))) 4554 end 4555 ) 4556 end; 4557 4558fun dfn'SLLIW (rd,(rs1,imm)) = 4559 if in32BitMode () 4560 then signalException Illegal_Instr 4561 else ( write'GPR 4562 (BitsN.signExtend 64 4563 (BitsN.<<(BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm)),rd) 4564 ; let 4565 val x = Delta () 4566 in 4567 write'Delta 4568 (StateDelta_data1_rupd 4569 (x, 4570 Option.SOME 4571 (BitsN.signExtend 64 4572 (BitsN.<< 4573 (BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm))))) 4574 end 4575 ); 4576 4577fun dfn'SRLIW (rd,(rs1,imm)) = 4578 if in32BitMode () 4579 then signalException Illegal_Instr 4580 else ( write'GPR 4581 (BitsN.signExtend 64 4582 (BitsN.>>+(BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm)),rd) 4583 ; let 4584 val x = Delta () 4585 in 4586 write'Delta 4587 (StateDelta_data1_rupd 4588 (x, 4589 Option.SOME 4590 (BitsN.signExtend 64 4591 (BitsN.>>+ 4592 (BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm))))) 4593 end 4594 ); 4595 4596fun dfn'SRAIW (rd,(rs1,imm)) = 4597 if in32BitMode () 4598 then signalException Illegal_Instr 4599 else ( write'GPR 4600 (BitsN.signExtend 64 4601 (BitsN.>>(BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm)),rd) 4602 ; let 4603 val x = Delta () 4604 in 4605 write'Delta 4606 (StateDelta_data1_rupd 4607 (x, 4608 Option.SOME 4609 (BitsN.signExtend 64 4610 (BitsN.>> 4611 (BitsN.bits(31,0) (GPR rs1),BitsN.toNat imm))))) 4612 end 4613 ); 4614 4615fun dfn'LUI (rd,imm) = 4616 ( write'GPR(BitsN.signExtend 64 (BitsN.@@(imm,BitsN.B(0x0,12))),rd) 4617 ; let 4618 val x = Delta () 4619 in 4620 write'Delta 4621 (StateDelta_data1_rupd 4622 (x, 4623 Option.SOME 4624 (BitsN.signExtend 64 (BitsN.@@(imm,BitsN.B(0x0,12)))))) 4625 end 4626 ); 4627 4628fun dfn'AUIPC (rd,imm) = 4629 ( write'GPR 4630 (BitsN.+(PC (),BitsN.signExtend 64 (BitsN.@@(imm,BitsN.B(0x0,12)))), 4631 rd) 4632 ; let 4633 val x = Delta () 4634 in 4635 write'Delta 4636 (StateDelta_data1_rupd 4637 (x, 4638 Option.SOME 4639 (BitsN.+ 4640 (PC (), 4641 BitsN.signExtend 64 (BitsN.@@(imm,BitsN.B(0x0,12))))))) 4642 end 4643 ); 4644 4645fun dfn'ADD (rd,(rs1,rs2)) = 4646 ( write'GPR(BitsN.+(GPR rs1,GPR rs2),rd) 4647 ; let 4648 val x = Delta () 4649 in 4650 write'Delta 4651 (StateDelta_data1_rupd(x,Option.SOME(BitsN.+(GPR rs1,GPR rs2)))) 4652 end 4653 ); 4654 4655fun dfn'ADDW (rd,(rs1,rs2)) = 4656 if in32BitMode () 4657 then signalException Illegal_Instr 4658 else ( write'GPR 4659 (BitsN.signExtend 64 4660 (BitsN.+ 4661 (BitsN.bits(31,0) (GPR rs1),BitsN.bits(31,0) (GPR rs2))), 4662 rd) 4663 ; let 4664 val x = Delta () 4665 in 4666 write'Delta 4667 (StateDelta_data1_rupd 4668 (x, 4669 Option.SOME 4670 (BitsN.signExtend 64 4671 (BitsN.+ 4672 (BitsN.bits(31,0) (GPR rs1), 4673 BitsN.bits(31,0) (GPR rs2)))))) 4674 end 4675 ); 4676 4677fun dfn'SUB (rd,(rs1,rs2)) = 4678 ( write'GPR(BitsN.-(GPR rs1,GPR rs2),rd) 4679 ; let 4680 val x = Delta () 4681 in 4682 write'Delta 4683 (StateDelta_data1_rupd(x,Option.SOME(BitsN.-(GPR rs1,GPR rs2)))) 4684 end 4685 ); 4686 4687fun dfn'SUBW (rd,(rs1,rs2)) = 4688 if in32BitMode () 4689 then signalException Illegal_Instr 4690 else ( write'GPR 4691 (BitsN.signExtend 64 4692 (BitsN.- 4693 (BitsN.bits(31,0) (GPR rs1),BitsN.bits(31,0) (GPR rs2))), 4694 rd) 4695 ; let 4696 val x = Delta () 4697 in 4698 write'Delta 4699 (StateDelta_data1_rupd 4700 (x, 4701 Option.SOME 4702 (BitsN.signExtend 64 4703 (BitsN.- 4704 (BitsN.bits(31,0) (GPR rs1), 4705 BitsN.bits(31,0) (GPR rs2)))))) 4706 end 4707 ); 4708 4709fun dfn'SLT (rd,(rs1,rs2)) = 4710 let 4711 val v1 = 4712 if in32BitMode () 4713 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 4714 else GPR rs1 4715 val v2 = 4716 if in32BitMode () 4717 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) 4718 else GPR rs2 4719 in 4720 ( write'GPR(BitsN.fromBool 64 (BitsN.<(v1,v2)),rd) 4721 ; let 4722 val x = Delta () 4723 in 4724 write'Delta 4725 (StateDelta_data1_rupd 4726 (x,Option.SOME(BitsN.fromBool 64 (BitsN.<(v1,v2))))) 4727 end 4728 ) 4729 end; 4730 4731fun dfn'SLTU (rd,(rs1,rs2)) = 4732 let 4733 val v1 = 4734 if in32BitMode () 4735 then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs1)) 4736 else GPR rs1 4737 val v2 = 4738 if in32BitMode () 4739 then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs2)) 4740 else GPR rs2 4741 in 4742 ( write'GPR(BitsN.fromBool 64 (BitsN.<+(v1,v2)),rd) 4743 ; let 4744 val x = Delta () 4745 in 4746 write'Delta 4747 (StateDelta_data1_rupd 4748 (x,Option.SOME(BitsN.fromBool 64 (BitsN.<+(v1,v2))))) 4749 end 4750 ) 4751 end; 4752 4753fun dfn'AND (rd,(rs1,rs2)) = 4754 ( write'GPR(BitsN.&&(GPR rs1,GPR rs2),rd) 4755 ; let 4756 val x = Delta () 4757 in 4758 write'Delta 4759 (StateDelta_data1_rupd(x,Option.SOME(BitsN.&&(GPR rs1,GPR rs2)))) 4760 end 4761 ); 4762 4763fun dfn'OR (rd,(rs1,rs2)) = 4764 ( write'GPR(BitsN.||(GPR rs1,GPR rs2),rd) 4765 ; let 4766 val x = Delta () 4767 in 4768 write'Delta 4769 (StateDelta_data1_rupd(x,Option.SOME(BitsN.||(GPR rs1,GPR rs2)))) 4770 end 4771 ); 4772 4773fun dfn'XOR (rd,(rs1,rs2)) = 4774 ( write'GPR(BitsN.??(GPR rs1,GPR rs2),rd) 4775 ; let 4776 val x = Delta () 4777 in 4778 write'Delta 4779 (StateDelta_data1_rupd(x,Option.SOME(BitsN.??(GPR rs1,GPR rs2)))) 4780 end 4781 ); 4782 4783fun dfn'SLL (rd,(rs1,rs2)) = 4784 if in32BitMode () 4785 then ( write'GPR 4786 (BitsN.<<^ 4787 (GPR rs1,BitsN.zeroExtend 64 (BitsN.bits(4,0) (GPR rs2))), 4788 rd) 4789 ; let 4790 val x = Delta () 4791 in 4792 write'Delta 4793 (StateDelta_data1_rupd 4794 (x, 4795 Option.SOME 4796 (BitsN.<<^ 4797 (GPR rs1, 4798 BitsN.zeroExtend 64 (BitsN.bits(4,0) (GPR rs2)))))) 4799 end 4800 ) 4801 else ( write'GPR 4802 (BitsN.<<^ 4803 (GPR rs1,BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2))),rd) 4804 ; let 4805 val x = Delta () 4806 in 4807 write'Delta 4808 (StateDelta_data1_rupd 4809 (x, 4810 Option.SOME 4811 (BitsN.<<^ 4812 (GPR rs1, 4813 BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2)))))) 4814 end 4815 ); 4816 4817fun dfn'SLLW (rd,(rs1,rs2)) = 4818 if in32BitMode () 4819 then signalException Illegal_Instr 4820 else ( write'GPR 4821 (BitsN.signExtend 64 4822 (BitsN.<<^ 4823 (BitsN.bits(31,0) (GPR rs1), 4824 BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) 4825 ; let 4826 val x = Delta () 4827 in 4828 write'Delta 4829 (StateDelta_data1_rupd 4830 (x, 4831 Option.SOME 4832 (BitsN.signExtend 64 4833 (BitsN.<<^ 4834 (BitsN.bits(31,0) (GPR rs1), 4835 BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2))))))) 4836 end 4837 ); 4838 4839fun dfn'SRL (rd,(rs1,rs2)) = 4840 if in32BitMode () 4841 then ( write'GPR 4842 (BitsN.zeroExtend 64 4843 (BitsN.>>+^ 4844 (BitsN.bits(31,0) (GPR rs1), 4845 BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) 4846 ; let 4847 val x = Delta () 4848 in 4849 write'Delta 4850 (StateDelta_data1_rupd 4851 (x, 4852 Option.SOME 4853 (BitsN.zeroExtend 64 4854 (BitsN.>>+^ 4855 (BitsN.bits(31,0) (GPR rs1), 4856 BitsN.zeroExtend 32 4857 (BitsN.bits(4,0) (GPR rs2))))))) 4858 end 4859 ) 4860 else ( write'GPR 4861 (BitsN.>>+^ 4862 (GPR rs1,BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2))),rd) 4863 ; let 4864 val x = Delta () 4865 in 4866 write'Delta 4867 (StateDelta_data1_rupd 4868 (x, 4869 Option.SOME 4870 (BitsN.>>+^ 4871 (GPR rs1, 4872 BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2)))))) 4873 end 4874 ); 4875 4876fun dfn'SRLW (rd,(rs1,rs2)) = 4877 if in32BitMode () 4878 then signalException Illegal_Instr 4879 else ( write'GPR 4880 (BitsN.signExtend 64 4881 (BitsN.>>+^ 4882 (BitsN.bits(31,0) (GPR rs1), 4883 BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) 4884 ; let 4885 val x = Delta () 4886 in 4887 write'Delta 4888 (StateDelta_data1_rupd 4889 (x, 4890 Option.SOME 4891 (BitsN.signExtend 64 4892 (BitsN.>>+^ 4893 (BitsN.bits(31,0) (GPR rs1), 4894 BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2))))))) 4895 end 4896 ); 4897 4898fun dfn'SRA (rd,(rs1,rs2)) = 4899 if in32BitMode () 4900 then ( write'GPR 4901 (BitsN.signExtend 64 4902 (BitsN.>>^ 4903 (BitsN.bits(31,0) (GPR rs1), 4904 BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) 4905 ; let 4906 val x = Delta () 4907 in 4908 write'Delta 4909 (StateDelta_data1_rupd 4910 (x, 4911 Option.SOME 4912 (BitsN.signExtend 64 4913 (BitsN.>>^ 4914 (BitsN.bits(31,0) (GPR rs1), 4915 BitsN.zeroExtend 32 4916 (BitsN.bits(4,0) (GPR rs2))))))) 4917 end 4918 ) 4919 else ( write'GPR 4920 (BitsN.>>^ 4921 (GPR rs1,BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2))),rd) 4922 ; let 4923 val x = Delta () 4924 in 4925 write'Delta 4926 (StateDelta_data1_rupd 4927 (x, 4928 Option.SOME 4929 (BitsN.>>^ 4930 (GPR rs1, 4931 BitsN.zeroExtend 64 (BitsN.bits(5,0) (GPR rs2)))))) 4932 end 4933 ); 4934 4935fun dfn'SRAW (rd,(rs1,rs2)) = 4936 if in32BitMode () 4937 then signalException Illegal_Instr 4938 else ( write'GPR 4939 (BitsN.signExtend 64 4940 (BitsN.>>^ 4941 (BitsN.bits(31,0) (GPR rs1), 4942 BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2)))),rd) 4943 ; let 4944 val x = Delta () 4945 in 4946 write'Delta 4947 (StateDelta_data1_rupd 4948 (x, 4949 Option.SOME 4950 (BitsN.signExtend 64 4951 (BitsN.>>^ 4952 (BitsN.bits(31,0) (GPR rs1), 4953 BitsN.zeroExtend 32 (BitsN.bits(4,0) (GPR rs2))))))) 4954 end 4955 ); 4956 4957fun dfn'MUL (rd,(rs1,rs2)) = 4958 ( write'GPR(BitsN.*(GPR rs1,GPR rs2),rd) 4959 ; let 4960 val x = Delta () 4961 in 4962 write'Delta 4963 (StateDelta_data1_rupd(x,Option.SOME(BitsN.*(GPR rs1,GPR rs2)))) 4964 end 4965 ); 4966 4967fun dfn'MULH (rd,(rs1,rs2)) = 4968 let 4969 val v1 = 4970 if in32BitMode () 4971 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 4972 else GPR rs1 4973 val v2 = 4974 if in32BitMode () 4975 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) 4976 else GPR rs2 4977 val prod = BitsN.*(BitsN.signExtend 128 v1,BitsN.signExtend 128 v2) 4978 val res = 4979 if in32BitMode () 4980 then BitsN.signExtend 64 (BitsN.bits(63,32) prod) 4981 else BitsN.signExtend 64 (BitsN.bits(127,64) prod) 4982 in 4983 ( write'GPR(res,rd) 4984 ; let 4985 val x = Delta () 4986 in 4987 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 4988 end 4989 ) 4990 end; 4991 4992fun dfn'MULHU (rd,(rs1,rs2)) = 4993 let 4994 val v1 = 4995 if in32BitMode () 4996 then BitsN.zeroExtend 128 (BitsN.bits(31,0) (GPR rs1)) 4997 else BitsN.zeroExtend 128 (GPR rs1) 4998 val v2 = 4999 if in32BitMode () 5000 then BitsN.zeroExtend 128 (BitsN.bits(31,0) (GPR rs2)) 5001 else BitsN.zeroExtend 128 (GPR rs2) 5002 val prod = BitsN.*(v1,v2) 5003 val res = 5004 if in32BitMode () 5005 then BitsN.zeroExtend 64 (BitsN.bits(63,32) prod) 5006 else BitsN.bits(127,64) prod 5007 in 5008 ( write'GPR(res,rd) 5009 ; let 5010 val x = Delta () 5011 in 5012 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 5013 end 5014 ) 5015 end; 5016 5017fun dfn'MULHSU (rd,(rs1,rs2)) = 5018 let 5019 val v1 = 5020 if in32BitMode () 5021 then BitsN.signExtend 128 (BitsN.bits(31,0) (GPR rs1)) 5022 else BitsN.signExtend 128 (GPR rs1) 5023 val v2 = 5024 if in32BitMode () 5025 then BitsN.zeroExtend 128 (BitsN.bits(31,0) (GPR rs2)) 5026 else BitsN.zeroExtend 128 (GPR rs2) 5027 val prod = BitsN.*(v1,v2) 5028 val res = 5029 if in32BitMode () 5030 then BitsN.signExtend 64 (BitsN.bits(63,32) prod) 5031 else BitsN.bits(127,64) prod 5032 in 5033 ( write'GPR(res,rd) 5034 ; let 5035 val x = Delta () 5036 in 5037 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 5038 end 5039 ) 5040 end; 5041 5042fun dfn'MULW (rd,(rs1,rs2)) = 5043 if in32BitMode () 5044 then signalException Illegal_Instr 5045 else let 5046 val prod = 5047 BitsN.signExtend 64 5048 (BitsN.* 5049 (BitsN.bits(31,0) (GPR rs1),BitsN.bits(31,0) (GPR rs2))) 5050 in 5051 ( write'GPR(BitsN.signExtend 64 (BitsN.bits(31,0) prod),rd) 5052 ; let 5053 val x = Delta () 5054 in 5055 write'Delta 5056 (StateDelta_data1_rupd 5057 (x, 5058 Option.SOME 5059 (BitsN.signExtend 64 (BitsN.bits(31,0) prod)))) 5060 end 5061 ) 5062 end; 5063 5064fun dfn'DIV (rd,(rs1,rs2)) = 5065 if (GPR rs2) = (BitsN.B(0x0,64)) 5066 then ( write'GPR(BitsN.signExtend 64 (BitsN.B(0x1,1)),rd) 5067 ; let 5068 val x = Delta () 5069 in 5070 write'Delta 5071 (StateDelta_data1_rupd 5072 (x,Option.SOME(BitsN.signExtend 64 (BitsN.B(0x1,1))))) 5073 end 5074 ) 5075 else ( write'GPR(BitsN.quot(GPR rs1,GPR rs2),rd) 5076 ; let 5077 val x = Delta () 5078 in 5079 write'Delta 5080 (StateDelta_data1_rupd 5081 (x,Option.SOME(BitsN.quot(GPR rs1,GPR rs2)))) 5082 end 5083 ); 5084 5085fun dfn'REM (rd,(rs1,rs2)) = 5086 if (GPR rs2) = (BitsN.B(0x0,64)) 5087 then ( write'GPR(GPR rs1,rd) 5088 ; let 5089 val x = Delta () 5090 in 5091 write'Delta(StateDelta_data1_rupd(x,Option.SOME(GPR rs1))) 5092 end 5093 ) 5094 else ( write'GPR(BitsN.rem(GPR rs1,GPR rs2),rd) 5095 ; let 5096 val x = Delta () 5097 in 5098 write'Delta 5099 (StateDelta_data1_rupd 5100 (x,Option.SOME(BitsN.rem(GPR rs1,GPR rs2)))) 5101 end 5102 ); 5103 5104fun dfn'DIVU (rd,(rs1,rs2)) = 5105 let 5106 val v1 = 5107 if in32BitMode () 5108 then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs1)) 5109 else GPR rs1 5110 val v2 = 5111 if in32BitMode () 5112 then BitsN.zeroExtend 64 (BitsN.bits(31,0) (GPR rs2)) 5113 else GPR rs2 5114 in 5115 if v2 = (BitsN.B(0x0,64)) 5116 then ( write'GPR(BitsN.signExtend 64 (BitsN.B(0x1,1)),rd) 5117 ; let 5118 val x = Delta () 5119 in 5120 write'Delta 5121 (StateDelta_data1_rupd 5122 (x,Option.SOME(BitsN.signExtend 64 (BitsN.B(0x1,1))))) 5123 end 5124 ) 5125 else ( write'GPR(BitsN.div(v1,v2),rd) 5126 ; let 5127 val x = Delta () 5128 in 5129 write'Delta 5130 (StateDelta_data1_rupd(x,Option.SOME(BitsN.div(v1,v2)))) 5131 end 5132 ) 5133 end; 5134 5135fun dfn'REMU (rd,(rs1,rs2)) = 5136 if (GPR rs2) = (BitsN.B(0x0,64)) 5137 then ( write'GPR(GPR rs1,rd) 5138 ; let 5139 val x = Delta () 5140 in 5141 write'Delta(StateDelta_data1_rupd(x,Option.SOME(GPR rs1))) 5142 end 5143 ) 5144 else ( write'GPR(BitsN.mod(GPR rs1,GPR rs2),rd) 5145 ; let 5146 val x = Delta () 5147 in 5148 write'Delta 5149 (StateDelta_data1_rupd 5150 (x,Option.SOME(BitsN.mod(GPR rs1,GPR rs2)))) 5151 end 5152 ); 5153 5154fun dfn'DIVW (rd,(rs1,rs2)) = 5155 if in32BitMode () 5156 then signalException Illegal_Instr 5157 else let 5158 val s1 = BitsN.bits(31,0) (GPR rs1) 5159 val s2 = BitsN.bits(31,0) (GPR rs2) 5160 in 5161 if s2 = (BitsN.B(0x0,32)) 5162 then ( write'GPR(BitsN.signExtend 64 (BitsN.B(0x1,1)),rd) 5163 ; let 5164 val x = Delta () 5165 in 5166 write'Delta 5167 (StateDelta_data1_rupd 5168 (x, 5169 Option.SOME 5170 (BitsN.signExtend 64 (BitsN.B(0x1,1))))) 5171 end 5172 ) 5173 else ( write'GPR(BitsN.signExtend 64 (BitsN.quot(s1,s2)),rd) 5174 ; let 5175 val x = Delta () 5176 in 5177 write'Delta 5178 (StateDelta_data1_rupd 5179 (x, 5180 Option.SOME 5181 (BitsN.signExtend 64 (BitsN.quot(s1,s2))))) 5182 end 5183 ) 5184 end; 5185 5186fun dfn'REMW (rd,(rs1,rs2)) = 5187 if in32BitMode () 5188 then signalException Illegal_Instr 5189 else let 5190 val s1 = BitsN.bits(31,0) (GPR rs1) 5191 val s2 = BitsN.bits(31,0) (GPR rs2) 5192 in 5193 if s2 = (BitsN.B(0x0,32)) 5194 then ( write'GPR(BitsN.signExtend 64 s1,rd) 5195 ; let 5196 val x = Delta () 5197 in 5198 write'Delta 5199 (StateDelta_data1_rupd 5200 (x,Option.SOME(BitsN.signExtend 64 s1))) 5201 end 5202 ) 5203 else ( write'GPR(BitsN.signExtend 64 (BitsN.rem(s1,s2)),rd) 5204 ; let 5205 val x = Delta () 5206 in 5207 write'Delta 5208 (StateDelta_data1_rupd 5209 (x, 5210 Option.SOME 5211 (BitsN.signExtend 64 (BitsN.rem(s1,s2))))) 5212 end 5213 ) 5214 end; 5215 5216fun dfn'DIVUW (rd,(rs1,rs2)) = 5217 if in32BitMode () 5218 then signalException Illegal_Instr 5219 else let 5220 val s1 = BitsN.bits(31,0) (GPR rs1) 5221 val s2 = BitsN.bits(31,0) (GPR rs2) 5222 in 5223 if s2 = (BitsN.B(0x0,32)) 5224 then ( write'GPR(BitsN.signExtend 64 (BitsN.B(0x1,1)),rd) 5225 ; let 5226 val x = Delta () 5227 in 5228 write'Delta 5229 (StateDelta_data1_rupd 5230 (x, 5231 Option.SOME 5232 (BitsN.signExtend 64 (BitsN.B(0x1,1))))) 5233 end 5234 ) 5235 else ( write'GPR(BitsN.signExtend 64 (BitsN.div(s1,s2)),rd) 5236 ; let 5237 val x = Delta () 5238 in 5239 write'Delta 5240 (StateDelta_data1_rupd 5241 (x, 5242 Option.SOME 5243 (BitsN.signExtend 64 (BitsN.div(s1,s2))))) 5244 end 5245 ) 5246 end; 5247 5248fun dfn'REMUW (rd,(rs1,rs2)) = 5249 if in32BitMode () 5250 then signalException Illegal_Instr 5251 else let 5252 val s1 = BitsN.bits(31,0) (GPR rs1) 5253 val s2 = BitsN.bits(31,0) (GPR rs2) 5254 in 5255 if s2 = (BitsN.B(0x0,32)) 5256 then ( write'GPR(BitsN.signExtend 64 s1,rd) 5257 ; let 5258 val x = Delta () 5259 in 5260 write'Delta 5261 (StateDelta_data1_rupd 5262 (x,Option.SOME(BitsN.signExtend 64 s1))) 5263 end 5264 ) 5265 else ( write'GPR(BitsN.signExtend 64 (BitsN.mod(s1,s2)),rd) 5266 ; let 5267 val x = Delta () 5268 in 5269 write'Delta 5270 (StateDelta_data1_rupd 5271 (x, 5272 Option.SOME 5273 (BitsN.signExtend 64 (BitsN.mod(s1,s2))))) 5274 end 5275 ) 5276 end; 5277 5278fun dfn'JAL (rd,imm) = 5279 let 5280 val addr = BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 imm,1)) 5281 in 5282 if not((BitsN.bits(1,0) addr) = (BitsN.B(0x0,2))) 5283 then signalAddressException(Fetch_Misaligned,addr) 5284 else ( ( write'GPR(BitsN.+(PC (),BitsN.B(0x4,64)),rd) 5285 ; let 5286 val x = Delta () 5287 in 5288 write'Delta 5289 (StateDelta_data1_rupd 5290 (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) 5291 end 5292 ) 5293 ; branchTo addr 5294 ) 5295 end; 5296 5297fun dfn'JALR (rd,(rs1,imm)) = 5298 let 5299 val addr = 5300 BitsN.&& 5301 (BitsN.+(GPR rs1,BitsN.signExtend 64 imm), 5302 BitsN.signExtend 64 (BitsN.B(0x2,2))) 5303 in 5304 if not((BitsN.bits(1,0) addr) = (BitsN.B(0x0,2))) 5305 then signalAddressException(Fetch_Misaligned,addr) 5306 else ( ( write'GPR(BitsN.+(PC (),BitsN.B(0x4,64)),rd) 5307 ; let 5308 val x = Delta () 5309 in 5310 write'Delta 5311 (StateDelta_data1_rupd 5312 (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) 5313 end 5314 ) 5315 ; branchTo addr 5316 ) 5317 end; 5318 5319fun dfn'BEQ (rs1,(rs2,offs)) = 5320 let 5321 val v1 = 5322 if in32BitMode () 5323 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 5324 else GPR rs1 5325 val v2 = 5326 if in32BitMode () 5327 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) 5328 else GPR rs2 5329 in 5330 if v1 = v2 5331 then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) 5332 else let 5333 val x = Delta () 5334 in 5335 write'Delta 5336 (StateDelta_addr_rupd 5337 (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) 5338 end 5339 end; 5340 5341fun dfn'BNE (rs1,(rs2,offs)) = 5342 let 5343 val v1 = 5344 if in32BitMode () 5345 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 5346 else GPR rs1 5347 val v2 = 5348 if in32BitMode () 5349 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) 5350 else GPR rs2 5351 in 5352 if not(v1 = v2) 5353 then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) 5354 else let 5355 val x = Delta () 5356 in 5357 write'Delta 5358 (StateDelta_addr_rupd 5359 (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) 5360 end 5361 end; 5362 5363fun dfn'BLT (rs1,(rs2,offs)) = 5364 let 5365 val v1 = 5366 if in32BitMode () 5367 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 5368 else GPR rs1 5369 val v2 = 5370 if in32BitMode () 5371 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) 5372 else GPR rs2 5373 in 5374 if BitsN.<(v1,v2) 5375 then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) 5376 else let 5377 val x = Delta () 5378 in 5379 write'Delta 5380 (StateDelta_addr_rupd 5381 (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) 5382 end 5383 end; 5384 5385fun dfn'BLTU (rs1,(rs2,offs)) = 5386 let 5387 val v1 = 5388 if in32BitMode () 5389 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 5390 else GPR rs1 5391 val v2 = 5392 if in32BitMode () 5393 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) 5394 else GPR rs2 5395 in 5396 if BitsN.<+(v1,v2) 5397 then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) 5398 else let 5399 val x = Delta () 5400 in 5401 write'Delta 5402 (StateDelta_addr_rupd 5403 (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) 5404 end 5405 end; 5406 5407fun dfn'BGE (rs1,(rs2,offs)) = 5408 let 5409 val v1 = 5410 if in32BitMode () 5411 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 5412 else GPR rs1 5413 val v2 = 5414 if in32BitMode () 5415 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) 5416 else GPR rs2 5417 in 5418 if BitsN.>=(v1,v2) 5419 then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) 5420 else let 5421 val x = Delta () 5422 in 5423 write'Delta 5424 (StateDelta_addr_rupd 5425 (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) 5426 end 5427 end; 5428 5429fun dfn'BGEU (rs1,(rs2,offs)) = 5430 let 5431 val v1 = 5432 if in32BitMode () 5433 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs1)) 5434 else GPR rs1 5435 val v2 = 5436 if in32BitMode () 5437 then BitsN.signExtend 64 (BitsN.bits(31,0) (GPR rs2)) 5438 else GPR rs2 5439 in 5440 if BitsN.>=+(v1,v2) 5441 then branchTo(BitsN.+(PC (),BitsN.<<(BitsN.signExtend 64 offs,1))) 5442 else let 5443 val x = Delta () 5444 in 5445 write'Delta 5446 (StateDelta_addr_rupd 5447 (x,Option.SOME(BitsN.+(PC (),BitsN.B(0x4,64))))) 5448 end 5449 end; 5450 5451fun dfn'LW (rd,(rs1,offs)) = 5452 let 5453 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5454 in 5455 case translateAddr(vAddr,(Data,Read)) of 5456 Option.SOME pAddr => 5457 let 5458 val val' = 5459 BitsN.signExtend 64 (BitsN.bits(31,0) (rawReadData pAddr)) 5460 in 5461 ( write'GPR(val',rd) 5462 ; let 5463 val x = Delta () 5464 in 5465 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5466 end 5467 ; let 5468 val x = Delta () 5469 in 5470 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 5471 end 5472 ) 5473 end 5474 | NONE => signalAddressException(Load_Fault,vAddr) 5475 end; 5476 5477fun dfn'LWU (rd,(rs1,offs)) = 5478 if in32BitMode () 5479 then signalException Illegal_Instr 5480 else let 5481 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5482 in 5483 case translateAddr(vAddr,(Data,Read)) of 5484 Option.SOME pAddr => 5485 let 5486 val val' = 5487 BitsN.zeroExtend 64 5488 (BitsN.bits(31,0) (rawReadData pAddr)) 5489 in 5490 ( write'GPR(val',rd) 5491 ; let 5492 val x = Delta () 5493 in 5494 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5495 end 5496 ; let 5497 val x = Delta () 5498 in 5499 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 5500 end 5501 ) 5502 end 5503 | NONE => signalAddressException(Load_Fault,vAddr) 5504 end; 5505 5506fun dfn'LH (rd,(rs1,offs)) = 5507 let 5508 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5509 in 5510 case translateAddr(vAddr,(Data,Read)) of 5511 Option.SOME pAddr => 5512 let 5513 val val' = 5514 BitsN.signExtend 64 (BitsN.bits(15,0) (rawReadData pAddr)) 5515 in 5516 ( write'GPR(val',rd) 5517 ; let 5518 val x = Delta () 5519 in 5520 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5521 end 5522 ; let 5523 val x = Delta () 5524 in 5525 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 5526 end 5527 ) 5528 end 5529 | NONE => signalAddressException(Load_Fault,vAddr) 5530 end; 5531 5532fun dfn'LHU (rd,(rs1,offs)) = 5533 let 5534 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5535 in 5536 case translateAddr(vAddr,(Data,Read)) of 5537 Option.SOME pAddr => 5538 let 5539 val val' = 5540 BitsN.zeroExtend 64 (BitsN.bits(15,0) (rawReadData pAddr)) 5541 in 5542 ( write'GPR(val',rd) 5543 ; let 5544 val x = Delta () 5545 in 5546 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5547 end 5548 ; let 5549 val x = Delta () 5550 in 5551 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 5552 end 5553 ) 5554 end 5555 | NONE => signalAddressException(Load_Fault,vAddr) 5556 end; 5557 5558fun dfn'LB (rd,(rs1,offs)) = 5559 let 5560 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5561 in 5562 case translateAddr(vAddr,(Data,Read)) of 5563 Option.SOME pAddr => 5564 let 5565 val val' = 5566 BitsN.signExtend 64 (BitsN.bits(7,0) (rawReadData pAddr)) 5567 in 5568 ( write'GPR(val',rd) 5569 ; let 5570 val x = Delta () 5571 in 5572 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5573 end 5574 ; let 5575 val x = Delta () 5576 in 5577 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 5578 end 5579 ) 5580 end 5581 | NONE => signalAddressException(Load_Fault,vAddr) 5582 end; 5583 5584fun dfn'LBU (rd,(rs1,offs)) = 5585 let 5586 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5587 in 5588 case translateAddr(vAddr,(Data,Read)) of 5589 Option.SOME pAddr => 5590 let 5591 val val' = 5592 BitsN.zeroExtend 64 (BitsN.bits(7,0) (rawReadData pAddr)) 5593 in 5594 ( write'GPR(val',rd) 5595 ; let 5596 val x = Delta () 5597 in 5598 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5599 end 5600 ; let 5601 val x = Delta () 5602 in 5603 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 5604 end 5605 ) 5606 end 5607 | NONE => signalAddressException(Load_Fault,vAddr) 5608 end; 5609 5610fun dfn'LD (rd,(rs1,offs)) = 5611 if in32BitMode () 5612 then signalException Illegal_Instr 5613 else let 5614 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5615 in 5616 case translateAddr(vAddr,(Data,Read)) of 5617 Option.SOME pAddr => 5618 let 5619 val val' = rawReadData pAddr 5620 in 5621 ( write'GPR(val',rd) 5622 ; let 5623 val x = Delta () 5624 in 5625 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5626 end 5627 ; let 5628 val x = Delta () 5629 in 5630 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 5631 end 5632 ) 5633 end 5634 | NONE => signalAddressException(Load_Fault,vAddr) 5635 end; 5636 5637fun dfn'SW (rs1,(rs2,offs)) = 5638 let 5639 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5640 in 5641 case translateAddr(vAddr,(Data,Write)) of 5642 Option.SOME pAddr => 5643 let 5644 val data = GPR rs2 5645 in 5646 ( rawWriteData(pAddr,(data,4)) 5647 ; let 5648 val x = Delta () 5649 in 5650 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5651 end 5652 ; let 5653 val x = Delta () 5654 in 5655 write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) 5656 end 5657 ; let 5658 val x = Delta () 5659 in 5660 write'Delta 5661 (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x4,32)))) 5662 end 5663 ) 5664 end 5665 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 5666 end; 5667 5668fun dfn'SH (rs1,(rs2,offs)) = 5669 let 5670 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5671 in 5672 case translateAddr(vAddr,(Data,Write)) of 5673 Option.SOME pAddr => 5674 let 5675 val data = GPR rs2 5676 in 5677 ( rawWriteData(pAddr,(data,2)) 5678 ; let 5679 val x = Delta () 5680 in 5681 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5682 end 5683 ; let 5684 val x = Delta () 5685 in 5686 write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) 5687 end 5688 ; let 5689 val x = Delta () 5690 in 5691 write'Delta 5692 (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x2,32)))) 5693 end 5694 ) 5695 end 5696 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 5697 end; 5698 5699fun dfn'SB (rs1,(rs2,offs)) = 5700 let 5701 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5702 in 5703 case translateAddr(vAddr,(Data,Write)) of 5704 Option.SOME pAddr => 5705 let 5706 val data = GPR rs2 5707 in 5708 ( rawWriteData(pAddr,(data,1)) 5709 ; let 5710 val x = Delta () 5711 in 5712 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5713 end 5714 ; let 5715 val x = Delta () 5716 in 5717 write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) 5718 end 5719 ; let 5720 val x = Delta () 5721 in 5722 write'Delta 5723 (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x1,32)))) 5724 end 5725 ) 5726 end 5727 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 5728 end; 5729 5730fun dfn'SD (rs1,(rs2,offs)) = 5731 if in32BitMode () 5732 then signalException Illegal_Instr 5733 else let 5734 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 5735 in 5736 case translateAddr(vAddr,(Data,Write)) of 5737 Option.SOME pAddr => 5738 let 5739 val data = GPR rs2 5740 in 5741 ( rawWriteData(pAddr,(data,8)) 5742 ; let 5743 val x = Delta () 5744 in 5745 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5746 end 5747 ; let 5748 val x = Delta () 5749 in 5750 write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) 5751 end 5752 ; let 5753 val x = Delta () 5754 in 5755 write'Delta 5756 (StateDelta_st_width_rupd 5757 (x,Option.SOME(BitsN.B(0x8,32)))) 5758 end 5759 ) 5760 end 5761 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 5762 end; 5763 5764fun dfn'FENCE (rd,(rs1,(pred,succ))) = (); 5765 5766fun dfn'FENCE_I (rd,(rs1,imm)) = (); 5767 5768fun dfn'LR_W (aq,(rl,(rd,rs1))) = 5769 let 5770 val vAddr = GPR rs1 5771 in 5772 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 5773 then signalAddressException(AMO_Misaligned,vAddr) 5774 else case translateAddr(vAddr,(Data,Read)) of 5775 Option.SOME pAddr => 5776 ( ( write'GPR 5777 (BitsN.signExtend 64 5778 (BitsN.bits(31,0) (rawReadData pAddr)),rd) 5779 ; let 5780 val x = Delta () 5781 in 5782 write'Delta 5783 (StateDelta_data1_rupd 5784 (x, 5785 Option.SOME 5786 (BitsN.signExtend 64 5787 (BitsN.bits(31,0) (rawReadData pAddr))))) 5788 end 5789 ) 5790 ; write'ReserveLoad(Option.SOME vAddr) 5791 ) 5792 | NONE => signalAddressException(Load_Fault,vAddr) 5793 end; 5794 5795fun dfn'LR_D (aq,(rl,(rd,rs1))) = 5796 if in32BitMode () 5797 then signalException Illegal_Instr 5798 else let 5799 val vAddr = GPR rs1 5800 in 5801 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 5802 then signalAddressException(AMO_Misaligned,vAddr) 5803 else case translateAddr(vAddr,(Data,Read)) of 5804 Option.SOME pAddr => 5805 ( ( write'GPR(rawReadData pAddr,rd) 5806 ; let 5807 val x = Delta () 5808 in 5809 write'Delta 5810 (StateDelta_data1_rupd 5811 (x,Option.SOME(rawReadData pAddr))) 5812 end 5813 ) 5814 ; write'ReserveLoad(Option.SOME vAddr) 5815 ) 5816 | NONE => signalAddressException(Load_Fault,vAddr) 5817 end; 5818 5819fun dfn'SC_W (aq,(rl,(rd,(rs1,rs2)))) = 5820 let 5821 val vAddr = GPR rs1 5822 in 5823 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 5824 then signalAddressException(AMO_Misaligned,vAddr) 5825 else if not(matchLoadReservation vAddr) 5826 then ( write'GPR(BitsN.B(0x1,64),rd) 5827 ; let 5828 val x = Delta () 5829 in 5830 write'Delta 5831 (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x1,64)))) 5832 end 5833 ) 5834 else case translateAddr(vAddr,(Data,Read)) of 5835 Option.SOME pAddr => 5836 let 5837 val data = GPR rs2 5838 in 5839 ( rawWriteData(pAddr,(data,4)) 5840 ; ( let 5841 val x = Delta () 5842 in 5843 write'Delta 5844 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 5845 end 5846 ; let 5847 val x = Delta () 5848 in 5849 write'Delta 5850 (StateDelta_data2_rupd(x,Option.SOME data)) 5851 end 5852 ; let 5853 val x = Delta () 5854 in 5855 write'Delta 5856 (StateDelta_st_width_rupd 5857 (x,Option.SOME(BitsN.B(0x4,32)))) 5858 end 5859 ) 5860 ; ( write'GPR(BitsN.B(0x0,64),rd) 5861 ; let 5862 val x = Delta () 5863 in 5864 write'Delta 5865 (StateDelta_data1_rupd 5866 (x,Option.SOME(BitsN.B(0x0,64)))) 5867 end 5868 ) 5869 ; write'ReserveLoad NONE 5870 ) 5871 end 5872 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 5873 end; 5874 5875fun dfn'SC_D (aq,(rl,(rd,(rs1,rs2)))) = 5876 if in32BitMode () 5877 then signalException Illegal_Instr 5878 else let 5879 val vAddr = GPR rs1 5880 in 5881 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 5882 then signalAddressException(AMO_Misaligned,vAddr) 5883 else if not(matchLoadReservation vAddr) 5884 then ( write'GPR(BitsN.B(0x1,64),rd) 5885 ; let 5886 val x = Delta () 5887 in 5888 write'Delta 5889 (StateDelta_data1_rupd 5890 (x,Option.SOME(BitsN.B(0x1,64)))) 5891 end 5892 ) 5893 else case translateAddr(vAddr,(Data,Read)) of 5894 Option.SOME pAddr => 5895 let 5896 val data = GPR rs2 5897 in 5898 ( rawWriteData(pAddr,(data,8)) 5899 ; ( let 5900 val x = Delta () 5901 in 5902 write'Delta 5903 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 5904 end 5905 ; let 5906 val x = Delta () 5907 in 5908 write'Delta 5909 (StateDelta_data2_rupd(x,Option.SOME data)) 5910 end 5911 ; let 5912 val x = Delta () 5913 in 5914 write'Delta 5915 (StateDelta_st_width_rupd 5916 (x,Option.SOME(BitsN.B(0x8,32)))) 5917 end 5918 ) 5919 ; ( write'GPR(BitsN.B(0x0,64),rd) 5920 ; let 5921 val x = Delta () 5922 in 5923 write'Delta 5924 (StateDelta_data1_rupd 5925 (x,Option.SOME(BitsN.B(0x0,64)))) 5926 end 5927 ) 5928 ; write'ReserveLoad NONE 5929 ) 5930 end 5931 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 5932 end; 5933 5934fun dfn'AMOSWAP_W (aq,(rl,(rd,(rs1,rs2)))) = 5935 let 5936 val vAddr = GPR rs1 5937 in 5938 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 5939 then signalAddressException(AMO_Misaligned,vAddr) 5940 else case translateAddr(vAddr,(Data,Write)) of 5941 Option.SOME pAddr => 5942 let 5943 val memv = 5944 BitsN.signExtend 64 5945 (BitsN.bits(31,0) (rawReadData pAddr)) 5946 val data = GPR rs2 5947 in 5948 ( write'GPR(memv,rd) 5949 ; rawWriteData(pAddr,(data,4)) 5950 ; ( let 5951 val x = Delta () 5952 in 5953 write'Delta 5954 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 5955 end 5956 ; let 5957 val x = Delta () 5958 in 5959 write'Delta 5960 (StateDelta_data1_rupd(x,Option.SOME memv)) 5961 end 5962 ) 5963 ; let 5964 val x = Delta () 5965 in 5966 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 5967 end 5968 ; let 5969 val x = Delta () 5970 in 5971 write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) 5972 end 5973 ; let 5974 val x = Delta () 5975 in 5976 write'Delta 5977 (StateDelta_st_width_rupd 5978 (x,Option.SOME(BitsN.B(0x4,32)))) 5979 end 5980 ) 5981 end 5982 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 5983 end; 5984 5985fun dfn'AMOSWAP_D (aq,(rl,(rd,(rs1,rs2)))) = 5986 let 5987 val vAddr = GPR rs1 5988 in 5989 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 5990 then signalAddressException(AMO_Misaligned,vAddr) 5991 else case translateAddr(vAddr,(Data,Write)) of 5992 Option.SOME pAddr => 5993 let 5994 val memv = rawReadData pAddr 5995 val data = GPR rs2 5996 in 5997 ( write'GPR(memv,rd) 5998 ; rawWriteData(pAddr,(data,8)) 5999 ; ( let 6000 val x = Delta () 6001 in 6002 write'Delta 6003 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6004 end 6005 ; let 6006 val x = Delta () 6007 in 6008 write'Delta 6009 (StateDelta_data1_rupd(x,Option.SOME memv)) 6010 end 6011 ) 6012 ; let 6013 val x = Delta () 6014 in 6015 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 6016 end 6017 ; let 6018 val x = Delta () 6019 in 6020 write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) 6021 end 6022 ; let 6023 val x = Delta () 6024 in 6025 write'Delta 6026 (StateDelta_st_width_rupd 6027 (x,Option.SOME(BitsN.B(0x8,32)))) 6028 end 6029 ) 6030 end 6031 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6032 end; 6033 6034fun dfn'AMOADD_W (aq,(rl,(rd,(rs1,rs2)))) = 6035 let 6036 val vAddr = GPR rs1 6037 in 6038 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 6039 then signalAddressException(AMO_Misaligned,vAddr) 6040 else case translateAddr(vAddr,(Data,Write)) of 6041 Option.SOME pAddr => 6042 let 6043 val memv = 6044 BitsN.signExtend 64 6045 (BitsN.bits(31,0) (rawReadData pAddr)) 6046 val data = GPR rs2 6047 in 6048 ( write'GPR(memv,rd) 6049 ; let 6050 val val' = BitsN.+(data,memv) 6051 in 6052 ( rawWriteData(pAddr,(val',4)) 6053 ; ( let 6054 val x = Delta () 6055 in 6056 write'Delta 6057 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6058 end 6059 ; let 6060 val x = Delta () 6061 in 6062 write'Delta 6063 (StateDelta_data1_rupd(x,Option.SOME memv)) 6064 end 6065 ) 6066 ; let 6067 val x = Delta () 6068 in 6069 write'Delta 6070 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6071 end 6072 ; let 6073 val x = Delta () 6074 in 6075 write'Delta 6076 (StateDelta_data2_rupd(x,Option.SOME val')) 6077 end 6078 ; let 6079 val x = Delta () 6080 in 6081 write'Delta 6082 (StateDelta_st_width_rupd 6083 (x,Option.SOME(BitsN.B(0x4,32)))) 6084 end 6085 ) 6086 end 6087 ) 6088 end 6089 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6090 end; 6091 6092fun dfn'AMOADD_D (aq,(rl,(rd,(rs1,rs2)))) = 6093 let 6094 val vAddr = GPR rs1 6095 in 6096 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 6097 then signalAddressException(AMO_Misaligned,vAddr) 6098 else case translateAddr(vAddr,(Data,Write)) of 6099 Option.SOME pAddr => 6100 let 6101 val memv = rawReadData pAddr 6102 val data = GPR rs2 6103 in 6104 ( write'GPR(memv,rd) 6105 ; let 6106 val val' = BitsN.+(data,memv) 6107 in 6108 ( rawWriteData(pAddr,(val',8)) 6109 ; ( let 6110 val x = Delta () 6111 in 6112 write'Delta 6113 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6114 end 6115 ; let 6116 val x = Delta () 6117 in 6118 write'Delta 6119 (StateDelta_data1_rupd(x,Option.SOME memv)) 6120 end 6121 ) 6122 ; let 6123 val x = Delta () 6124 in 6125 write'Delta 6126 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6127 end 6128 ; let 6129 val x = Delta () 6130 in 6131 write'Delta 6132 (StateDelta_data2_rupd(x,Option.SOME val')) 6133 end 6134 ; let 6135 val x = Delta () 6136 in 6137 write'Delta 6138 (StateDelta_st_width_rupd 6139 (x,Option.SOME(BitsN.B(0x8,32)))) 6140 end 6141 ) 6142 end 6143 ) 6144 end 6145 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6146 end; 6147 6148fun dfn'AMOXOR_W (aq,(rl,(rd,(rs1,rs2)))) = 6149 let 6150 val vAddr = GPR rs1 6151 in 6152 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 6153 then signalAddressException(AMO_Misaligned,vAddr) 6154 else case translateAddr(vAddr,(Data,Write)) of 6155 Option.SOME pAddr => 6156 let 6157 val memv = 6158 BitsN.signExtend 64 6159 (BitsN.bits(31,0) (rawReadData pAddr)) 6160 val data = GPR rs2 6161 in 6162 ( write'GPR(memv,rd) 6163 ; let 6164 val val' = BitsN.??(data,memv) 6165 in 6166 ( rawWriteData(pAddr,(val',4)) 6167 ; ( let 6168 val x = Delta () 6169 in 6170 write'Delta 6171 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6172 end 6173 ; let 6174 val x = Delta () 6175 in 6176 write'Delta 6177 (StateDelta_data1_rupd(x,Option.SOME memv)) 6178 end 6179 ) 6180 ; let 6181 val x = Delta () 6182 in 6183 write'Delta 6184 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6185 end 6186 ; let 6187 val x = Delta () 6188 in 6189 write'Delta 6190 (StateDelta_data2_rupd(x,Option.SOME val')) 6191 end 6192 ; let 6193 val x = Delta () 6194 in 6195 write'Delta 6196 (StateDelta_st_width_rupd 6197 (x,Option.SOME(BitsN.B(0x4,32)))) 6198 end 6199 ) 6200 end 6201 ) 6202 end 6203 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6204 end; 6205 6206fun dfn'AMOXOR_D (aq,(rl,(rd,(rs1,rs2)))) = 6207 let 6208 val vAddr = GPR rs1 6209 in 6210 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 6211 then signalAddressException(AMO_Misaligned,vAddr) 6212 else case translateAddr(vAddr,(Data,Write)) of 6213 Option.SOME pAddr => 6214 let 6215 val memv = rawReadData pAddr 6216 val data = GPR rs2 6217 in 6218 ( write'GPR(memv,rd) 6219 ; let 6220 val val' = BitsN.??(data,memv) 6221 in 6222 ( rawWriteData(pAddr,(val',8)) 6223 ; ( let 6224 val x = Delta () 6225 in 6226 write'Delta 6227 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6228 end 6229 ; let 6230 val x = Delta () 6231 in 6232 write'Delta 6233 (StateDelta_data1_rupd(x,Option.SOME memv)) 6234 end 6235 ) 6236 ; let 6237 val x = Delta () 6238 in 6239 write'Delta 6240 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6241 end 6242 ; let 6243 val x = Delta () 6244 in 6245 write'Delta 6246 (StateDelta_data2_rupd(x,Option.SOME val')) 6247 end 6248 ; let 6249 val x = Delta () 6250 in 6251 write'Delta 6252 (StateDelta_st_width_rupd 6253 (x,Option.SOME(BitsN.B(0x8,32)))) 6254 end 6255 ) 6256 end 6257 ) 6258 end 6259 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6260 end; 6261 6262fun dfn'AMOAND_W (aq,(rl,(rd,(rs1,rs2)))) = 6263 let 6264 val vAddr = GPR rs1 6265 in 6266 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 6267 then signalAddressException(AMO_Misaligned,vAddr) 6268 else case translateAddr(vAddr,(Data,Write)) of 6269 Option.SOME pAddr => 6270 let 6271 val memv = 6272 BitsN.signExtend 64 6273 (BitsN.bits(31,0) (rawReadData pAddr)) 6274 val data = GPR rs2 6275 in 6276 ( write'GPR(memv,rd) 6277 ; let 6278 val val' = BitsN.&&(data,memv) 6279 in 6280 ( rawWriteData(pAddr,(val',4)) 6281 ; ( let 6282 val x = Delta () 6283 in 6284 write'Delta 6285 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6286 end 6287 ; let 6288 val x = Delta () 6289 in 6290 write'Delta 6291 (StateDelta_data1_rupd(x,Option.SOME memv)) 6292 end 6293 ) 6294 ; let 6295 val x = Delta () 6296 in 6297 write'Delta 6298 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6299 end 6300 ; let 6301 val x = Delta () 6302 in 6303 write'Delta 6304 (StateDelta_data2_rupd(x,Option.SOME val')) 6305 end 6306 ; let 6307 val x = Delta () 6308 in 6309 write'Delta 6310 (StateDelta_st_width_rupd 6311 (x,Option.SOME(BitsN.B(0x4,32)))) 6312 end 6313 ) 6314 end 6315 ) 6316 end 6317 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6318 end; 6319 6320fun dfn'AMOAND_D (aq,(rl,(rd,(rs1,rs2)))) = 6321 let 6322 val vAddr = GPR rs1 6323 in 6324 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 6325 then signalAddressException(AMO_Misaligned,vAddr) 6326 else case translateAddr(vAddr,(Data,Write)) of 6327 Option.SOME pAddr => 6328 let 6329 val memv = rawReadData pAddr 6330 val data = GPR rs2 6331 in 6332 ( write'GPR(memv,rd) 6333 ; let 6334 val val' = BitsN.&&(data,memv) 6335 in 6336 ( rawWriteData(pAddr,(val',8)) 6337 ; ( let 6338 val x = Delta () 6339 in 6340 write'Delta 6341 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6342 end 6343 ; let 6344 val x = Delta () 6345 in 6346 write'Delta 6347 (StateDelta_data1_rupd(x,Option.SOME memv)) 6348 end 6349 ) 6350 ; let 6351 val x = Delta () 6352 in 6353 write'Delta 6354 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6355 end 6356 ; let 6357 val x = Delta () 6358 in 6359 write'Delta 6360 (StateDelta_data2_rupd(x,Option.SOME val')) 6361 end 6362 ; let 6363 val x = Delta () 6364 in 6365 write'Delta 6366 (StateDelta_st_width_rupd 6367 (x,Option.SOME(BitsN.B(0x8,32)))) 6368 end 6369 ) 6370 end 6371 ) 6372 end 6373 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6374 end; 6375 6376fun dfn'AMOOR_W (aq,(rl,(rd,(rs1,rs2)))) = 6377 let 6378 val vAddr = GPR rs1 6379 in 6380 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 6381 then signalAddressException(AMO_Misaligned,vAddr) 6382 else case translateAddr(vAddr,(Data,Write)) of 6383 Option.SOME pAddr => 6384 let 6385 val memv = 6386 BitsN.signExtend 64 6387 (BitsN.bits(31,0) (rawReadData pAddr)) 6388 val data = GPR rs2 6389 in 6390 ( write'GPR(memv,rd) 6391 ; let 6392 val val' = BitsN.||(data,memv) 6393 in 6394 ( rawWriteData(pAddr,(val',4)) 6395 ; ( let 6396 val x = Delta () 6397 in 6398 write'Delta 6399 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6400 end 6401 ; let 6402 val x = Delta () 6403 in 6404 write'Delta 6405 (StateDelta_data1_rupd(x,Option.SOME memv)) 6406 end 6407 ) 6408 ; let 6409 val x = Delta () 6410 in 6411 write'Delta 6412 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6413 end 6414 ; let 6415 val x = Delta () 6416 in 6417 write'Delta 6418 (StateDelta_data2_rupd(x,Option.SOME val')) 6419 end 6420 ; let 6421 val x = Delta () 6422 in 6423 write'Delta 6424 (StateDelta_st_width_rupd 6425 (x,Option.SOME(BitsN.B(0x4,32)))) 6426 end 6427 ) 6428 end 6429 ) 6430 end 6431 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6432 end; 6433 6434fun dfn'AMOOR_D (aq,(rl,(rd,(rs1,rs2)))) = 6435 let 6436 val vAddr = GPR rs1 6437 in 6438 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 6439 then signalAddressException(AMO_Misaligned,vAddr) 6440 else case translateAddr(vAddr,(Data,Write)) of 6441 Option.SOME pAddr => 6442 let 6443 val memv = rawReadData pAddr 6444 val data = GPR rs2 6445 in 6446 ( write'GPR(memv,rd) 6447 ; let 6448 val val' = BitsN.||(data,memv) 6449 in 6450 ( rawWriteData(pAddr,(val',8)) 6451 ; ( let 6452 val x = Delta () 6453 in 6454 write'Delta 6455 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6456 end 6457 ; let 6458 val x = Delta () 6459 in 6460 write'Delta 6461 (StateDelta_data1_rupd(x,Option.SOME memv)) 6462 end 6463 ) 6464 ; let 6465 val x = Delta () 6466 in 6467 write'Delta 6468 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6469 end 6470 ; let 6471 val x = Delta () 6472 in 6473 write'Delta 6474 (StateDelta_data2_rupd(x,Option.SOME val')) 6475 end 6476 ; let 6477 val x = Delta () 6478 in 6479 write'Delta 6480 (StateDelta_st_width_rupd 6481 (x,Option.SOME(BitsN.B(0x8,32)))) 6482 end 6483 ) 6484 end 6485 ) 6486 end 6487 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6488 end; 6489 6490fun dfn'AMOMIN_W (aq,(rl,(rd,(rs1,rs2)))) = 6491 let 6492 val vAddr = GPR rs1 6493 in 6494 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 6495 then signalAddressException(AMO_Misaligned,vAddr) 6496 else case translateAddr(vAddr,(Data,Write)) of 6497 Option.SOME pAddr => 6498 let 6499 val memv = 6500 BitsN.signExtend 64 6501 (BitsN.bits(31,0) (rawReadData pAddr)) 6502 val data = GPR rs2 6503 in 6504 ( write'GPR(memv,rd) 6505 ; let 6506 val val' = BitsN.smin(data,memv) 6507 in 6508 ( rawWriteData(pAddr,(val',4)) 6509 ; ( let 6510 val x = Delta () 6511 in 6512 write'Delta 6513 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6514 end 6515 ; let 6516 val x = Delta () 6517 in 6518 write'Delta 6519 (StateDelta_data1_rupd(x,Option.SOME memv)) 6520 end 6521 ) 6522 ; let 6523 val x = Delta () 6524 in 6525 write'Delta 6526 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6527 end 6528 ; let 6529 val x = Delta () 6530 in 6531 write'Delta 6532 (StateDelta_data2_rupd(x,Option.SOME val')) 6533 end 6534 ; let 6535 val x = Delta () 6536 in 6537 write'Delta 6538 (StateDelta_st_width_rupd 6539 (x,Option.SOME(BitsN.B(0x4,32)))) 6540 end 6541 ) 6542 end 6543 ) 6544 end 6545 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6546 end; 6547 6548fun dfn'AMOMIN_D (aq,(rl,(rd,(rs1,rs2)))) = 6549 let 6550 val vAddr = GPR rs1 6551 in 6552 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 6553 then signalAddressException(AMO_Misaligned,vAddr) 6554 else case translateAddr(vAddr,(Data,Write)) of 6555 Option.SOME pAddr => 6556 let 6557 val memv = rawReadData pAddr 6558 val data = GPR rs2 6559 in 6560 ( write'GPR(memv,rd) 6561 ; let 6562 val val' = BitsN.smin(data,memv) 6563 in 6564 ( rawWriteData(pAddr,(val',8)) 6565 ; ( let 6566 val x = Delta () 6567 in 6568 write'Delta 6569 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6570 end 6571 ; let 6572 val x = Delta () 6573 in 6574 write'Delta 6575 (StateDelta_data1_rupd(x,Option.SOME memv)) 6576 end 6577 ) 6578 ; let 6579 val x = Delta () 6580 in 6581 write'Delta 6582 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6583 end 6584 ; let 6585 val x = Delta () 6586 in 6587 write'Delta 6588 (StateDelta_data2_rupd(x,Option.SOME val')) 6589 end 6590 ; let 6591 val x = Delta () 6592 in 6593 write'Delta 6594 (StateDelta_st_width_rupd 6595 (x,Option.SOME(BitsN.B(0x8,32)))) 6596 end 6597 ) 6598 end 6599 ) 6600 end 6601 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6602 end; 6603 6604fun dfn'AMOMAX_W (aq,(rl,(rd,(rs1,rs2)))) = 6605 let 6606 val vAddr = GPR rs1 6607 in 6608 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 6609 then signalAddressException(AMO_Misaligned,vAddr) 6610 else case translateAddr(vAddr,(Data,Write)) of 6611 Option.SOME pAddr => 6612 let 6613 val memv = 6614 BitsN.signExtend 64 6615 (BitsN.bits(31,0) (rawReadData pAddr)) 6616 val data = GPR rs2 6617 in 6618 ( write'GPR(memv,rd) 6619 ; let 6620 val val' = BitsN.smax(data,memv) 6621 in 6622 ( rawWriteData(pAddr,(val',4)) 6623 ; ( let 6624 val x = Delta () 6625 in 6626 write'Delta 6627 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6628 end 6629 ; let 6630 val x = Delta () 6631 in 6632 write'Delta 6633 (StateDelta_data1_rupd(x,Option.SOME memv)) 6634 end 6635 ) 6636 ; let 6637 val x = Delta () 6638 in 6639 write'Delta 6640 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6641 end 6642 ; let 6643 val x = Delta () 6644 in 6645 write'Delta 6646 (StateDelta_data2_rupd(x,Option.SOME val')) 6647 end 6648 ; let 6649 val x = Delta () 6650 in 6651 write'Delta 6652 (StateDelta_st_width_rupd 6653 (x,Option.SOME(BitsN.B(0x4,32)))) 6654 end 6655 ) 6656 end 6657 ) 6658 end 6659 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6660 end; 6661 6662fun dfn'AMOMAX_D (aq,(rl,(rd,(rs1,rs2)))) = 6663 let 6664 val vAddr = GPR rs1 6665 in 6666 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 6667 then signalAddressException(AMO_Misaligned,vAddr) 6668 else case translateAddr(vAddr,(Data,Write)) of 6669 Option.SOME pAddr => 6670 let 6671 val memv = rawReadData pAddr 6672 val data = GPR rs2 6673 in 6674 ( write'GPR(memv,rd) 6675 ; let 6676 val val' = BitsN.smax(data,memv) 6677 in 6678 ( rawWriteData(pAddr,(val',8)) 6679 ; ( let 6680 val x = Delta () 6681 in 6682 write'Delta 6683 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6684 end 6685 ; let 6686 val x = Delta () 6687 in 6688 write'Delta 6689 (StateDelta_data1_rupd(x,Option.SOME memv)) 6690 end 6691 ) 6692 ; let 6693 val x = Delta () 6694 in 6695 write'Delta 6696 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6697 end 6698 ; let 6699 val x = Delta () 6700 in 6701 write'Delta 6702 (StateDelta_data2_rupd(x,Option.SOME val')) 6703 end 6704 ; let 6705 val x = Delta () 6706 in 6707 write'Delta 6708 (StateDelta_st_width_rupd 6709 (x,Option.SOME(BitsN.B(0x8,32)))) 6710 end 6711 ) 6712 end 6713 ) 6714 end 6715 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6716 end; 6717 6718fun dfn'AMOMINU_W (aq,(rl,(rd,(rs1,rs2)))) = 6719 let 6720 val vAddr = GPR rs1 6721 in 6722 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 6723 then signalAddressException(AMO_Misaligned,vAddr) 6724 else case translateAddr(vAddr,(Data,Write)) of 6725 Option.SOME pAddr => 6726 let 6727 val memv = 6728 BitsN.signExtend 64 6729 (BitsN.bits(31,0) (rawReadData pAddr)) 6730 val data = GPR rs2 6731 in 6732 ( write'GPR(memv,rd) 6733 ; let 6734 val val' = BitsN.min(data,memv) 6735 in 6736 ( rawWriteData(pAddr,(val',4)) 6737 ; ( let 6738 val x = Delta () 6739 in 6740 write'Delta 6741 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6742 end 6743 ; let 6744 val x = Delta () 6745 in 6746 write'Delta 6747 (StateDelta_data1_rupd(x,Option.SOME memv)) 6748 end 6749 ) 6750 ; let 6751 val x = Delta () 6752 in 6753 write'Delta 6754 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6755 end 6756 ; let 6757 val x = Delta () 6758 in 6759 write'Delta 6760 (StateDelta_data2_rupd(x,Option.SOME val')) 6761 end 6762 ; let 6763 val x = Delta () 6764 in 6765 write'Delta 6766 (StateDelta_st_width_rupd 6767 (x,Option.SOME(BitsN.B(0x4,32)))) 6768 end 6769 ) 6770 end 6771 ) 6772 end 6773 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6774 end; 6775 6776fun dfn'AMOMINU_D (aq,(rl,(rd,(rs1,rs2)))) = 6777 let 6778 val vAddr = GPR rs1 6779 in 6780 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 6781 then signalAddressException(AMO_Misaligned,vAddr) 6782 else case translateAddr(vAddr,(Data,Write)) of 6783 Option.SOME pAddr => 6784 let 6785 val memv = rawReadData pAddr 6786 val data = GPR rs2 6787 in 6788 ( write'GPR(memv,rd) 6789 ; let 6790 val val' = BitsN.min(data,memv) 6791 in 6792 ( rawWriteData(pAddr,(val',8)) 6793 ; ( let 6794 val x = Delta () 6795 in 6796 write'Delta 6797 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6798 end 6799 ; let 6800 val x = Delta () 6801 in 6802 write'Delta 6803 (StateDelta_data1_rupd(x,Option.SOME memv)) 6804 end 6805 ) 6806 ; let 6807 val x = Delta () 6808 in 6809 write'Delta 6810 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6811 end 6812 ; let 6813 val x = Delta () 6814 in 6815 write'Delta 6816 (StateDelta_data2_rupd(x,Option.SOME val')) 6817 end 6818 ; let 6819 val x = Delta () 6820 in 6821 write'Delta 6822 (StateDelta_st_width_rupd 6823 (x,Option.SOME(BitsN.B(0x8,32)))) 6824 end 6825 ) 6826 end 6827 ) 6828 end 6829 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6830 end; 6831 6832fun dfn'AMOMAXU_W (aq,(rl,(rd,(rs1,rs2)))) = 6833 let 6834 val vAddr = GPR rs1 6835 in 6836 if not((BitsN.bits(1,0) vAddr) = (BitsN.B(0x0,2))) 6837 then signalAddressException(AMO_Misaligned,vAddr) 6838 else case translateAddr(vAddr,(Data,Write)) of 6839 Option.SOME pAddr => 6840 let 6841 val memv = 6842 BitsN.signExtend 64 6843 (BitsN.bits(31,0) (rawReadData pAddr)) 6844 val data = GPR rs2 6845 in 6846 ( write'GPR(memv,rd) 6847 ; let 6848 val val' = BitsN.max(data,memv) 6849 in 6850 ( rawWriteData(pAddr,(val',4)) 6851 ; ( let 6852 val x = Delta () 6853 in 6854 write'Delta 6855 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6856 end 6857 ; let 6858 val x = Delta () 6859 in 6860 write'Delta 6861 (StateDelta_data1_rupd(x,Option.SOME memv)) 6862 end 6863 ) 6864 ; let 6865 val x = Delta () 6866 in 6867 write'Delta 6868 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6869 end 6870 ; let 6871 val x = Delta () 6872 in 6873 write'Delta 6874 (StateDelta_data2_rupd(x,Option.SOME val')) 6875 end 6876 ; let 6877 val x = Delta () 6878 in 6879 write'Delta 6880 (StateDelta_st_width_rupd 6881 (x,Option.SOME(BitsN.B(0x4,32)))) 6882 end 6883 ) 6884 end 6885 ) 6886 end 6887 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6888 end; 6889 6890fun dfn'AMOMAXU_D (aq,(rl,(rd,(rs1,rs2)))) = 6891 let 6892 val vAddr = GPR rs1 6893 in 6894 if not((BitsN.bits(2,0) vAddr) = (BitsN.B(0x0,3))) 6895 then signalAddressException(AMO_Misaligned,vAddr) 6896 else case translateAddr(vAddr,(Data,Write)) of 6897 Option.SOME pAddr => 6898 let 6899 val memv = rawReadData pAddr 6900 val data = GPR rs2 6901 in 6902 ( write'GPR(memv,rd) 6903 ; let 6904 val val' = BitsN.max(data,memv) 6905 in 6906 ( rawWriteData(pAddr,(val',8)) 6907 ; ( let 6908 val x = Delta () 6909 in 6910 write'Delta 6911 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6912 end 6913 ; let 6914 val x = Delta () 6915 in 6916 write'Delta 6917 (StateDelta_data1_rupd(x,Option.SOME memv)) 6918 end 6919 ) 6920 ; let 6921 val x = Delta () 6922 in 6923 write'Delta 6924 (StateDelta_addr_rupd(x,Option.SOME vAddr)) 6925 end 6926 ; let 6927 val x = Delta () 6928 in 6929 write'Delta 6930 (StateDelta_data2_rupd(x,Option.SOME val')) 6931 end 6932 ; let 6933 val x = Delta () 6934 in 6935 write'Delta 6936 (StateDelta_st_width_rupd 6937 (x,Option.SOME(BitsN.B(0x8,32)))) 6938 end 6939 ) 6940 end 6941 ) 6942 end 6943 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 6944 end; 6945 6946fun dfn'FLW (rd,(rs1,offs)) = 6947 let 6948 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 6949 in 6950 case translateAddr(vAddr,(Data,Read)) of 6951 Option.SOME pAddr => 6952 let 6953 val val' = BitsN.bits(31,0) (rawReadData pAddr) 6954 in 6955 ( write'FPRS(val',rd) 6956 ; let 6957 val x = Delta () 6958 in 6959 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 6960 end 6961 ; let 6962 val x = Delta () 6963 in 6964 write'Delta 6965 (StateDelta_data1_rupd 6966 (x,Option.SOME(BitsN.zeroExtend 64 val'))) 6967 end 6968 ) 6969 end 6970 | NONE => signalAddressException(Load_Fault,vAddr) 6971 end; 6972 6973fun dfn'FSW (rs1,(rs2,offs)) = 6974 let 6975 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 6976 in 6977 case translateAddr(vAddr,(Data,Write)) of 6978 Option.SOME pAddr => 6979 let 6980 val data = FPRS rs2 6981 in 6982 ( rawWriteData(pAddr,(BitsN.zeroExtend 64 data,4)) 6983 ; let 6984 val x = Delta () 6985 in 6986 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 6987 end 6988 ; let 6989 val x = Delta () 6990 in 6991 write'Delta 6992 (StateDelta_data2_rupd 6993 (x,Option.SOME(BitsN.zeroExtend 64 data))) 6994 end 6995 ; let 6996 val x = Delta () 6997 in 6998 write'Delta 6999 (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x4,32)))) 7000 end 7001 ) 7002 end 7003 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 7004 end; 7005 7006fun dfn'FADD_S (rd,(rs1,(rs2,fprnd))) = 7007 case round fprnd of 7008 Option.SOME r => 7009 writeFPRS(rd,(L3.snd o FP32.add) (r,(FPRS rs1,FPRS rs2))) 7010 | NONE => signalException Illegal_Instr; 7011 7012fun dfn'FSUB_S (rd,(rs1,(rs2,fprnd))) = 7013 case round fprnd of 7014 Option.SOME r => 7015 writeFPRS(rd,(L3.snd o FP32.sub) (r,(FPRS rs1,FPRS rs2))) 7016 | NONE => signalException Illegal_Instr; 7017 7018fun dfn'FMUL_S (rd,(rs1,(rs2,fprnd))) = 7019 case round fprnd of 7020 Option.SOME r => 7021 writeFPRS(rd,(L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2))) 7022 | NONE => signalException Illegal_Instr; 7023 7024fun dfn'FDIV_S (rd,(rs1,(rs2,fprnd))) = 7025 case round fprnd of 7026 Option.SOME r => 7027 writeFPRS(rd,(L3.snd o FP32.div) (r,(FPRS rs1,FPRS rs2))) 7028 | NONE => signalException Illegal_Instr; 7029 7030fun dfn'FSQRT_S (rd,(rs,fprnd)) = 7031 case round fprnd of 7032 Option.SOME r => writeFPRS(rd,(L3.snd o FP32.sqrt) (r,FPRS rs)) 7033 | NONE => signalException Illegal_Instr; 7034 7035fun dfn'FMIN_S (rd,(rs1,rs2)) = 7036 let 7037 val f1 = FPRS rs1 7038 val f2 = FPRS rs2 7039 val res = 7040 case FP32.compare(f1,f2) of 7041 IEEEReal.LESS => f1 7042 | IEEEReal.EQUAL => f1 7043 | IEEEReal.GREATER => f2 7044 | IEEEReal.UNORDERED => 7045 if ((FP32_IsSignalingNan f1) orelse (FP32_IsSignalingNan f2)) orelse 7046 ((f1 = RV32_CanonicalNan) andalso (f2 = RV32_CanonicalNan)) 7047 then RV32_CanonicalNan 7048 else if f1 = RV32_CanonicalNan then f2 else f1 7049 in 7050 writeFPRS(rd,res) 7051 end; 7052 7053fun dfn'FMAX_S (rd,(rs1,rs2)) = 7054 let 7055 val f1 = FPRS rs1 7056 val f2 = FPRS rs2 7057 val res = 7058 case FP32.compare(f1,f2) of 7059 IEEEReal.LESS => f2 7060 | IEEEReal.EQUAL => f2 7061 | IEEEReal.GREATER => f1 7062 | IEEEReal.UNORDERED => 7063 if ((FP32_IsSignalingNan f1) orelse (FP32_IsSignalingNan f2)) orelse 7064 ((f1 = RV32_CanonicalNan) andalso (f2 = RV32_CanonicalNan)) 7065 then RV32_CanonicalNan 7066 else if f1 = RV32_CanonicalNan then f2 else f1 7067 in 7068 writeFPRS(rd,res) 7069 end; 7070 7071fun dfn'FMADD_S (rd,(rs1,(rs2,(rs3,fprnd)))) = 7072 case round fprnd of 7073 Option.SOME r => 7074 writeFPRS 7075 (rd, 7076 (L3.snd o FP32.add) 7077 (r,((L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2)),FPRS rs3))) 7078 | NONE => signalException Illegal_Instr; 7079 7080fun dfn'FMSUB_S (rd,(rs1,(rs2,(rs3,fprnd)))) = 7081 case round fprnd of 7082 Option.SOME r => 7083 writeFPRS 7084 (rd, 7085 (L3.snd o FP32.sub) 7086 (r,((L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2)),FPRS rs3))) 7087 | NONE => signalException Illegal_Instr; 7088 7089fun dfn'FNMADD_S (rd,(rs1,(rs2,(rs3,fprnd)))) = 7090 case round fprnd of 7091 Option.SOME r => 7092 writeFPRS 7093 (rd, 7094 FP32.neg 7095 ((L3.snd o FP32.add) 7096 (r,((L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2)),FPRS rs3)))) 7097 | NONE => signalException Illegal_Instr; 7098 7099fun dfn'FNMSUB_S (rd,(rs1,(rs2,(rs3,fprnd)))) = 7100 case round fprnd of 7101 Option.SOME r => 7102 writeFPRS 7103 (rd, 7104 FP32.neg 7105 ((L3.snd o FP32.sub) 7106 (r,((L3.snd o FP32.mul) (r,(FPRS rs1,FPRS rs2)),FPRS rs3)))) 7107 | NONE => signalException Illegal_Instr; 7108 7109fun dfn'FCVT_S_W (rd,(rs,fprnd)) = 7110 case round fprnd of 7111 Option.SOME r => 7112 writeFPRS 7113 (rd,FP32.fromInt(r,BitsN.toInt(BitsN.bits(31,0) (GPR rs)))) 7114 | NONE => signalException Illegal_Instr; 7115 7116fun dfn'FCVT_S_WU (rd,(rs,fprnd)) = 7117 case round fprnd of 7118 Option.SOME r => 7119 writeFPRS 7120 (rd, 7121 FP32.fromInt 7122 (r, 7123 BitsN.toInt 7124 (BitsN.@@(BitsN.B(0x0,1),BitsN.bits(31,0) (GPR rs))))) 7125 | NONE => signalException Illegal_Instr; 7126 7127fun dfn'FCVT_W_S (rd,(rs,fprnd)) = 7128 case round fprnd of 7129 Option.SOME r => 7130 let 7131 val inp = FPRS rs 7132 val val' = Option.valOf(FP32.toInt(r,inp)) 7133 val res = 7134 if (FP32.isNan inp) orelse (inp = FP32.posInf) 7135 then BitsN.fromNat(Nat.-(Nat.pow(2,31),1),64) 7136 else if inp = FP32.negInf 7137 then BitsN.neg(BitsN.fromNat(Nat.pow(2,31),64)) 7138 else if IntInf.>(val',IntInf.-(IntInf.pow(2,31),1)) 7139 then BitsN.fromNat(Nat.-(Nat.pow(2,31),1),64) 7140 else if IntInf.<(val',IntInf.~(IntInf.pow(2,31))) 7141 then BitsN.neg(BitsN.fromNat(Nat.pow(2,31),64)) 7142 else BitsN.fromInt(val',64) 7143 in 7144 ( write'GPR(res,rd) 7145 ; let 7146 val x = Delta () 7147 in 7148 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7149 end 7150 ) 7151 end 7152 | NONE => signalException Illegal_Instr; 7153 7154fun dfn'FCVT_WU_S (rd,(rs,fprnd)) = 7155 case round fprnd of 7156 Option.SOME r => 7157 let 7158 val inp = FPRS rs 7159 val val' = Option.valOf(FP32.toInt(r,inp)) 7160 val res = 7161 if (FP32.isNan inp) orelse (inp = FP32.posInf) 7162 then BitsN.fromNat(Nat.-(Nat.pow(2,32),1),64) 7163 else if inp = FP32.negInf 7164 then BitsN.B(0x0,64) 7165 else if IntInf.>(val',IntInf.-(IntInf.pow(2,32),1)) 7166 then BitsN.fromNat(Nat.-(Nat.pow(2,32),1),64) 7167 else if IntInf.<(val',0) 7168 then BitsN.B(0x0,64) 7169 else BitsN.fromInt(val',64) 7170 in 7171 ( write'GPR(res,rd) 7172 ; let 7173 val x = Delta () 7174 in 7175 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7176 end 7177 ) 7178 end 7179 | NONE => signalException Illegal_Instr; 7180 7181fun dfn'FCVT_S_L (rd,(rs,fprnd)) = 7182 case round fprnd of 7183 Option.SOME r => writeFPRS(rd,FP32.fromInt(r,BitsN.toInt(GPR rs))) 7184 | NONE => signalException Illegal_Instr; 7185 7186fun dfn'FCVT_S_LU (rd,(rs,fprnd)) = 7187 case round fprnd of 7188 Option.SOME r => 7189 writeFPRS 7190 (rd,FP32.fromInt(r,BitsN.toInt(BitsN.@@(BitsN.B(0x0,1),GPR rs)))) 7191 | NONE => signalException Illegal_Instr; 7192 7193fun dfn'FCVT_L_S (rd,(rs,fprnd)) = 7194 case round fprnd of 7195 Option.SOME r => 7196 let 7197 val inp = FPRS rs 7198 val val' = Option.valOf(FP32.toInt(r,inp)) 7199 val res = 7200 if (FP32.isNan inp) orelse (inp = FP32.posInf) 7201 then BitsN.fromNat(Nat.-(Nat.pow(2,63),1),64) 7202 else if inp = FP32.negInf 7203 then BitsN.neg(BitsN.fromNat(Nat.pow(2,63),64)) 7204 else if IntInf.>(val',IntInf.-(IntInf.pow(2,63),1)) 7205 then BitsN.fromNat(Nat.-(Nat.pow(2,63),1),64) 7206 else if IntInf.<(val',IntInf.~(IntInf.pow(2,63))) 7207 then BitsN.neg(BitsN.fromNat(Nat.pow(2,63),64)) 7208 else BitsN.fromInt(val',64) 7209 in 7210 ( write'GPR(res,rd) 7211 ; let 7212 val x = Delta () 7213 in 7214 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7215 end 7216 ) 7217 end 7218 | NONE => signalException Illegal_Instr; 7219 7220fun dfn'FCVT_LU_S (rd,(rs,fprnd)) = 7221 case round fprnd of 7222 Option.SOME r => 7223 let 7224 val inp = FPRS rs 7225 val val' = Option.valOf(FP32.toInt(r,inp)) 7226 val res = 7227 if (FP32.isNan inp) orelse (inp = FP32.posInf) 7228 then BitsN.fromNat(Nat.-(Nat.pow(2,64),1),64) 7229 else if inp = FP32.negInf 7230 then BitsN.B(0x0,64) 7231 else if IntInf.>(val',IntInf.-(IntInf.pow(2,64),1)) 7232 then BitsN.fromNat(Nat.-(Nat.pow(2,64),1),64) 7233 else if IntInf.<(val',0) 7234 then BitsN.B(0x0,64) 7235 else BitsN.fromInt(val',64) 7236 in 7237 ( write'GPR(res,rd) 7238 ; let 7239 val x = Delta () 7240 in 7241 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7242 end 7243 ) 7244 end 7245 | NONE => signalException Illegal_Instr; 7246 7247fun dfn'FSGNJ_S (rd,(rs1,rs2)) = 7248 let 7249 val f1 = FPRS rs1 7250 val f2 = FPRS rs2 7251 in 7252 writeFPRS 7253 (rd,BitsN.@@(BitsN.fromBit(FP32_Sign f2),BitsN.bits(30,0) f1)) 7254 end; 7255 7256fun dfn'FSGNJN_S (rd,(rs1,rs2)) = 7257 let 7258 val f1 = FPRS rs1 7259 val f2 = FPRS rs2 7260 in 7261 writeFPRS 7262 (rd,BitsN.@@(BitsN.fromBit(not(FP32_Sign f2)),BitsN.bits(30,0) f1)) 7263 end; 7264 7265fun dfn'FSGNJX_S (rd,(rs1,rs2)) = 7266 let 7267 val f1 = FPRS rs1 7268 val f2 = FPRS rs2 7269 in 7270 writeFPRS 7271 (rd, 7272 BitsN.@@ 7273 (BitsN.?? 7274 (BitsN.fromBit(FP32_Sign f2),BitsN.fromBit(FP32_Sign f1)), 7275 BitsN.bits(30,0) f1)) 7276 end; 7277 7278fun dfn'FMV_X_S (rd,rs) = write'GPR(BitsN.signExtend 64 (FPRS rs),rd); 7279 7280fun dfn'FMV_S_X (rd,rs) = writeFPRS(rd,BitsN.bits(31,0) (GPR rs)); 7281 7282fun dfn'FEQ_S (rd,(rs1,rs2)) = 7283 let 7284 val f1 = FPRS rs1 7285 val f2 = FPRS rs2 7286 in 7287 if (FP32_IsSignalingNan f1) orelse (FP32_IsSignalingNan f2) 7288 then ( ( write'GPR(BitsN.B(0x0,64),rd) 7289 ; let 7290 val x = Delta () 7291 in 7292 write'Delta 7293 (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) 7294 end 7295 ) 7296 ; setFP_Invalid () 7297 ) 7298 else let 7299 val res = 7300 case FP32.compare(f1,f2) of 7301 IEEEReal.LESS => BitsN.B(0x0,64) 7302 | IEEEReal.EQUAL => BitsN.B(0x1,64) 7303 | IEEEReal.GREATER => BitsN.B(0x0,64) 7304 | IEEEReal.UNORDERED => BitsN.B(0x0,64) 7305 in 7306 ( write'GPR(res,rd) 7307 ; let 7308 val x = Delta () 7309 in 7310 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7311 end 7312 ) 7313 end 7314 end; 7315 7316fun dfn'FLT_S (rd,(rs1,rs2)) = 7317 let 7318 val f1 = FPRS rs1 7319 val f2 = FPRS rs2 7320 in 7321 if (FP32.isNan f1) orelse (FP32.isNan f2) 7322 then ( ( write'GPR(BitsN.B(0x0,64),rd) 7323 ; let 7324 val x = Delta () 7325 in 7326 write'Delta 7327 (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) 7328 end 7329 ) 7330 ; setFP_Invalid () 7331 ) 7332 else let 7333 val res = 7334 case FP32.compare(f1,f2) of 7335 IEEEReal.LESS => BitsN.B(0x1,64) 7336 | IEEEReal.EQUAL => BitsN.B(0x0,64) 7337 | IEEEReal.GREATER => BitsN.B(0x0,64) 7338 | IEEEReal.UNORDERED => BitsN.B(0x0,64) 7339 in 7340 ( write'GPR(res,rd) 7341 ; let 7342 val x = Delta () 7343 in 7344 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7345 end 7346 ) 7347 end 7348 end; 7349 7350fun dfn'FLE_S (rd,(rs1,rs2)) = 7351 let 7352 val f1 = FPRS rs1 7353 val f2 = FPRS rs2 7354 in 7355 if (FP32.isNan f1) orelse (FP32.isNan f2) 7356 then ( ( write'GPR(BitsN.B(0x0,64),rd) 7357 ; let 7358 val x = Delta () 7359 in 7360 write'Delta 7361 (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) 7362 end 7363 ) 7364 ; setFP_Invalid () 7365 ) 7366 else let 7367 val res = 7368 case FP32.compare(f1,f2) of 7369 IEEEReal.LESS => BitsN.B(0x1,64) 7370 | IEEEReal.EQUAL => BitsN.B(0x1,64) 7371 | IEEEReal.GREATER => BitsN.B(0x0,64) 7372 | IEEEReal.UNORDERED => BitsN.B(0x0,64) 7373 in 7374 ( write'GPR(res,rd) 7375 ; let 7376 val x = Delta () 7377 in 7378 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7379 end 7380 ) 7381 end 7382 end; 7383 7384fun dfn'FCLASS_S (rd,rs) = 7385 let 7386 val ret = ref (BitsN.B(0x0,10)) 7387 in 7388 let 7389 val val' = FPRS rs 7390 in 7391 ( ret := 7392 (BitsN.bitFieldInsert(0,0) 7393 ((!ret),BitsN.fromBit(val' = FP32.negInf))) 7394 ; ret := 7395 (BitsN.bitFieldInsert(1,1) 7396 ((!ret), 7397 BitsN.fromBit((FP32_Sign val') andalso (FP32.isNormal val')))) 7398 ; ret := 7399 (BitsN.bitFieldInsert(2,2) 7400 ((!ret), 7401 BitsN.fromBit 7402 ((FP32_Sign val') andalso (FP32.isSubnormal val')))) 7403 ; ret := 7404 (BitsN.bitFieldInsert(3,3) 7405 ((!ret),BitsN.fromBit(val' = FP32.negZero))) 7406 ; ret := 7407 (BitsN.bitFieldInsert(4,4) 7408 ((!ret),BitsN.fromBit(val' = FP32.posZero))) 7409 ; ret := 7410 (BitsN.bitFieldInsert(5,5) 7411 ((!ret), 7412 BitsN.fromBit 7413 ((not(FP32_Sign val')) andalso (FP32.isSubnormal val')))) 7414 ; ret := 7415 (BitsN.bitFieldInsert(6,6) 7416 ((!ret), 7417 BitsN.fromBit 7418 ((not(FP32_Sign val')) andalso (FP32.isNormal val')))) 7419 ; ret := 7420 (BitsN.bitFieldInsert(7,7) 7421 ((!ret),BitsN.fromBit(val' = FP32.posInf))) 7422 ; ret := 7423 (BitsN.bitFieldInsert(8,8) 7424 ((!ret),BitsN.fromBit(FP32_IsSignalingNan val'))) 7425 ; ret := 7426 (BitsN.bitFieldInsert(9,9) 7427 ((!ret),BitsN.fromBit(val' = RV32_CanonicalNan))) 7428 ; write'GPR(BitsN.zeroExtend 64 (!ret),rd) 7429 ; let 7430 val x = Delta () 7431 in 7432 write'Delta 7433 (StateDelta_data1_rupd 7434 (x,Option.SOME(BitsN.zeroExtend 64 (!ret)))) 7435 end 7436 ) 7437 end 7438 end; 7439 7440fun dfn'FLD (rd,(rs1,offs)) = 7441 let 7442 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 7443 in 7444 case translateAddr(vAddr,(Data,Read)) of 7445 Option.SOME pAddr => 7446 let 7447 val val' = rawReadData pAddr 7448 in 7449 ( write'FPRD(val',rd) 7450 ; let 7451 val x = Delta () 7452 in 7453 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 7454 end 7455 ; let 7456 val x = Delta () 7457 in 7458 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 7459 end 7460 ) 7461 end 7462 | NONE => signalAddressException(Load_Fault,vAddr) 7463 end; 7464 7465fun dfn'FSD (rs1,(rs2,offs)) = 7466 let 7467 val vAddr = BitsN.+(GPR rs1,BitsN.signExtend 64 offs) 7468 in 7469 case translateAddr(vAddr,(Data,Write)) of 7470 Option.SOME pAddr => 7471 let 7472 val data = FPRD rs2 7473 in 7474 ( rawWriteData(pAddr,(data,8)) 7475 ; let 7476 val x = Delta () 7477 in 7478 write'Delta(StateDelta_addr_rupd(x,Option.SOME vAddr)) 7479 end 7480 ; let 7481 val x = Delta () 7482 in 7483 write'Delta(StateDelta_data2_rupd(x,Option.SOME data)) 7484 end 7485 ; let 7486 val x = Delta () 7487 in 7488 write'Delta 7489 (StateDelta_st_width_rupd(x,Option.SOME(BitsN.B(0x8,32)))) 7490 end 7491 ) 7492 end 7493 | NONE => signalAddressException(Store_AMO_Fault,vAddr) 7494 end; 7495 7496fun dfn'FADD_D (rd,(rs1,(rs2,fprnd))) = 7497 case round fprnd of 7498 Option.SOME r => 7499 writeFPRD(rd,(L3.snd o FP64.add) (r,(FPRD rs1,FPRD rs2))) 7500 | NONE => signalException Illegal_Instr; 7501 7502fun dfn'FSUB_D (rd,(rs1,(rs2,fprnd))) = 7503 case round fprnd of 7504 Option.SOME r => 7505 writeFPRD(rd,(L3.snd o FP64.sub) (r,(FPRD rs1,FPRD rs2))) 7506 | NONE => signalException Illegal_Instr; 7507 7508fun dfn'FMUL_D (rd,(rs1,(rs2,fprnd))) = 7509 case round fprnd of 7510 Option.SOME r => 7511 writeFPRD(rd,(L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2))) 7512 | NONE => signalException Illegal_Instr; 7513 7514fun dfn'FDIV_D (rd,(rs1,(rs2,fprnd))) = 7515 case round fprnd of 7516 Option.SOME r => 7517 writeFPRD(rd,(L3.snd o FP64.div) (r,(FPRD rs1,FPRD rs2))) 7518 | NONE => signalException Illegal_Instr; 7519 7520fun dfn'FSQRT_D (rd,(rs,fprnd)) = 7521 case round fprnd of 7522 Option.SOME r => writeFPRD(rd,(L3.snd o FP64.sqrt) (r,FPRD rs)) 7523 | NONE => signalException Illegal_Instr; 7524 7525fun dfn'FMIN_D (rd,(rs1,rs2)) = 7526 let 7527 val f1 = FPRD rs1 7528 val f2 = FPRD rs2 7529 val res = 7530 case FP64.compare(f1,f2) of 7531 IEEEReal.LESS => f1 7532 | IEEEReal.EQUAL => f1 7533 | IEEEReal.GREATER => f2 7534 | IEEEReal.UNORDERED => 7535 if ((FP64_IsSignalingNan f1) orelse (FP64_IsSignalingNan f2)) orelse 7536 ((f1 = RV64_CanonicalNan) andalso (f2 = RV64_CanonicalNan)) 7537 then RV64_CanonicalNan 7538 else if f1 = RV64_CanonicalNan then f2 else f1 7539 in 7540 writeFPRD(rd,res) 7541 end; 7542 7543fun dfn'FMAX_D (rd,(rs1,rs2)) = 7544 let 7545 val f1 = FPRD rs1 7546 val f2 = FPRD rs2 7547 val res = 7548 case FP64.compare(f1,f2) of 7549 IEEEReal.LESS => f2 7550 | IEEEReal.EQUAL => f2 7551 | IEEEReal.GREATER => f1 7552 | IEEEReal.UNORDERED => 7553 if ((FP64_IsSignalingNan f1) orelse (FP64_IsSignalingNan f2)) orelse 7554 ((f1 = RV64_CanonicalNan) andalso (f2 = RV64_CanonicalNan)) 7555 then RV64_CanonicalNan 7556 else if f1 = RV64_CanonicalNan then f2 else f1 7557 in 7558 writeFPRD(rd,res) 7559 end; 7560 7561fun dfn'FMADD_D (rd,(rs1,(rs2,(rs3,fprnd)))) = 7562 case round fprnd of 7563 Option.SOME r => 7564 writeFPRD 7565 (rd, 7566 (L3.snd o FP64.add) 7567 (r,((L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2)),FPRD rs3))) 7568 | NONE => signalException Illegal_Instr; 7569 7570fun dfn'FMSUB_D (rd,(rs1,(rs2,(rs3,fprnd)))) = 7571 case round fprnd of 7572 Option.SOME r => 7573 writeFPRD 7574 (rd, 7575 (L3.snd o FP64.sub) 7576 (r,((L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2)),FPRD rs3))) 7577 | NONE => signalException Illegal_Instr; 7578 7579fun dfn'FNMADD_D (rd,(rs1,(rs2,(rs3,fprnd)))) = 7580 case round fprnd of 7581 Option.SOME r => 7582 writeFPRD 7583 (rd, 7584 FP64.neg 7585 ((L3.snd o FP64.add) 7586 (r,((L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2)),FPRD rs3)))) 7587 | NONE => signalException Illegal_Instr; 7588 7589fun dfn'FNMSUB_D (rd,(rs1,(rs2,(rs3,fprnd)))) = 7590 case round fprnd of 7591 Option.SOME r => 7592 writeFPRD 7593 (rd, 7594 FP64.neg 7595 ((L3.snd o FP64.sub) 7596 (r,((L3.snd o FP64.mul) (r,(FPRD rs1,FPRD rs2)),FPRD rs3)))) 7597 | NONE => signalException Illegal_Instr; 7598 7599fun dfn'FCVT_D_W (rd,(rs,fprnd)) = 7600 case round fprnd of 7601 Option.SOME r => 7602 writeFPRD 7603 (rd,FP64.fromInt(r,BitsN.toInt(BitsN.bits(31,0) (GPR rs)))) 7604 | NONE => signalException Illegal_Instr; 7605 7606fun dfn'FCVT_D_WU (rd,(rs,fprnd)) = 7607 case round fprnd of 7608 Option.SOME r => 7609 writeFPRD 7610 (rd, 7611 FP64.fromInt 7612 (r, 7613 BitsN.toInt 7614 (BitsN.@@(BitsN.B(0x0,1),BitsN.bits(31,0) (GPR rs))))) 7615 | NONE => signalException Illegal_Instr; 7616 7617fun dfn'FCVT_W_D (rd,(rs,fprnd)) = 7618 case round fprnd of 7619 Option.SOME r => 7620 let 7621 val inp = FPRD rs 7622 val val' = Option.valOf(FP64.toInt(r,inp)) 7623 val res = 7624 if (FP64.isNan inp) orelse (inp = FP64.posInf) 7625 then BitsN.fromNat(Nat.-(Nat.pow(2,31),1),64) 7626 else if inp = FP64.negInf 7627 then BitsN.neg(BitsN.fromNat(Nat.pow(2,31),64)) 7628 else if IntInf.>(val',IntInf.-(IntInf.pow(2,31),1)) 7629 then BitsN.fromNat(Nat.-(Nat.pow(2,31),1),64) 7630 else if IntInf.<(val',IntInf.~(IntInf.pow(2,31))) 7631 then BitsN.neg(BitsN.fromNat(Nat.pow(2,31),64)) 7632 else BitsN.fromInt(val',64) 7633 in 7634 ( write'GPR(res,rd) 7635 ; let 7636 val x = Delta () 7637 in 7638 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7639 end 7640 ) 7641 end 7642 | NONE => signalException Illegal_Instr; 7643 7644fun dfn'FCVT_WU_D (rd,(rs,fprnd)) = 7645 case round fprnd of 7646 Option.SOME r => 7647 let 7648 val inp = FPRD rs 7649 val val' = Option.valOf(FP64.toInt(r,inp)) 7650 val res = 7651 if (FP64.isNan inp) orelse (inp = FP64.posInf) 7652 then BitsN.fromNat(Nat.-(Nat.pow(2,32),1),64) 7653 else if inp = FP64.negInf 7654 then BitsN.B(0x0,64) 7655 else if IntInf.>(val',IntInf.-(IntInf.pow(2,32),1)) 7656 then BitsN.fromNat(Nat.-(Nat.pow(2,32),1),64) 7657 else if IntInf.<(val',0) 7658 then BitsN.B(0x0,64) 7659 else BitsN.fromInt(val',64) 7660 in 7661 ( write'GPR(res,rd) 7662 ; let 7663 val x = Delta () 7664 in 7665 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7666 end 7667 ) 7668 end 7669 | NONE => signalException Illegal_Instr; 7670 7671fun dfn'FCVT_D_L (rd,(rs,fprnd)) = 7672 case round fprnd of 7673 Option.SOME r => writeFPRD(rd,FP64.fromInt(r,BitsN.toInt(GPR rs))) 7674 | NONE => signalException Illegal_Instr; 7675 7676fun dfn'FCVT_D_LU (rd,(rs,fprnd)) = 7677 case round fprnd of 7678 Option.SOME r => 7679 writeFPRD 7680 (rd,FP64.fromInt(r,BitsN.toInt(BitsN.@@(BitsN.B(0x0,1),GPR rs)))) 7681 | NONE => signalException Illegal_Instr; 7682 7683fun dfn'FCVT_L_D (rd,(rs,fprnd)) = 7684 case round fprnd of 7685 Option.SOME r => 7686 let 7687 val inp = FPRD rs 7688 val val' = Option.valOf(FP64.toInt(r,inp)) 7689 val res = 7690 if (FP64.isNan inp) orelse (inp = FP64.posInf) 7691 then BitsN.fromNat(Nat.-(Nat.pow(2,63),1),64) 7692 else if inp = FP64.negInf 7693 then BitsN.neg(BitsN.fromNat(Nat.pow(2,63),64)) 7694 else if IntInf.>(val',IntInf.-(IntInf.pow(2,63),1)) 7695 then BitsN.fromNat(Nat.-(Nat.pow(2,63),1),64) 7696 else if IntInf.<(val',IntInf.~(IntInf.pow(2,63))) 7697 then BitsN.neg(BitsN.fromNat(Nat.pow(2,63),64)) 7698 else BitsN.fromInt(val',64) 7699 in 7700 ( write'GPR(res,rd) 7701 ; let 7702 val x = Delta () 7703 in 7704 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7705 end 7706 ) 7707 end 7708 | NONE => signalException Illegal_Instr; 7709 7710fun dfn'FCVT_LU_D (rd,(rs,fprnd)) = 7711 case round fprnd of 7712 Option.SOME r => 7713 let 7714 val inp = FPRD rs 7715 val val' = Option.valOf(FP64.toInt(r,inp)) 7716 val res = 7717 if (FP64.isNan inp) orelse (inp = FP64.posInf) 7718 then BitsN.fromNat(Nat.-(Nat.pow(2,64),1),64) 7719 else if inp = FP64.negInf 7720 then BitsN.B(0x0,64) 7721 else if IntInf.>(val',IntInf.-(IntInf.pow(2,64),1)) 7722 then BitsN.fromNat(Nat.-(Nat.pow(2,64),1),64) 7723 else if IntInf.<(val',0) 7724 then BitsN.B(0x0,64) 7725 else BitsN.fromInt(val',64) 7726 in 7727 ( write'GPR(res,rd) 7728 ; let 7729 val x = Delta () 7730 in 7731 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7732 end 7733 ) 7734 end 7735 | NONE => signalException Illegal_Instr; 7736 7737fun dfn'FCVT_S_D (rd,(rs,fprnd)) = 7738 case round fprnd of 7739 Option.SOME r => writeFPRS(rd,FPConvert.fp64_to_fp32(r,FPRD rs)) 7740 | NONE => signalException Illegal_Instr; 7741 7742fun dfn'FCVT_D_S (rd,(rs,fprnd)) = 7743 case round fprnd of 7744 Option.SOME r => writeFPRD(rd,FPConvert.fp32_to_fp64(FPRS rs)) 7745 | NONE => signalException Illegal_Instr; 7746 7747fun dfn'FSGNJ_D (rd,(rs1,rs2)) = 7748 let 7749 val f1 = FPRD rs1 7750 val f2 = FPRD rs2 7751 in 7752 writeFPRD 7753 (rd,BitsN.@@(BitsN.fromBit(FP64_Sign f2),BitsN.bits(62,0) f1)) 7754 end; 7755 7756fun dfn'FSGNJN_D (rd,(rs1,rs2)) = 7757 let 7758 val f1 = FPRD rs1 7759 val f2 = FPRD rs2 7760 in 7761 writeFPRD 7762 (rd,BitsN.@@(BitsN.fromBit(not(FP64_Sign f2)),BitsN.bits(62,0) f1)) 7763 end; 7764 7765fun dfn'FSGNJX_D (rd,(rs1,rs2)) = 7766 let 7767 val f1 = FPRD rs1 7768 val f2 = FPRD rs2 7769 in 7770 writeFPRD 7771 (rd, 7772 BitsN.@@ 7773 (BitsN.?? 7774 (BitsN.fromBit(FP64_Sign f2),BitsN.fromBit(FP64_Sign f1)), 7775 BitsN.bits(62,0) f1)) 7776 end; 7777 7778fun dfn'FMV_X_D (rd,rs) = write'GPR(BitsN.signExtend 64 (FPRD rs),rd); 7779 7780fun dfn'FMV_D_X (rd,rs) = writeFPRD(rd,GPR rs); 7781 7782fun dfn'FEQ_D (rd,(rs1,rs2)) = 7783 let 7784 val f1 = FPRD rs1 7785 val f2 = FPRD rs2 7786 in 7787 if (FP64_IsSignalingNan f1) orelse (FP64_IsSignalingNan f2) 7788 then ( ( write'GPR(BitsN.B(0x0,64),rd) 7789 ; let 7790 val x = Delta () 7791 in 7792 write'Delta 7793 (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) 7794 end 7795 ) 7796 ; setFP_Invalid () 7797 ) 7798 else let 7799 val res = 7800 case FP64.compare(f1,f2) of 7801 IEEEReal.LESS => BitsN.B(0x0,64) 7802 | IEEEReal.EQUAL => BitsN.B(0x1,64) 7803 | IEEEReal.GREATER => BitsN.B(0x0,64) 7804 | IEEEReal.UNORDERED => BitsN.B(0x0,64) 7805 in 7806 ( write'GPR(res,rd) 7807 ; let 7808 val x = Delta () 7809 in 7810 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7811 end 7812 ) 7813 end 7814 end; 7815 7816fun dfn'FLT_D (rd,(rs1,rs2)) = 7817 let 7818 val f1 = FPRD rs1 7819 val f2 = FPRD rs2 7820 in 7821 if (FP64.isNan f1) orelse (FP64.isNan f2) 7822 then ( ( write'GPR(BitsN.B(0x0,64),rd) 7823 ; let 7824 val x = Delta () 7825 in 7826 write'Delta 7827 (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) 7828 end 7829 ) 7830 ; setFP_Invalid () 7831 ) 7832 else let 7833 val res = 7834 case FP64.compare(f1,f2) of 7835 IEEEReal.LESS => BitsN.B(0x1,64) 7836 | IEEEReal.EQUAL => BitsN.B(0x0,64) 7837 | IEEEReal.GREATER => BitsN.B(0x0,64) 7838 | IEEEReal.UNORDERED => BitsN.B(0x0,64) 7839 in 7840 ( write'GPR(res,rd) 7841 ; let 7842 val x = Delta () 7843 in 7844 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7845 end 7846 ) 7847 end 7848 end; 7849 7850fun dfn'FLE_D (rd,(rs1,rs2)) = 7851 let 7852 val f1 = FPRD rs1 7853 val f2 = FPRD rs2 7854 in 7855 if (FP64.isNan f1) orelse (FP64.isNan f2) 7856 then ( ( write'GPR(BitsN.B(0x0,64),rd) 7857 ; let 7858 val x = Delta () 7859 in 7860 write'Delta 7861 (StateDelta_data1_rupd(x,Option.SOME(BitsN.B(0x0,64)))) 7862 end 7863 ) 7864 ; setFP_Invalid () 7865 ) 7866 else let 7867 val res = 7868 case FP64.compare(f1,f2) of 7869 IEEEReal.LESS => BitsN.B(0x1,64) 7870 | IEEEReal.EQUAL => BitsN.B(0x1,64) 7871 | IEEEReal.GREATER => BitsN.B(0x0,64) 7872 | IEEEReal.UNORDERED => BitsN.B(0x0,64) 7873 in 7874 ( write'GPR(res,rd) 7875 ; let 7876 val x = Delta () 7877 in 7878 write'Delta(StateDelta_data1_rupd(x,Option.SOME res)) 7879 end 7880 ) 7881 end 7882 end; 7883 7884fun dfn'FCLASS_D (rd,rs) = 7885 let 7886 val ret = ref (BitsN.B(0x0,10)) 7887 in 7888 let 7889 val val' = FPRD rs 7890 in 7891 ( ret := 7892 (BitsN.bitFieldInsert(0,0) 7893 ((!ret),BitsN.fromBit(val' = FP64.negInf))) 7894 ; ret := 7895 (BitsN.bitFieldInsert(1,1) 7896 ((!ret), 7897 BitsN.fromBit((FP64_Sign val') andalso (FP64.isNormal val')))) 7898 ; ret := 7899 (BitsN.bitFieldInsert(2,2) 7900 ((!ret), 7901 BitsN.fromBit 7902 ((FP64_Sign val') andalso (FP64.isSubnormal val')))) 7903 ; ret := 7904 (BitsN.bitFieldInsert(3,3) 7905 ((!ret),BitsN.fromBit(val' = FP64.negZero))) 7906 ; ret := 7907 (BitsN.bitFieldInsert(4,4) 7908 ((!ret),BitsN.fromBit(val' = FP64.posZero))) 7909 ; ret := 7910 (BitsN.bitFieldInsert(5,5) 7911 ((!ret), 7912 BitsN.fromBit 7913 ((not(FP64_Sign val')) andalso (FP64.isSubnormal val')))) 7914 ; ret := 7915 (BitsN.bitFieldInsert(6,6) 7916 ((!ret), 7917 BitsN.fromBit 7918 ((not(FP64_Sign val')) andalso (FP64.isNormal val')))) 7919 ; ret := 7920 (BitsN.bitFieldInsert(7,7) 7921 ((!ret),BitsN.fromBit(val' = FP64.posInf))) 7922 ; ret := 7923 (BitsN.bitFieldInsert(8,8) 7924 ((!ret),BitsN.fromBit(FP64_IsSignalingNan val'))) 7925 ; ret := 7926 (BitsN.bitFieldInsert(9,9) 7927 ((!ret),BitsN.fromBit(val' = RV64_CanonicalNan))) 7928 ; write'GPR(BitsN.zeroExtend 64 (!ret),rd) 7929 ; let 7930 val x = Delta () 7931 in 7932 write'Delta 7933 (StateDelta_data1_rupd 7934 (x,Option.SOME(BitsN.zeroExtend 64 (!ret)))) 7935 end 7936 ) 7937 end 7938 end; 7939 7940fun dfn'ECALL () = signalEnvCall (); 7941 7942fun dfn'EBREAK () = signalException Breakpoint; 7943 7944fun dfn'ERET () = write'NextFetch(Option.SOME Ereturn); 7945 7946fun dfn'MRTS () = 7947 ( let 7948 val x = SCSR () 7949 in 7950 write'SCSR 7951 (SupervisorCSR_scause_rupd(x,#mcause((MCSR ()) : MachineCSR))) 7952 end 7953 ; let 7954 val x = SCSR () 7955 in 7956 write'SCSR 7957 (SupervisorCSR_sbadaddr_rupd(x,#mbadaddr((MCSR ()) : MachineCSR))) 7958 end 7959 ; let 7960 val x = SCSR () 7961 in 7962 write'SCSR(SupervisorCSR_sepc_rupd(x,#mepc((MCSR ()) : MachineCSR))) 7963 end 7964 ; let 7965 val x = MCSR () 7966 val x0 = #mstatus(x : MachineCSR) 7967 in 7968 write'MCSR 7969 (MachineCSR_mstatus_rupd 7970 (x,mstatus_MPRV_rupd(x0,privLevel Supervisor))) 7971 end 7972 ; write'NextFetch(Option.SOME Mrts) 7973 ); 7974 7975val dfn'WFI = () 7976 7977fun checkCSROp (csr,(rs1,a)) = 7978 (is_CSR_defined csr) andalso 7979 (check_CSR_access(csrRW csr,(csrPR csr,(curPrivilege (),a)))); 7980 7981fun dfn'CSRRW (rd,(rs1,csr)) = 7982 if checkCSROp(csr,(rs1,Write)) 7983 then let 7984 val val' = CSR csr 7985 in 7986 ( writeCSR(csr,GPR rs1) 7987 ; write'GPR(val',rd) 7988 ; let 7989 val x = Delta () 7990 in 7991 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 7992 end 7993 ) 7994 end 7995 else signalException Illegal_Instr; 7996 7997fun dfn'CSRRS (rd,(rs1,csr)) = 7998 if checkCSROp(csr,(rs1,if rs1 = (BitsN.B(0x0,5)) then Read else Write)) 7999 then let 8000 val val' = CSR csr 8001 in 8002 ( if not(rs1 = (BitsN.B(0x0,5))) 8003 then writeCSR(csr,BitsN.||(val',GPR rs1)) 8004 else () 8005 ; write'GPR(val',rd) 8006 ; let 8007 val x = Delta () 8008 in 8009 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 8010 end 8011 ) 8012 end 8013 else signalException Illegal_Instr; 8014 8015fun dfn'CSRRC (rd,(rs1,csr)) = 8016 if checkCSROp(csr,(rs1,if rs1 = (BitsN.B(0x0,5)) then Read else Write)) 8017 then let 8018 val val' = CSR csr 8019 in 8020 ( if not(rs1 = (BitsN.B(0x0,5))) 8021 then writeCSR(csr,BitsN.&&(val',BitsN.~(GPR rs1))) 8022 else () 8023 ; write'GPR(val',rd) 8024 ; let 8025 val x = Delta () 8026 in 8027 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 8028 end 8029 ) 8030 end 8031 else signalException Illegal_Instr; 8032 8033fun dfn'CSRRWI (rd,(zimm,csr)) = 8034 if checkCSROp 8035 (csr,(zimm,if zimm = (BitsN.B(0x0,5)) then Read else Write)) 8036 then let 8037 val val' = CSR csr 8038 in 8039 ( if not(zimm = (BitsN.B(0x0,5))) 8040 then writeCSR(csr,BitsN.zeroExtend 64 zimm) 8041 else () 8042 ; write'GPR(val',rd) 8043 ; let 8044 val x = Delta () 8045 in 8046 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 8047 end 8048 ) 8049 end 8050 else signalException Illegal_Instr; 8051 8052fun dfn'CSRRSI (rd,(zimm,csr)) = 8053 if checkCSROp 8054 (csr,(zimm,if zimm = (BitsN.B(0x0,5)) then Read else Write)) 8055 then let 8056 val val' = CSR csr 8057 in 8058 ( if not(zimm = (BitsN.B(0x0,5))) 8059 then writeCSR(csr,BitsN.||(val',BitsN.zeroExtend 64 zimm)) 8060 else () 8061 ; write'GPR(val',rd) 8062 ; let 8063 val x = Delta () 8064 in 8065 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 8066 end 8067 ) 8068 end 8069 else signalException Illegal_Instr; 8070 8071fun dfn'CSRRCI (rd,(zimm,csr)) = 8072 if checkCSROp 8073 (csr,(zimm,if zimm = (BitsN.B(0x0,5)) then Read else Write)) 8074 then let 8075 val val' = CSR csr 8076 in 8077 ( if not(zimm = (BitsN.B(0x0,5))) 8078 then writeCSR 8079 (csr, 8080 BitsN.&&(val',BitsN.~(BitsN.zeroExtend 64 zimm))) 8081 else () 8082 ; write'GPR(val',rd) 8083 ; let 8084 val x = Delta () 8085 in 8086 write'Delta(StateDelta_data1_rupd(x,Option.SOME val')) 8087 end 8088 ) 8089 end 8090 else signalException Illegal_Instr; 8091 8092fun dfn'SFENCE_VM rs1 = 8093 let 8094 val addr = 8095 if rs1 = (BitsN.B(0x0,5)) then NONE else Option.SOME(GPR rs1) 8096 in 8097 write'TLB(flushTLB(curASID (),(addr,TLB ()))) 8098 end; 8099 8100fun dfn'UnknownInstruction () = signalException Illegal_Instr; 8101 8102fun dfn'FETCH_MISALIGNED addr = 8103 ( signalAddressException(Fetch_Misaligned,addr) 8104 ; let 8105 val x = Delta () 8106 in 8107 write'Delta(StateDelta_fetch_exc_rupd(x,true)) 8108 end 8109 ; let val x = Delta () in write'Delta(StateDelta_pc_rupd(x,addr)) end 8110 ); 8111 8112fun dfn'FETCH_FAULT addr = 8113 ( signalAddressException(Fetch_Fault,addr) 8114 ; let 8115 val x = Delta () 8116 in 8117 write'Delta(StateDelta_fetch_exc_rupd(x,true)) 8118 end 8119 ; let val x = Delta () in write'Delta(StateDelta_pc_rupd(x,addr)) end 8120 ); 8121 8122fun Run v0 = 8123 case v0 of 8124 UnknownInstruction => dfn'UnknownInstruction () 8125 | FENCE v170 => dfn'FENCE v170 8126 | FENCE_I v171 => dfn'FENCE_I v171 8127 | AMO v1 => 8128 (case v1 of 8129 AMOADD_D v2 => dfn'AMOADD_D v2 8130 | AMOADD_W v3 => dfn'AMOADD_W v3 8131 | AMOAND_D v4 => dfn'AMOAND_D v4 8132 | AMOAND_W v5 => dfn'AMOAND_W v5 8133 | AMOMAXU_D v6 => dfn'AMOMAXU_D v6 8134 | AMOMAXU_W v7 => dfn'AMOMAXU_W v7 8135 | AMOMAX_D v8 => dfn'AMOMAX_D v8 8136 | AMOMAX_W v9 => dfn'AMOMAX_W v9 8137 | AMOMINU_D v10 => dfn'AMOMINU_D v10 8138 | AMOMINU_W v11 => dfn'AMOMINU_W v11 8139 | AMOMIN_D v12 => dfn'AMOMIN_D v12 8140 | AMOMIN_W v13 => dfn'AMOMIN_W v13 8141 | AMOOR_D v14 => dfn'AMOOR_D v14 8142 | AMOOR_W v15 => dfn'AMOOR_W v15 8143 | AMOSWAP_D v16 => dfn'AMOSWAP_D v16 8144 | AMOSWAP_W v17 => dfn'AMOSWAP_W v17 8145 | AMOXOR_D v18 => dfn'AMOXOR_D v18 8146 | AMOXOR_W v19 => dfn'AMOXOR_W v19 8147 | LR_D v20 => dfn'LR_D v20 8148 | LR_W v21 => dfn'LR_W v21 8149 | SC_D v22 => dfn'SC_D v22 8150 | SC_W v23 => dfn'SC_W v23) 8151 | ArithI v24 => 8152 (case v24 of 8153 ADDI v25 => dfn'ADDI v25 8154 | ADDIW v26 => dfn'ADDIW v26 8155 | ANDI v27 => dfn'ANDI v27 8156 | AUIPC v28 => dfn'AUIPC v28 8157 | LUI v29 => dfn'LUI v29 8158 | ORI v30 => dfn'ORI v30 8159 | SLTI v31 => dfn'SLTI v31 8160 | SLTIU v32 => dfn'SLTIU v32 8161 | XORI v33 => dfn'XORI v33) 8162 | ArithR v34 => 8163 (case v34 of 8164 ADD v35 => dfn'ADD v35 8165 | ADDW v36 => dfn'ADDW v36 8166 | AND v37 => dfn'AND v37 8167 | OR v38 => dfn'OR v38 8168 | SLT v39 => dfn'SLT v39 8169 | SLTU v40 => dfn'SLTU v40 8170 | SUB v41 => dfn'SUB v41 8171 | SUBW v42 => dfn'SUBW v42 8172 | XOR v43 => dfn'XOR v43) 8173 | Branch v44 => 8174 (case v44 of 8175 BEQ v45 => dfn'BEQ v45 8176 | BGE v46 => dfn'BGE v46 8177 | BGEU v47 => dfn'BGEU v47 8178 | BLT v48 => dfn'BLT v48 8179 | BLTU v49 => dfn'BLTU v49 8180 | BNE v50 => dfn'BNE v50 8181 | JAL v51 => dfn'JAL v51 8182 | JALR v52 => dfn'JALR v52) 8183 | FArith v53 => 8184 (case v53 of 8185 FADD_D v54 => dfn'FADD_D v54 8186 | FADD_S v55 => dfn'FADD_S v55 8187 | FDIV_D v56 => dfn'FDIV_D v56 8188 | FDIV_S v57 => dfn'FDIV_S v57 8189 | FEQ_D v58 => dfn'FEQ_D v58 8190 | FEQ_S v59 => dfn'FEQ_S v59 8191 | FLE_D v60 => dfn'FLE_D v60 8192 | FLE_S v61 => dfn'FLE_S v61 8193 | FLT_D v62 => dfn'FLT_D v62 8194 | FLT_S v63 => dfn'FLT_S v63 8195 | FMADD_D v64 => dfn'FMADD_D v64 8196 | FMADD_S v65 => dfn'FMADD_S v65 8197 | FMAX_D v66 => dfn'FMAX_D v66 8198 | FMAX_S v67 => dfn'FMAX_S v67 8199 | FMIN_D v68 => dfn'FMIN_D v68 8200 | FMIN_S v69 => dfn'FMIN_S v69 8201 | FMSUB_D v70 => dfn'FMSUB_D v70 8202 | FMSUB_S v71 => dfn'FMSUB_S v71 8203 | FMUL_D v72 => dfn'FMUL_D v72 8204 | FMUL_S v73 => dfn'FMUL_S v73 8205 | FNMADD_D v74 => dfn'FNMADD_D v74 8206 | FNMADD_S v75 => dfn'FNMADD_S v75 8207 | FNMSUB_D v76 => dfn'FNMSUB_D v76 8208 | FNMSUB_S v77 => dfn'FNMSUB_S v77 8209 | FSQRT_D v78 => dfn'FSQRT_D v78 8210 | FSQRT_S v79 => dfn'FSQRT_S v79 8211 | FSUB_D v80 => dfn'FSUB_D v80 8212 | FSUB_S v81 => dfn'FSUB_S v81) 8213 | FConv v82 => 8214 (case v82 of 8215 FCLASS_D v83 => dfn'FCLASS_D v83 8216 | FCLASS_S v84 => dfn'FCLASS_S v84 8217 | FCVT_D_L v85 => dfn'FCVT_D_L v85 8218 | FCVT_D_LU v86 => dfn'FCVT_D_LU v86 8219 | FCVT_D_S v87 => dfn'FCVT_D_S v87 8220 | FCVT_D_W v88 => dfn'FCVT_D_W v88 8221 | FCVT_D_WU v89 => dfn'FCVT_D_WU v89 8222 | FCVT_LU_D v90 => dfn'FCVT_LU_D v90 8223 | FCVT_LU_S v91 => dfn'FCVT_LU_S v91 8224 | FCVT_L_D v92 => dfn'FCVT_L_D v92 8225 | FCVT_L_S v93 => dfn'FCVT_L_S v93 8226 | FCVT_S_D v94 => dfn'FCVT_S_D v94 8227 | FCVT_S_L v95 => dfn'FCVT_S_L v95 8228 | FCVT_S_LU v96 => dfn'FCVT_S_LU v96 8229 | FCVT_S_W v97 => dfn'FCVT_S_W v97 8230 | FCVT_S_WU v98 => dfn'FCVT_S_WU v98 8231 | FCVT_WU_D v99 => dfn'FCVT_WU_D v99 8232 | FCVT_WU_S v100 => dfn'FCVT_WU_S v100 8233 | FCVT_W_D v101 => dfn'FCVT_W_D v101 8234 | FCVT_W_S v102 => dfn'FCVT_W_S v102 8235 | FMV_D_X v103 => dfn'FMV_D_X v103 8236 | FMV_S_X v104 => dfn'FMV_S_X v104 8237 | FMV_X_D v105 => dfn'FMV_X_D v105 8238 | FMV_X_S v106 => dfn'FMV_X_S v106 8239 | FSGNJN_D v107 => dfn'FSGNJN_D v107 8240 | FSGNJN_S v108 => dfn'FSGNJN_S v108 8241 | FSGNJX_D v109 => dfn'FSGNJX_D v109 8242 | FSGNJX_S v110 => dfn'FSGNJX_S v110 8243 | FSGNJ_D v111 => dfn'FSGNJ_D v111 8244 | FSGNJ_S v112 => dfn'FSGNJ_S v112) 8245 | FPLoad v113 => 8246 (case v113 of FLD v114 => dfn'FLD v114 | FLW v115 => dfn'FLW v115) 8247 | FPStore v116 => 8248 (case v116 of FSD v117 => dfn'FSD v117 | FSW v118 => dfn'FSW v118) 8249 | Internal v119 => 8250 (case v119 of 8251 FETCH_FAULT v120 => dfn'FETCH_FAULT v120 8252 | FETCH_MISALIGNED v121 => dfn'FETCH_MISALIGNED v121) 8253 | Load v122 => 8254 (case v122 of 8255 LB v123 => dfn'LB v123 8256 | LBU v124 => dfn'LBU v124 8257 | LD v125 => dfn'LD v125 8258 | LH v126 => dfn'LH v126 8259 | LHU v127 => dfn'LHU v127 8260 | LW v128 => dfn'LW v128 8261 | LWU v129 => dfn'LWU v129) 8262 | MulDiv v130 => 8263 (case v130 of 8264 DIV v131 => dfn'DIV v131 8265 | DIVU v132 => dfn'DIVU v132 8266 | DIVUW v133 => dfn'DIVUW v133 8267 | DIVW v134 => dfn'DIVW v134 8268 | MUL v135 => dfn'MUL v135 8269 | MULH v136 => dfn'MULH v136 8270 | MULHSU v137 => dfn'MULHSU v137 8271 | MULHU v138 => dfn'MULHU v138 8272 | MULW v139 => dfn'MULW v139 8273 | REM v140 => dfn'REM v140 8274 | REMU v141 => dfn'REMU v141 8275 | REMUW v142 => dfn'REMUW v142 8276 | REMW v143 => dfn'REMW v143) 8277 | Shift v144 => 8278 (case v144 of 8279 SLL v145 => dfn'SLL v145 8280 | SLLI v146 => dfn'SLLI v146 8281 | SLLIW v147 => dfn'SLLIW v147 8282 | SLLW v148 => dfn'SLLW v148 8283 | SRA v149 => dfn'SRA v149 8284 | SRAI v150 => dfn'SRAI v150 8285 | SRAIW v151 => dfn'SRAIW v151 8286 | SRAW v152 => dfn'SRAW v152 8287 | SRL v153 => dfn'SRL v153 8288 | SRLI v154 => dfn'SRLI v154 8289 | SRLIW v155 => dfn'SRLIW v155 8290 | SRLW v156 => dfn'SRLW v156) 8291 | Store v157 => 8292 (case v157 of 8293 SB v158 => dfn'SB v158 8294 | SD v159 => dfn'SD v159 8295 | SH v160 => dfn'SH v160 8296 | SW v161 => dfn'SW v161) 8297 | System v162 => 8298 (case v162 of 8299 EBREAK => dfn'EBREAK () 8300 | ECALL => dfn'ECALL () 8301 | ERET => dfn'ERET () 8302 | MRTS => dfn'MRTS () 8303 | WFI => dfn'WFI 8304 | CSRRC v163 => dfn'CSRRC v163 8305 | CSRRCI v164 => dfn'CSRRCI v164 8306 | CSRRS v165 => dfn'CSRRS v165 8307 | CSRRSI v166 => dfn'CSRRSI v166 8308 | CSRRW v167 => dfn'CSRRW v167 8309 | CSRRWI v168 => dfn'CSRRWI v168 8310 | SFENCE_VM v169 => dfn'SFENCE_VM v169); 8311 8312fun Fetch () = 8313 let 8314 val vPC = PC () 8315 in 8316 if not((BitsN.bits(1,0) vPC) = (BitsN.B(0x0,2))) 8317 then F_Error(Internal(FETCH_MISALIGNED vPC)) 8318 else case translateAddr(vPC,(Instruction,Read)) of 8319 Option.SOME pPC => 8320 let 8321 val instw = rawReadInst pPC 8322 in 8323 ( ( let 8324 val x = Delta () 8325 in 8326 write'Delta(StateDelta_exc_taken_rupd(x,false)) 8327 end 8328 ; let 8329 val x = Delta () 8330 in 8331 write'Delta(StateDelta_fetch_exc_rupd(x,false)) 8332 end 8333 ; let 8334 val x = Delta () 8335 in 8336 write'Delta(StateDelta_pc_rupd(x,vPC)) 8337 end 8338 ; let 8339 val x = Delta () 8340 in 8341 write'Delta(StateDelta_rinstr_rupd(x,instw)) 8342 end 8343 ; let 8344 val x = Delta () 8345 in 8346 write'Delta(StateDelta_addr_rupd(x,NONE)) 8347 end 8348 ; let 8349 val x = Delta () 8350 in 8351 write'Delta(StateDelta_data1_rupd(x,NONE)) 8352 end 8353 ; let 8354 val x = Delta () 8355 in 8356 write'Delta(StateDelta_data2_rupd(x,NONE)) 8357 end 8358 ; let 8359 val x = Delta () 8360 in 8361 write'Delta(StateDelta_fp_data_rupd(x,NONE)) 8362 end 8363 ; let 8364 val x = Delta () 8365 in 8366 write'Delta(StateDelta_st_width_rupd(x,NONE)) 8367 end 8368 ) 8369 ; F_Result instw 8370 ) 8371 end 8372 | NONE => F_Error(Internal(FETCH_FAULT vPC)) 8373 end; 8374 8375fun asImm12 (imm12,(imm11,(immhi,immlo))) = 8376 BitsN.concat[imm12,imm11,immhi,immlo]; 8377 8378fun asImm20 (imm20,(immhi,(imm11,immlo))) = 8379 BitsN.concat[imm20,immhi,imm11,immlo]; 8380 8381fun asSImm12 (immhi,immlo) = BitsN.@@(immhi,immlo); 8382 8383fun Decode w = 8384 case boolify'32 w of 8385 (i12'0, 8386 (ihi'5, 8387 (ihi'4, 8388 (ihi'3, 8389 (ihi'2, 8390 (ihi'1, 8391 (ihi'0, 8392 (rs2'4, 8393 (rs2'3, 8394 (rs2'2, 8395 (rs2'1, 8396 (rs2'0, 8397 (rs1'4, 8398 (rs1'3, 8399 (rs1'2, 8400 (rs1'1, 8401 (rs1'0, 8402 (false, 8403 (false, 8404 (false, 8405 (ilo'3, 8406 (ilo'2, 8407 (ilo'1, 8408 (ilo'0, 8409 (i11'0, 8410 (true, 8411 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8412 Branch 8413 (BEQ(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8414 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 8415 asImm12 8416 (BitsN.fromBitstring([i12'0],1), 8417 (BitsN.fromBitstring([i11'0],1), 8418 (BitsN.fromBitstring 8419 ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), 8420 BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) 8421 | (i12'0, 8422 (ihi'5, 8423 (ihi'4, 8424 (ihi'3, 8425 (ihi'2, 8426 (ihi'1, 8427 (ihi'0, 8428 (rs2'4, 8429 (rs2'3, 8430 (rs2'2, 8431 (rs2'1, 8432 (rs2'0, 8433 (rs1'4, 8434 (rs1'3, 8435 (rs1'2, 8436 (rs1'1, 8437 (rs1'0, 8438 (false, 8439 (false, 8440 (true, 8441 (ilo'3, 8442 (ilo'2, 8443 (ilo'1, 8444 (ilo'0, 8445 (i11'0, 8446 (true, 8447 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8448 Branch 8449 (BNE(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8450 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 8451 asImm12 8452 (BitsN.fromBitstring([i12'0],1), 8453 (BitsN.fromBitstring([i11'0],1), 8454 (BitsN.fromBitstring 8455 ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), 8456 BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) 8457 | (i12'0, 8458 (ihi'5, 8459 (ihi'4, 8460 (ihi'3, 8461 (ihi'2, 8462 (ihi'1, 8463 (ihi'0, 8464 (rs2'4, 8465 (rs2'3, 8466 (rs2'2, 8467 (rs2'1, 8468 (rs2'0, 8469 (rs1'4, 8470 (rs1'3, 8471 (rs1'2, 8472 (rs1'1, 8473 (rs1'0, 8474 (true, 8475 (false, 8476 (false, 8477 (ilo'3, 8478 (ilo'2, 8479 (ilo'1, 8480 (ilo'0, 8481 (i11'0, 8482 (true, 8483 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8484 Branch 8485 (BLT(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8486 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 8487 asImm12 8488 (BitsN.fromBitstring([i12'0],1), 8489 (BitsN.fromBitstring([i11'0],1), 8490 (BitsN.fromBitstring 8491 ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), 8492 BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) 8493 | (i12'0, 8494 (ihi'5, 8495 (ihi'4, 8496 (ihi'3, 8497 (ihi'2, 8498 (ihi'1, 8499 (ihi'0, 8500 (rs2'4, 8501 (rs2'3, 8502 (rs2'2, 8503 (rs2'1, 8504 (rs2'0, 8505 (rs1'4, 8506 (rs1'3, 8507 (rs1'2, 8508 (rs1'1, 8509 (rs1'0, 8510 (true, 8511 (false, 8512 (true, 8513 (ilo'3, 8514 (ilo'2, 8515 (ilo'1, 8516 (ilo'0, 8517 (i11'0, 8518 (true, 8519 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8520 Branch 8521 (BGE(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8522 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 8523 asImm12 8524 (BitsN.fromBitstring([i12'0],1), 8525 (BitsN.fromBitstring([i11'0],1), 8526 (BitsN.fromBitstring 8527 ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), 8528 BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) 8529 | (i12'0, 8530 (ihi'5, 8531 (ihi'4, 8532 (ihi'3, 8533 (ihi'2, 8534 (ihi'1, 8535 (ihi'0, 8536 (rs2'4, 8537 (rs2'3, 8538 (rs2'2, 8539 (rs2'1, 8540 (rs2'0, 8541 (rs1'4, 8542 (rs1'3, 8543 (rs1'2, 8544 (rs1'1, 8545 (rs1'0, 8546 (true, 8547 (true, 8548 (false, 8549 (ilo'3, 8550 (ilo'2, 8551 (ilo'1, 8552 (ilo'0, 8553 (i11'0, 8554 (true, 8555 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8556 Branch 8557 (BLTU 8558 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8559 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 8560 asImm12 8561 (BitsN.fromBitstring([i12'0],1), 8562 (BitsN.fromBitstring([i11'0],1), 8563 (BitsN.fromBitstring 8564 ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), 8565 BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) 8566 | (i12'0, 8567 (ihi'5, 8568 (ihi'4, 8569 (ihi'3, 8570 (ihi'2, 8571 (ihi'1, 8572 (ihi'0, 8573 (rs2'4, 8574 (rs2'3, 8575 (rs2'2, 8576 (rs2'1, 8577 (rs2'0, 8578 (rs1'4, 8579 (rs1'3, 8580 (rs1'2, 8581 (rs1'1, 8582 (rs1'0, 8583 (true, 8584 (true, 8585 (true, 8586 (ilo'3, 8587 (ilo'2, 8588 (ilo'1, 8589 (ilo'0, 8590 (i11'0, 8591 (true, 8592 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8593 Branch 8594 (BGEU 8595 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8596 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 8597 asImm12 8598 (BitsN.fromBitstring([i12'0],1), 8599 (BitsN.fromBitstring([i11'0],1), 8600 (BitsN.fromBitstring 8601 ([ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],6), 8602 BitsN.fromBitstring([ilo'3,ilo'2,ilo'1,ilo'0],4))))))) 8603 | (imm'11, 8604 (imm'10, 8605 (imm'9, 8606 (imm'8, 8607 (imm'7, 8608 (imm'6, 8609 (imm'5, 8610 (imm'4, 8611 (imm'3, 8612 (imm'2, 8613 (imm'1, 8614 (imm'0, 8615 (rs1'4, 8616 (rs1'3, 8617 (rs1'2, 8618 (rs1'1, 8619 (rs1'0, 8620 (false, 8621 (false, 8622 (false, 8623 (rd'4, 8624 (rd'3, 8625 (rd'2, 8626 (rd'1, 8627 (rd'0, 8628 (true, 8629 (true,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 8630 Branch 8631 (JALR 8632 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8633 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8634 BitsN.fromBitstring 8635 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 8636 imm'2,imm'1,imm'0],12)))) 8637 | (i20'0, 8638 (ilo'9, 8639 (ilo'8, 8640 (ilo'7, 8641 (ilo'6, 8642 (ilo'5, 8643 (ilo'4, 8644 (ilo'3, 8645 (ilo'2, 8646 (ilo'1, 8647 (ilo'0, 8648 (i11'0, 8649 (ihi'7, 8650 (ihi'6, 8651 (ihi'5, 8652 (ihi'4, 8653 (ihi'3, 8654 (ihi'2, 8655 (ihi'1, 8656 (ihi'0, 8657 (rd'4, 8658 (rd'3, 8659 (rd'2, 8660 (rd'1, 8661 (rd'0, 8662 (true,(true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 8663 Branch 8664 (JAL(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8665 asImm20 8666 (BitsN.fromBitstring([i20'0],1), 8667 (BitsN.fromBitstring 8668 ([ihi'7,ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],8), 8669 (BitsN.fromBitstring([i11'0],1), 8670 BitsN.fromBitstring 8671 ([ilo'9,ilo'8,ilo'7,ilo'6,ilo'5,ilo'4,ilo'3,ilo'2, 8672 ilo'1,ilo'0],10)))))) 8673 | (imm'19, 8674 (imm'18, 8675 (imm'17, 8676 (imm'16, 8677 (imm'15, 8678 (imm'14, 8679 (imm'13, 8680 (imm'12, 8681 (imm'11, 8682 (imm'10, 8683 (imm'9, 8684 (imm'8, 8685 (imm'7, 8686 (imm'6, 8687 (imm'5, 8688 (imm'4, 8689 (imm'3, 8690 (imm'2, 8691 (imm'1, 8692 (imm'0, 8693 (rd'4, 8694 (rd'3, 8695 (rd'2, 8696 (rd'1, 8697 (rd'0, 8698 (false, 8699 (true,(true,(false,(true,(true,true))))))))))))))))))))))))))))))) => 8700 ArithI 8701 (LUI(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8702 BitsN.fromBitstring 8703 ([imm'19,imm'18,imm'17,imm'16,imm'15,imm'14,imm'13,imm'12, 8704 imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 8705 imm'2,imm'1,imm'0],20))) 8706 | (imm'19, 8707 (imm'18, 8708 (imm'17, 8709 (imm'16, 8710 (imm'15, 8711 (imm'14, 8712 (imm'13, 8713 (imm'12, 8714 (imm'11, 8715 (imm'10, 8716 (imm'9, 8717 (imm'8, 8718 (imm'7, 8719 (imm'6, 8720 (imm'5, 8721 (imm'4, 8722 (imm'3, 8723 (imm'2, 8724 (imm'1, 8725 (imm'0, 8726 (rd'4, 8727 (rd'3, 8728 (rd'2, 8729 (rd'1, 8730 (rd'0, 8731 (false, 8732 (false,(true,(false,(true,(true,true))))))))))))))))))))))))))))))) => 8733 ArithI 8734 (AUIPC 8735 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8736 BitsN.fromBitstring 8737 ([imm'19,imm'18,imm'17,imm'16,imm'15,imm'14,imm'13,imm'12, 8738 imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 8739 imm'2,imm'1,imm'0],20))) 8740 | (imm'11, 8741 (imm'10, 8742 (imm'9, 8743 (imm'8, 8744 (imm'7, 8745 (imm'6, 8746 (imm'5, 8747 (imm'4, 8748 (imm'3, 8749 (imm'2, 8750 (imm'1, 8751 (imm'0, 8752 (rs1'4, 8753 (rs1'3, 8754 (rs1'2, 8755 (rs1'1, 8756 (rs1'0, 8757 (false, 8758 (false, 8759 (false, 8760 (rd'4, 8761 (rd'3, 8762 (rd'2, 8763 (rd'1, 8764 (rd'0, 8765 (false, 8766 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8767 ArithI 8768 (ADDI 8769 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8770 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8771 BitsN.fromBitstring 8772 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 8773 imm'2,imm'1,imm'0],12)))) 8774 | (false, 8775 (false, 8776 (false, 8777 (false, 8778 (false, 8779 (false, 8780 (shamt'5, 8781 (shamt'4, 8782 (shamt'3, 8783 (shamt'2, 8784 (shamt'1, 8785 (shamt'0, 8786 (rs1'4, 8787 (rs1'3, 8788 (rs1'2, 8789 (rs1'1, 8790 (rs1'0, 8791 (false, 8792 (false, 8793 (true, 8794 (rd'4, 8795 (rd'3, 8796 (rd'2, 8797 (rd'1, 8798 (rd'0, 8799 (false, 8800 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8801 Shift 8802 (SLLI 8803 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8804 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8805 BitsN.fromBitstring 8806 ([shamt'5,shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],6)))) 8807 | (imm'11, 8808 (imm'10, 8809 (imm'9, 8810 (imm'8, 8811 (imm'7, 8812 (imm'6, 8813 (imm'5, 8814 (imm'4, 8815 (imm'3, 8816 (imm'2, 8817 (imm'1, 8818 (imm'0, 8819 (rs1'4, 8820 (rs1'3, 8821 (rs1'2, 8822 (rs1'1, 8823 (rs1'0, 8824 (false, 8825 (true, 8826 (false, 8827 (rd'4, 8828 (rd'3, 8829 (rd'2, 8830 (rd'1, 8831 (rd'0, 8832 (false, 8833 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8834 ArithI 8835 (SLTI 8836 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8837 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8838 BitsN.fromBitstring 8839 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 8840 imm'2,imm'1,imm'0],12)))) 8841 | (imm'11, 8842 (imm'10, 8843 (imm'9, 8844 (imm'8, 8845 (imm'7, 8846 (imm'6, 8847 (imm'5, 8848 (imm'4, 8849 (imm'3, 8850 (imm'2, 8851 (imm'1, 8852 (imm'0, 8853 (rs1'4, 8854 (rs1'3, 8855 (rs1'2, 8856 (rs1'1, 8857 (rs1'0, 8858 (false, 8859 (true, 8860 (true, 8861 (rd'4, 8862 (rd'3, 8863 (rd'2, 8864 (rd'1, 8865 (rd'0, 8866 (false, 8867 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8868 ArithI 8869 (SLTIU 8870 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8871 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8872 BitsN.fromBitstring 8873 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 8874 imm'2,imm'1,imm'0],12)))) 8875 | (imm'11, 8876 (imm'10, 8877 (imm'9, 8878 (imm'8, 8879 (imm'7, 8880 (imm'6, 8881 (imm'5, 8882 (imm'4, 8883 (imm'3, 8884 (imm'2, 8885 (imm'1, 8886 (imm'0, 8887 (rs1'4, 8888 (rs1'3, 8889 (rs1'2, 8890 (rs1'1, 8891 (rs1'0, 8892 (true, 8893 (false, 8894 (false, 8895 (rd'4, 8896 (rd'3, 8897 (rd'2, 8898 (rd'1, 8899 (rd'0, 8900 (false, 8901 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8902 ArithI 8903 (XORI 8904 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8905 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8906 BitsN.fromBitstring 8907 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 8908 imm'2,imm'1,imm'0],12)))) 8909 | (false, 8910 (false, 8911 (false, 8912 (false, 8913 (false, 8914 (false, 8915 (shamt'5, 8916 (shamt'4, 8917 (shamt'3, 8918 (shamt'2, 8919 (shamt'1, 8920 (shamt'0, 8921 (rs1'4, 8922 (rs1'3, 8923 (rs1'2, 8924 (rs1'1, 8925 (rs1'0, 8926 (true, 8927 (false, 8928 (true, 8929 (rd'4, 8930 (rd'3, 8931 (rd'2, 8932 (rd'1, 8933 (rd'0, 8934 (false, 8935 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8936 Shift 8937 (SRLI 8938 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8939 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8940 BitsN.fromBitstring 8941 ([shamt'5,shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],6)))) 8942 | (false, 8943 (true, 8944 (false, 8945 (false, 8946 (false, 8947 (false, 8948 (shamt'5, 8949 (shamt'4, 8950 (shamt'3, 8951 (shamt'2, 8952 (shamt'1, 8953 (shamt'0, 8954 (rs1'4, 8955 (rs1'3, 8956 (rs1'2, 8957 (rs1'1, 8958 (rs1'0, 8959 (true, 8960 (false, 8961 (true, 8962 (rd'4, 8963 (rd'3, 8964 (rd'2, 8965 (rd'1, 8966 (rd'0, 8967 (false, 8968 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 8969 Shift 8970 (SRAI 8971 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 8972 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 8973 BitsN.fromBitstring 8974 ([shamt'5,shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],6)))) 8975 | (imm'11, 8976 (imm'10, 8977 (imm'9, 8978 (imm'8, 8979 (imm'7, 8980 (imm'6, 8981 (imm'5, 8982 (imm'4, 8983 (imm'3, 8984 (imm'2, 8985 (imm'1, 8986 (imm'0, 8987 (rs1'4, 8988 (rs1'3, 8989 (rs1'2, 8990 (rs1'1, 8991 (rs1'0, 8992 (true, 8993 (true, 8994 (false, 8995 (rd'4, 8996 (rd'3, 8997 (rd'2, 8998 (rd'1, 8999 (rd'0, 9000 (false, 9001 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9002 ArithI 9003 (ORI(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9004 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9005 BitsN.fromBitstring 9006 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 9007 imm'2,imm'1,imm'0],12)))) 9008 | (imm'11, 9009 (imm'10, 9010 (imm'9, 9011 (imm'8, 9012 (imm'7, 9013 (imm'6, 9014 (imm'5, 9015 (imm'4, 9016 (imm'3, 9017 (imm'2, 9018 (imm'1, 9019 (imm'0, 9020 (rs1'4, 9021 (rs1'3, 9022 (rs1'2, 9023 (rs1'1, 9024 (rs1'0, 9025 (true, 9026 (true, 9027 (true, 9028 (rd'4, 9029 (rd'3, 9030 (rd'2, 9031 (rd'1, 9032 (rd'0, 9033 (false, 9034 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9035 ArithI 9036 (ANDI 9037 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9038 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9039 BitsN.fromBitstring 9040 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 9041 imm'2,imm'1,imm'0],12)))) 9042 | (false, 9043 (false, 9044 (false, 9045 (false, 9046 (false, 9047 (false, 9048 (false, 9049 (rs2'4, 9050 (rs2'3, 9051 (rs2'2, 9052 (rs2'1, 9053 (rs2'0, 9054 (rs1'4, 9055 (rs1'3, 9056 (rs1'2, 9057 (rs1'1, 9058 (rs1'0, 9059 (false, 9060 (false, 9061 (false, 9062 (rd'4, 9063 (rd'3, 9064 (rd'2, 9065 (rd'1, 9066 (rd'0, 9067 (false, 9068 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9069 ArithR 9070 (ADD(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9071 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9072 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9073 | (false, 9074 (true, 9075 (false, 9076 (false, 9077 (false, 9078 (false, 9079 (false, 9080 (rs2'4, 9081 (rs2'3, 9082 (rs2'2, 9083 (rs2'1, 9084 (rs2'0, 9085 (rs1'4, 9086 (rs1'3, 9087 (rs1'2, 9088 (rs1'1, 9089 (rs1'0, 9090 (false, 9091 (false, 9092 (false, 9093 (rd'4, 9094 (rd'3, 9095 (rd'2, 9096 (rd'1, 9097 (rd'0, 9098 (false, 9099 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9100 ArithR 9101 (SUB(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9102 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9103 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9104 | (false, 9105 (false, 9106 (false, 9107 (false, 9108 (false, 9109 (false, 9110 (false, 9111 (rs2'4, 9112 (rs2'3, 9113 (rs2'2, 9114 (rs2'1, 9115 (rs2'0, 9116 (rs1'4, 9117 (rs1'3, 9118 (rs1'2, 9119 (rs1'1, 9120 (rs1'0, 9121 (false, 9122 (false, 9123 (true, 9124 (rd'4, 9125 (rd'3, 9126 (rd'2, 9127 (rd'1, 9128 (rd'0, 9129 (false, 9130 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9131 Shift 9132 (SLL(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9133 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9134 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9135 | (false, 9136 (false, 9137 (false, 9138 (false, 9139 (false, 9140 (false, 9141 (false, 9142 (rs2'4, 9143 (rs2'3, 9144 (rs2'2, 9145 (rs2'1, 9146 (rs2'0, 9147 (rs1'4, 9148 (rs1'3, 9149 (rs1'2, 9150 (rs1'1, 9151 (rs1'0, 9152 (false, 9153 (true, 9154 (false, 9155 (rd'4, 9156 (rd'3, 9157 (rd'2, 9158 (rd'1, 9159 (rd'0, 9160 (false, 9161 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9162 ArithR 9163 (SLT(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9164 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9165 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9166 | (false, 9167 (false, 9168 (false, 9169 (false, 9170 (false, 9171 (false, 9172 (false, 9173 (rs2'4, 9174 (rs2'3, 9175 (rs2'2, 9176 (rs2'1, 9177 (rs2'0, 9178 (rs1'4, 9179 (rs1'3, 9180 (rs1'2, 9181 (rs1'1, 9182 (rs1'0, 9183 (false, 9184 (true, 9185 (true, 9186 (rd'4, 9187 (rd'3, 9188 (rd'2, 9189 (rd'1, 9190 (rd'0, 9191 (false, 9192 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9193 ArithR 9194 (SLTU 9195 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9196 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9197 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9198 | (false, 9199 (false, 9200 (false, 9201 (false, 9202 (false, 9203 (false, 9204 (false, 9205 (rs2'4, 9206 (rs2'3, 9207 (rs2'2, 9208 (rs2'1, 9209 (rs2'0, 9210 (rs1'4, 9211 (rs1'3, 9212 (rs1'2, 9213 (rs1'1, 9214 (rs1'0, 9215 (true, 9216 (false, 9217 (false, 9218 (rd'4, 9219 (rd'3, 9220 (rd'2, 9221 (rd'1, 9222 (rd'0, 9223 (false, 9224 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9225 ArithR 9226 (XOR(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9227 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9228 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9229 | (false, 9230 (false, 9231 (false, 9232 (false, 9233 (false, 9234 (false, 9235 (false, 9236 (rs2'4, 9237 (rs2'3, 9238 (rs2'2, 9239 (rs2'1, 9240 (rs2'0, 9241 (rs1'4, 9242 (rs1'3, 9243 (rs1'2, 9244 (rs1'1, 9245 (rs1'0, 9246 (true, 9247 (false, 9248 (true, 9249 (rd'4, 9250 (rd'3, 9251 (rd'2, 9252 (rd'1, 9253 (rd'0, 9254 (false, 9255 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9256 Shift 9257 (SRL(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9258 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9259 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9260 | (false, 9261 (true, 9262 (false, 9263 (false, 9264 (false, 9265 (false, 9266 (false, 9267 (rs2'4, 9268 (rs2'3, 9269 (rs2'2, 9270 (rs2'1, 9271 (rs2'0, 9272 (rs1'4, 9273 (rs1'3, 9274 (rs1'2, 9275 (rs1'1, 9276 (rs1'0, 9277 (true, 9278 (false, 9279 (true, 9280 (rd'4, 9281 (rd'3, 9282 (rd'2, 9283 (rd'1, 9284 (rd'0, 9285 (false, 9286 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9287 Shift 9288 (SRA(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9289 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9290 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9291 | (false, 9292 (false, 9293 (false, 9294 (false, 9295 (false, 9296 (false, 9297 (false, 9298 (rs2'4, 9299 (rs2'3, 9300 (rs2'2, 9301 (rs2'1, 9302 (rs2'0, 9303 (rs1'4, 9304 (rs1'3, 9305 (rs1'2, 9306 (rs1'1, 9307 (rs1'0, 9308 (true, 9309 (true, 9310 (false, 9311 (rd'4, 9312 (rd'3, 9313 (rd'2, 9314 (rd'1, 9315 (rd'0, 9316 (false, 9317 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9318 ArithR 9319 (OR(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9320 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9321 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9322 | (false, 9323 (false, 9324 (false, 9325 (false, 9326 (false, 9327 (false, 9328 (false, 9329 (rs2'4, 9330 (rs2'3, 9331 (rs2'2, 9332 (rs2'1, 9333 (rs2'0, 9334 (rs1'4, 9335 (rs1'3, 9336 (rs1'2, 9337 (rs1'1, 9338 (rs1'0, 9339 (true, 9340 (true, 9341 (true, 9342 (rd'4, 9343 (rd'3, 9344 (rd'2, 9345 (rd'1, 9346 (rd'0, 9347 (false, 9348 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9349 ArithR 9350 (AND(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9351 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9352 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9353 | (imm'11, 9354 (imm'10, 9355 (imm'9, 9356 (imm'8, 9357 (imm'7, 9358 (imm'6, 9359 (imm'5, 9360 (imm'4, 9361 (imm'3, 9362 (imm'2, 9363 (imm'1, 9364 (imm'0, 9365 (rs1'4, 9366 (rs1'3, 9367 (rs1'2, 9368 (rs1'1, 9369 (rs1'0, 9370 (false, 9371 (false, 9372 (false, 9373 (rd'4, 9374 (rd'3, 9375 (rd'2, 9376 (rd'1, 9377 (rd'0, 9378 (false, 9379 (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9380 ArithI 9381 (ADDIW 9382 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9383 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9384 BitsN.fromBitstring 9385 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 9386 imm'2,imm'1,imm'0],12)))) 9387 | (false, 9388 (false, 9389 (false, 9390 (false, 9391 (false, 9392 (false, 9393 (false, 9394 (shamt'4, 9395 (shamt'3, 9396 (shamt'2, 9397 (shamt'1, 9398 (shamt'0, 9399 (rs1'4, 9400 (rs1'3, 9401 (rs1'2, 9402 (rs1'1, 9403 (rs1'0, 9404 (false, 9405 (false, 9406 (true, 9407 (rd'4, 9408 (rd'3, 9409 (rd'2, 9410 (rd'1, 9411 (rd'0, 9412 (false, 9413 (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9414 Shift 9415 (SLLIW 9416 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9417 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9418 BitsN.fromBitstring 9419 ([shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],5)))) 9420 | (false, 9421 (false, 9422 (false, 9423 (false, 9424 (false, 9425 (false, 9426 (false, 9427 (shamt'4, 9428 (shamt'3, 9429 (shamt'2, 9430 (shamt'1, 9431 (shamt'0, 9432 (rs1'4, 9433 (rs1'3, 9434 (rs1'2, 9435 (rs1'1, 9436 (rs1'0, 9437 (true, 9438 (false, 9439 (true, 9440 (rd'4, 9441 (rd'3, 9442 (rd'2, 9443 (rd'1, 9444 (rd'0, 9445 (false, 9446 (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9447 Shift 9448 (SRLIW 9449 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9450 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9451 BitsN.fromBitstring 9452 ([shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],5)))) 9453 | (false, 9454 (true, 9455 (false, 9456 (false, 9457 (false, 9458 (false, 9459 (false, 9460 (shamt'4, 9461 (shamt'3, 9462 (shamt'2, 9463 (shamt'1, 9464 (shamt'0, 9465 (rs1'4, 9466 (rs1'3, 9467 (rs1'2, 9468 (rs1'1, 9469 (rs1'0, 9470 (true, 9471 (false, 9472 (true, 9473 (rd'4, 9474 (rd'3, 9475 (rd'2, 9476 (rd'1, 9477 (rd'0, 9478 (false, 9479 (false,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9480 Shift 9481 (SRAIW 9482 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9483 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9484 BitsN.fromBitstring 9485 ([shamt'4,shamt'3,shamt'2,shamt'1,shamt'0],5)))) 9486 | (false, 9487 (false, 9488 (false, 9489 (false, 9490 (false, 9491 (false, 9492 (false, 9493 (rs2'4, 9494 (rs2'3, 9495 (rs2'2, 9496 (rs2'1, 9497 (rs2'0, 9498 (rs1'4, 9499 (rs1'3, 9500 (rs1'2, 9501 (rs1'1, 9502 (rs1'0, 9503 (false, 9504 (false, 9505 (false, 9506 (rd'4, 9507 (rd'3, 9508 (rd'2, 9509 (rd'1, 9510 (rd'0, 9511 (false, 9512 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9513 ArithR 9514 (ADDW 9515 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9516 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9517 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9518 | (false, 9519 (true, 9520 (false, 9521 (false, 9522 (false, 9523 (false, 9524 (false, 9525 (rs2'4, 9526 (rs2'3, 9527 (rs2'2, 9528 (rs2'1, 9529 (rs2'0, 9530 (rs1'4, 9531 (rs1'3, 9532 (rs1'2, 9533 (rs1'1, 9534 (rs1'0, 9535 (false, 9536 (false, 9537 (false, 9538 (rd'4, 9539 (rd'3, 9540 (rd'2, 9541 (rd'1, 9542 (rd'0, 9543 (false, 9544 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9545 ArithR 9546 (SUBW 9547 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9548 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9549 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9550 | (false, 9551 (false, 9552 (false, 9553 (false, 9554 (false, 9555 (false, 9556 (false, 9557 (rs2'4, 9558 (rs2'3, 9559 (rs2'2, 9560 (rs2'1, 9561 (rs2'0, 9562 (rs1'4, 9563 (rs1'3, 9564 (rs1'2, 9565 (rs1'1, 9566 (rs1'0, 9567 (false, 9568 (false, 9569 (true, 9570 (rd'4, 9571 (rd'3, 9572 (rd'2, 9573 (rd'1, 9574 (rd'0, 9575 (false, 9576 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9577 Shift 9578 (SLLW 9579 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9580 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9581 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9582 | (false, 9583 (false, 9584 (false, 9585 (false, 9586 (false, 9587 (false, 9588 (false, 9589 (rs2'4, 9590 (rs2'3, 9591 (rs2'2, 9592 (rs2'1, 9593 (rs2'0, 9594 (rs1'4, 9595 (rs1'3, 9596 (rs1'2, 9597 (rs1'1, 9598 (rs1'0, 9599 (true, 9600 (false, 9601 (true, 9602 (rd'4, 9603 (rd'3, 9604 (rd'2, 9605 (rd'1, 9606 (rd'0, 9607 (false, 9608 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9609 Shift 9610 (SRLW 9611 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9612 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9613 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9614 | (false, 9615 (true, 9616 (false, 9617 (false, 9618 (false, 9619 (false, 9620 (false, 9621 (rs2'4, 9622 (rs2'3, 9623 (rs2'2, 9624 (rs2'1, 9625 (rs2'0, 9626 (rs1'4, 9627 (rs1'3, 9628 (rs1'2, 9629 (rs1'1, 9630 (rs1'0, 9631 (true, 9632 (false, 9633 (true, 9634 (rd'4, 9635 (rd'3, 9636 (rd'2, 9637 (rd'1, 9638 (rd'0, 9639 (false, 9640 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9641 Shift 9642 (SRAW 9643 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9644 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9645 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9646 | (false, 9647 (false, 9648 (false, 9649 (false, 9650 (false, 9651 (false, 9652 (true, 9653 (rs2'4, 9654 (rs2'3, 9655 (rs2'2, 9656 (rs2'1, 9657 (rs2'0, 9658 (rs1'4, 9659 (rs1'3, 9660 (rs1'2, 9661 (rs1'1, 9662 (rs1'0, 9663 (false, 9664 (false, 9665 (false, 9666 (rd'4, 9667 (rd'3, 9668 (rd'2, 9669 (rd'1, 9670 (rd'0, 9671 (false, 9672 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9673 MulDiv 9674 (MUL(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9675 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9676 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9677 | (false, 9678 (false, 9679 (false, 9680 (false, 9681 (false, 9682 (false, 9683 (true, 9684 (rs2'4, 9685 (rs2'3, 9686 (rs2'2, 9687 (rs2'1, 9688 (rs2'0, 9689 (rs1'4, 9690 (rs1'3, 9691 (rs1'2, 9692 (rs1'1, 9693 (rs1'0, 9694 (false, 9695 (false, 9696 (true, 9697 (rd'4, 9698 (rd'3, 9699 (rd'2, 9700 (rd'1, 9701 (rd'0, 9702 (false, 9703 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9704 MulDiv 9705 (MULH 9706 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9707 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9708 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9709 | (false, 9710 (false, 9711 (false, 9712 (false, 9713 (false, 9714 (false, 9715 (true, 9716 (rs2'4, 9717 (rs2'3, 9718 (rs2'2, 9719 (rs2'1, 9720 (rs2'0, 9721 (rs1'4, 9722 (rs1'3, 9723 (rs1'2, 9724 (rs1'1, 9725 (rs1'0, 9726 (false, 9727 (true, 9728 (false, 9729 (rd'4, 9730 (rd'3, 9731 (rd'2, 9732 (rd'1, 9733 (rd'0, 9734 (false, 9735 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9736 MulDiv 9737 (MULHSU 9738 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9739 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9740 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9741 | (false, 9742 (false, 9743 (false, 9744 (false, 9745 (false, 9746 (false, 9747 (true, 9748 (rs2'4, 9749 (rs2'3, 9750 (rs2'2, 9751 (rs2'1, 9752 (rs2'0, 9753 (rs1'4, 9754 (rs1'3, 9755 (rs1'2, 9756 (rs1'1, 9757 (rs1'0, 9758 (false, 9759 (true, 9760 (true, 9761 (rd'4, 9762 (rd'3, 9763 (rd'2, 9764 (rd'1, 9765 (rd'0, 9766 (false, 9767 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9768 MulDiv 9769 (MULHU 9770 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9771 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9772 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9773 | (false, 9774 (false, 9775 (false, 9776 (false, 9777 (false, 9778 (false, 9779 (true, 9780 (rs2'4, 9781 (rs2'3, 9782 (rs2'2, 9783 (rs2'1, 9784 (rs2'0, 9785 (rs1'4, 9786 (rs1'3, 9787 (rs1'2, 9788 (rs1'1, 9789 (rs1'0, 9790 (true, 9791 (false, 9792 (false, 9793 (rd'4, 9794 (rd'3, 9795 (rd'2, 9796 (rd'1, 9797 (rd'0, 9798 (false, 9799 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9800 MulDiv 9801 (DIV(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9802 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9803 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9804 | (false, 9805 (false, 9806 (false, 9807 (false, 9808 (false, 9809 (false, 9810 (true, 9811 (rs2'4, 9812 (rs2'3, 9813 (rs2'2, 9814 (rs2'1, 9815 (rs2'0, 9816 (rs1'4, 9817 (rs1'3, 9818 (rs1'2, 9819 (rs1'1, 9820 (rs1'0, 9821 (true, 9822 (false, 9823 (true, 9824 (rd'4, 9825 (rd'3, 9826 (rd'2, 9827 (rd'1, 9828 (rd'0, 9829 (false, 9830 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9831 MulDiv 9832 (DIVU 9833 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9834 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9835 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9836 | (false, 9837 (false, 9838 (false, 9839 (false, 9840 (false, 9841 (false, 9842 (true, 9843 (rs2'4, 9844 (rs2'3, 9845 (rs2'2, 9846 (rs2'1, 9847 (rs2'0, 9848 (rs1'4, 9849 (rs1'3, 9850 (rs1'2, 9851 (rs1'1, 9852 (rs1'0, 9853 (true, 9854 (true, 9855 (false, 9856 (rd'4, 9857 (rd'3, 9858 (rd'2, 9859 (rd'1, 9860 (rd'0, 9861 (false, 9862 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9863 MulDiv 9864 (REM(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9865 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9866 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9867 | (false, 9868 (false, 9869 (false, 9870 (false, 9871 (false, 9872 (false, 9873 (true, 9874 (rs2'4, 9875 (rs2'3, 9876 (rs2'2, 9877 (rs2'1, 9878 (rs2'0, 9879 (rs1'4, 9880 (rs1'3, 9881 (rs1'2, 9882 (rs1'1, 9883 (rs1'0, 9884 (true, 9885 (true, 9886 (true, 9887 (rd'4, 9888 (rd'3, 9889 (rd'2, 9890 (rd'1, 9891 (rd'0, 9892 (false, 9893 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 9894 MulDiv 9895 (REMU 9896 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9897 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9898 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9899 | (false, 9900 (false, 9901 (false, 9902 (false, 9903 (false, 9904 (false, 9905 (true, 9906 (rs2'4, 9907 (rs2'3, 9908 (rs2'2, 9909 (rs2'1, 9910 (rs2'0, 9911 (rs1'4, 9912 (rs1'3, 9913 (rs1'2, 9914 (rs1'1, 9915 (rs1'0, 9916 (false, 9917 (false, 9918 (false, 9919 (rd'4, 9920 (rd'3, 9921 (rd'2, 9922 (rd'1, 9923 (rd'0, 9924 (false, 9925 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9926 MulDiv 9927 (MULW 9928 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9929 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9930 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9931 | (false, 9932 (false, 9933 (false, 9934 (false, 9935 (false, 9936 (false, 9937 (true, 9938 (rs2'4, 9939 (rs2'3, 9940 (rs2'2, 9941 (rs2'1, 9942 (rs2'0, 9943 (rs1'4, 9944 (rs1'3, 9945 (rs1'2, 9946 (rs1'1, 9947 (rs1'0, 9948 (true, 9949 (false, 9950 (false, 9951 (rd'4, 9952 (rd'3, 9953 (rd'2, 9954 (rd'1, 9955 (rd'0, 9956 (false, 9957 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9958 MulDiv 9959 (DIVW 9960 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9961 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9962 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9963 | (false, 9964 (false, 9965 (false, 9966 (false, 9967 (false, 9968 (false, 9969 (true, 9970 (rs2'4, 9971 (rs2'3, 9972 (rs2'2, 9973 (rs2'1, 9974 (rs2'0, 9975 (rs1'4, 9976 (rs1'3, 9977 (rs1'2, 9978 (rs1'1, 9979 (rs1'0, 9980 (true, 9981 (false, 9982 (true, 9983 (rd'4, 9984 (rd'3, 9985 (rd'2, 9986 (rd'1, 9987 (rd'0, 9988 (false, 9989 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 9990 MulDiv 9991 (DIVUW 9992 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 9993 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 9994 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 9995 | (false, 9996 (false, 9997 (false, 9998 (false, 9999 (false, 10000 (false, 10001 (true, 10002 (rs2'4, 10003 (rs2'3, 10004 (rs2'2, 10005 (rs2'1, 10006 (rs2'0, 10007 (rs1'4, 10008 (rs1'3, 10009 (rs1'2, 10010 (rs1'1, 10011 (rs1'0, 10012 (true, 10013 (true, 10014 (false, 10015 (rd'4, 10016 (rd'3, 10017 (rd'2, 10018 (rd'1, 10019 (rd'0, 10020 (false, 10021 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 10022 MulDiv 10023 (REMW 10024 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10025 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10026 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 10027 | (false, 10028 (false, 10029 (false, 10030 (false, 10031 (false, 10032 (false, 10033 (true, 10034 (rs2'4, 10035 (rs2'3, 10036 (rs2'2, 10037 (rs2'1, 10038 (rs2'0, 10039 (rs1'4, 10040 (rs1'3, 10041 (rs1'2, 10042 (rs1'1, 10043 (rs1'0, 10044 (true, 10045 (true, 10046 (true, 10047 (rd'4, 10048 (rd'3, 10049 (rd'2, 10050 (rd'1, 10051 (rd'0, 10052 (false, 10053 (true,(true,(true,(false,(true,true))))))))))))))))))))))))))))))) => 10054 MulDiv 10055 (REMUW 10056 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10057 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10058 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 10059 | (imm'11, 10060 (imm'10, 10061 (imm'9, 10062 (imm'8, 10063 (imm'7, 10064 (imm'6, 10065 (imm'5, 10066 (imm'4, 10067 (imm'3, 10068 (imm'2, 10069 (imm'1, 10070 (imm'0, 10071 (rs1'4, 10072 (rs1'3, 10073 (rs1'2, 10074 (rs1'1, 10075 (rs1'0, 10076 (false, 10077 (false, 10078 (false, 10079 (rd'4, 10080 (rd'3, 10081 (rd'2, 10082 (rd'1, 10083 (rd'0, 10084 (false, 10085 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10086 Load 10087 (LB(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10088 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10089 BitsN.fromBitstring 10090 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 10091 imm'2,imm'1,imm'0],12)))) 10092 | (imm'11, 10093 (imm'10, 10094 (imm'9, 10095 (imm'8, 10096 (imm'7, 10097 (imm'6, 10098 (imm'5, 10099 (imm'4, 10100 (imm'3, 10101 (imm'2, 10102 (imm'1, 10103 (imm'0, 10104 (rs1'4, 10105 (rs1'3, 10106 (rs1'2, 10107 (rs1'1, 10108 (rs1'0, 10109 (false, 10110 (false, 10111 (true, 10112 (rd'4, 10113 (rd'3, 10114 (rd'2, 10115 (rd'1, 10116 (rd'0, 10117 (false, 10118 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10119 Load 10120 (LH(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10121 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10122 BitsN.fromBitstring 10123 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 10124 imm'2,imm'1,imm'0],12)))) 10125 | (imm'11, 10126 (imm'10, 10127 (imm'9, 10128 (imm'8, 10129 (imm'7, 10130 (imm'6, 10131 (imm'5, 10132 (imm'4, 10133 (imm'3, 10134 (imm'2, 10135 (imm'1, 10136 (imm'0, 10137 (rs1'4, 10138 (rs1'3, 10139 (rs1'2, 10140 (rs1'1, 10141 (rs1'0, 10142 (false, 10143 (true, 10144 (false, 10145 (rd'4, 10146 (rd'3, 10147 (rd'2, 10148 (rd'1, 10149 (rd'0, 10150 (false, 10151 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10152 Load 10153 (LW(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10154 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10155 BitsN.fromBitstring 10156 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 10157 imm'2,imm'1,imm'0],12)))) 10158 | (imm'11, 10159 (imm'10, 10160 (imm'9, 10161 (imm'8, 10162 (imm'7, 10163 (imm'6, 10164 (imm'5, 10165 (imm'4, 10166 (imm'3, 10167 (imm'2, 10168 (imm'1, 10169 (imm'0, 10170 (rs1'4, 10171 (rs1'3, 10172 (rs1'2, 10173 (rs1'1, 10174 (rs1'0, 10175 (false, 10176 (true, 10177 (true, 10178 (rd'4, 10179 (rd'3, 10180 (rd'2, 10181 (rd'1, 10182 (rd'0, 10183 (false, 10184 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10185 Load 10186 (LD(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10187 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10188 BitsN.fromBitstring 10189 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 10190 imm'2,imm'1,imm'0],12)))) 10191 | (imm'11, 10192 (imm'10, 10193 (imm'9, 10194 (imm'8, 10195 (imm'7, 10196 (imm'6, 10197 (imm'5, 10198 (imm'4, 10199 (imm'3, 10200 (imm'2, 10201 (imm'1, 10202 (imm'0, 10203 (rs1'4, 10204 (rs1'3, 10205 (rs1'2, 10206 (rs1'1, 10207 (rs1'0, 10208 (true, 10209 (false, 10210 (false, 10211 (rd'4, 10212 (rd'3, 10213 (rd'2, 10214 (rd'1, 10215 (rd'0, 10216 (false, 10217 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10218 Load 10219 (LBU(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10220 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10221 BitsN.fromBitstring 10222 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 10223 imm'2,imm'1,imm'0],12)))) 10224 | (imm'11, 10225 (imm'10, 10226 (imm'9, 10227 (imm'8, 10228 (imm'7, 10229 (imm'6, 10230 (imm'5, 10231 (imm'4, 10232 (imm'3, 10233 (imm'2, 10234 (imm'1, 10235 (imm'0, 10236 (rs1'4, 10237 (rs1'3, 10238 (rs1'2, 10239 (rs1'1, 10240 (rs1'0, 10241 (true, 10242 (false, 10243 (true, 10244 (rd'4, 10245 (rd'3, 10246 (rd'2, 10247 (rd'1, 10248 (rd'0, 10249 (false, 10250 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10251 Load 10252 (LHU(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10253 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10254 BitsN.fromBitstring 10255 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 10256 imm'2,imm'1,imm'0],12)))) 10257 | (imm'11, 10258 (imm'10, 10259 (imm'9, 10260 (imm'8, 10261 (imm'7, 10262 (imm'6, 10263 (imm'5, 10264 (imm'4, 10265 (imm'3, 10266 (imm'2, 10267 (imm'1, 10268 (imm'0, 10269 (rs1'4, 10270 (rs1'3, 10271 (rs1'2, 10272 (rs1'1, 10273 (rs1'0, 10274 (true, 10275 (true, 10276 (false, 10277 (rd'4, 10278 (rd'3, 10279 (rd'2, 10280 (rd'1, 10281 (rd'0, 10282 (false, 10283 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10284 Load 10285 (LWU(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10286 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10287 BitsN.fromBitstring 10288 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 10289 imm'2,imm'1,imm'0],12)))) 10290 | (ihi'6, 10291 (ihi'5, 10292 (ihi'4, 10293 (ihi'3, 10294 (ihi'2, 10295 (ihi'1, 10296 (ihi'0, 10297 (rs2'4, 10298 (rs2'3, 10299 (rs2'2, 10300 (rs2'1, 10301 (rs2'0, 10302 (rs1'4, 10303 (rs1'3, 10304 (rs1'2, 10305 (rs1'1, 10306 (rs1'0, 10307 (false, 10308 (false, 10309 (false, 10310 (ilo'4, 10311 (ilo'3, 10312 (ilo'2, 10313 (ilo'1, 10314 (ilo'0, 10315 (false, 10316 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10317 Store 10318 (SB(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10319 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10320 asSImm12 10321 (BitsN.fromBitstring 10322 ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), 10323 BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) 10324 | (ihi'6, 10325 (ihi'5, 10326 (ihi'4, 10327 (ihi'3, 10328 (ihi'2, 10329 (ihi'1, 10330 (ihi'0, 10331 (rs2'4, 10332 (rs2'3, 10333 (rs2'2, 10334 (rs2'1, 10335 (rs2'0, 10336 (rs1'4, 10337 (rs1'3, 10338 (rs1'2, 10339 (rs1'1, 10340 (rs1'0, 10341 (false, 10342 (false, 10343 (true, 10344 (ilo'4, 10345 (ilo'3, 10346 (ilo'2, 10347 (ilo'1, 10348 (ilo'0, 10349 (false, 10350 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10351 Store 10352 (SH(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10353 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10354 asSImm12 10355 (BitsN.fromBitstring 10356 ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), 10357 BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) 10358 | (ihi'6, 10359 (ihi'5, 10360 (ihi'4, 10361 (ihi'3, 10362 (ihi'2, 10363 (ihi'1, 10364 (ihi'0, 10365 (rs2'4, 10366 (rs2'3, 10367 (rs2'2, 10368 (rs2'1, 10369 (rs2'0, 10370 (rs1'4, 10371 (rs1'3, 10372 (rs1'2, 10373 (rs1'1, 10374 (rs1'0, 10375 (false, 10376 (true, 10377 (false, 10378 (ilo'4, 10379 (ilo'3, 10380 (ilo'2, 10381 (ilo'1, 10382 (ilo'0, 10383 (false, 10384 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10385 Store 10386 (SW(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10387 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10388 asSImm12 10389 (BitsN.fromBitstring 10390 ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), 10391 BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) 10392 | (ihi'6, 10393 (ihi'5, 10394 (ihi'4, 10395 (ihi'3, 10396 (ihi'2, 10397 (ihi'1, 10398 (ihi'0, 10399 (rs2'4, 10400 (rs2'3, 10401 (rs2'2, 10402 (rs2'1, 10403 (rs2'0, 10404 (rs1'4, 10405 (rs1'3, 10406 (rs1'2, 10407 (rs1'1, 10408 (rs1'0, 10409 (false, 10410 (true, 10411 (true, 10412 (ilo'4, 10413 (ilo'3, 10414 (ilo'2, 10415 (ilo'1, 10416 (ilo'0, 10417 (false, 10418 (true,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10419 Store 10420 (SD(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10421 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10422 asSImm12 10423 (BitsN.fromBitstring 10424 ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), 10425 BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) 10426 | (_, 10427 (_, 10428 (_, 10429 (_, 10430 (pred'3, 10431 (pred'2, 10432 (pred'1, 10433 (pred'0, 10434 (succ'3, 10435 (succ'2, 10436 (succ'1, 10437 (succ'0, 10438 (rs1'4, 10439 (rs1'3, 10440 (rs1'2, 10441 (rs1'1, 10442 (rs1'0, 10443 (false, 10444 (false, 10445 (false, 10446 (rd'4, 10447 (rd'3, 10448 (rd'2, 10449 (rd'1, 10450 (rd'0, 10451 (false, 10452 (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 10453 FENCE 10454 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10455 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10456 (BitsN.fromBitstring([pred'3,pred'2,pred'1,pred'0],4), 10457 BitsN.fromBitstring([succ'3,succ'2,succ'1,succ'0],4)))) 10458 | (imm'11, 10459 (imm'10, 10460 (imm'9, 10461 (imm'8, 10462 (imm'7, 10463 (imm'6, 10464 (imm'5, 10465 (imm'4, 10466 (imm'3, 10467 (imm'2, 10468 (imm'1, 10469 (imm'0, 10470 (rs1'4, 10471 (rs1'3, 10472 (rs1'2, 10473 (rs1'1, 10474 (rs1'0, 10475 (false, 10476 (false, 10477 (true, 10478 (rd'4, 10479 (rd'3, 10480 (rd'2, 10481 (rd'1, 10482 (rd'0, 10483 (false, 10484 (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 10485 FENCE_I 10486 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10487 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10488 BitsN.fromBitstring 10489 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 10490 imm'2,imm'1,imm'0],12))) 10491 | (rs3'4, 10492 (rs3'3, 10493 (rs3'2, 10494 (rs3'1, 10495 (rs3'0, 10496 (false, 10497 (false, 10498 (rs2'4, 10499 (rs2'3, 10500 (rs2'2, 10501 (rs2'1, 10502 (rs2'0, 10503 (rs1'4, 10504 (rs1'3, 10505 (rs1'2, 10506 (rs1'1, 10507 (rs1'0, 10508 (frm'2, 10509 (frm'1, 10510 (frm'0, 10511 (rd'4, 10512 (rd'3, 10513 (rd'2, 10514 (rd'1, 10515 (rd'0, 10516 (true, 10517 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10518 FArith 10519 (FMADD_S 10520 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10521 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10522 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10523 (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), 10524 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) 10525 | (rs3'4, 10526 (rs3'3, 10527 (rs3'2, 10528 (rs3'1, 10529 (rs3'0, 10530 (false, 10531 (false, 10532 (rs2'4, 10533 (rs2'3, 10534 (rs2'2, 10535 (rs2'1, 10536 (rs2'0, 10537 (rs1'4, 10538 (rs1'3, 10539 (rs1'2, 10540 (rs1'1, 10541 (rs1'0, 10542 (frm'2, 10543 (frm'1, 10544 (frm'0, 10545 (rd'4, 10546 (rd'3, 10547 (rd'2, 10548 (rd'1, 10549 (rd'0, 10550 (true, 10551 (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 10552 FArith 10553 (FMSUB_S 10554 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10555 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10556 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10557 (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), 10558 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) 10559 | (rs3'4, 10560 (rs3'3, 10561 (rs3'2, 10562 (rs3'1, 10563 (rs3'0, 10564 (false, 10565 (false, 10566 (rs2'4, 10567 (rs2'3, 10568 (rs2'2, 10569 (rs2'1, 10570 (rs2'0, 10571 (rs1'4, 10572 (rs1'3, 10573 (rs1'2, 10574 (rs1'1, 10575 (rs1'0, 10576 (frm'2, 10577 (frm'1, 10578 (frm'0, 10579 (rd'4, 10580 (rd'3, 10581 (rd'2, 10582 (rd'1, 10583 (rd'0, 10584 (true, 10585 (false,(false,(true,(false,(true,true))))))))))))))))))))))))))))))) => 10586 FArith 10587 (FNMSUB_S 10588 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10589 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10590 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10591 (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), 10592 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) 10593 | (rs3'4, 10594 (rs3'3, 10595 (rs3'2, 10596 (rs3'1, 10597 (rs3'0, 10598 (false, 10599 (false, 10600 (rs2'4, 10601 (rs2'3, 10602 (rs2'2, 10603 (rs2'1, 10604 (rs2'0, 10605 (rs1'4, 10606 (rs1'3, 10607 (rs1'2, 10608 (rs1'1, 10609 (rs1'0, 10610 (frm'2, 10611 (frm'1, 10612 (frm'0, 10613 (rd'4, 10614 (rd'3, 10615 (rd'2, 10616 (rd'1, 10617 (rd'0, 10618 (true, 10619 (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 10620 FArith 10621 (FNMADD_S 10622 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10623 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10624 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10625 (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), 10626 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) 10627 | (false, 10628 (false, 10629 (false, 10630 (false, 10631 (false, 10632 (false, 10633 (false, 10634 (rs2'4, 10635 (rs2'3, 10636 (rs2'2, 10637 (rs2'1, 10638 (rs2'0, 10639 (rs1'4, 10640 (rs1'3, 10641 (rs1'2, 10642 (rs1'1, 10643 (rs1'0, 10644 (frm'2, 10645 (frm'1, 10646 (frm'0, 10647 (rd'4, 10648 (rd'3, 10649 (rd'2, 10650 (rd'1, 10651 (rd'0, 10652 (true, 10653 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10654 FArith 10655 (FADD_S 10656 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10657 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10658 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10659 BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) 10660 | (false, 10661 (false, 10662 (false, 10663 (false, 10664 (true, 10665 (false, 10666 (false, 10667 (rs2'4, 10668 (rs2'3, 10669 (rs2'2, 10670 (rs2'1, 10671 (rs2'0, 10672 (rs1'4, 10673 (rs1'3, 10674 (rs1'2, 10675 (rs1'1, 10676 (rs1'0, 10677 (frm'2, 10678 (frm'1, 10679 (frm'0, 10680 (rd'4, 10681 (rd'3, 10682 (rd'2, 10683 (rd'1, 10684 (rd'0, 10685 (true, 10686 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10687 FArith 10688 (FSUB_S 10689 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10690 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10691 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10692 BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) 10693 | (false, 10694 (false, 10695 (false, 10696 (true, 10697 (false, 10698 (false, 10699 (false, 10700 (rs2'4, 10701 (rs2'3, 10702 (rs2'2, 10703 (rs2'1, 10704 (rs2'0, 10705 (rs1'4, 10706 (rs1'3, 10707 (rs1'2, 10708 (rs1'1, 10709 (rs1'0, 10710 (frm'2, 10711 (frm'1, 10712 (frm'0, 10713 (rd'4, 10714 (rd'3, 10715 (rd'2, 10716 (rd'1, 10717 (rd'0, 10718 (true, 10719 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10720 FArith 10721 (FMUL_S 10722 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10723 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10724 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10725 BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) 10726 | (false, 10727 (false, 10728 (false, 10729 (true, 10730 (true, 10731 (false, 10732 (false, 10733 (rs2'4, 10734 (rs2'3, 10735 (rs2'2, 10736 (rs2'1, 10737 (rs2'0, 10738 (rs1'4, 10739 (rs1'3, 10740 (rs1'2, 10741 (rs1'1, 10742 (rs1'0, 10743 (frm'2, 10744 (frm'1, 10745 (frm'0, 10746 (rd'4, 10747 (rd'3, 10748 (rd'2, 10749 (rd'1, 10750 (rd'0, 10751 (true, 10752 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10753 FArith 10754 (FDIV_S 10755 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10756 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10757 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 10758 BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) 10759 | (false, 10760 (true, 10761 (false, 10762 (true, 10763 (true, 10764 (false, 10765 (false, 10766 (false, 10767 (false, 10768 (false, 10769 (false, 10770 (false, 10771 (rs1'4, 10772 (rs1'3, 10773 (rs1'2, 10774 (rs1'1, 10775 (rs1'0, 10776 (frm'2, 10777 (frm'1, 10778 (frm'0, 10779 (rd'4, 10780 (rd'3, 10781 (rd'2, 10782 (rd'1, 10783 (rd'0, 10784 (true, 10785 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10786 FArith 10787 (FSQRT_S 10788 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10789 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10790 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 10791 | (false, 10792 (false, 10793 (true, 10794 (false, 10795 (true, 10796 (false, 10797 (false, 10798 (rs2'4, 10799 (rs2'3, 10800 (rs2'2, 10801 (rs2'1, 10802 (rs2'0, 10803 (rs1'4, 10804 (rs1'3, 10805 (rs1'2, 10806 (rs1'1, 10807 (rs1'0, 10808 (false, 10809 (false, 10810 (false, 10811 (rd'4, 10812 (rd'3, 10813 (rd'2, 10814 (rd'1, 10815 (rd'0, 10816 (true, 10817 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10818 FArith 10819 (FMIN_S 10820 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10821 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10822 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 10823 | (false, 10824 (false, 10825 (true, 10826 (false, 10827 (true, 10828 (false, 10829 (false, 10830 (rs2'4, 10831 (rs2'3, 10832 (rs2'2, 10833 (rs2'1, 10834 (rs2'0, 10835 (rs1'4, 10836 (rs1'3, 10837 (rs1'2, 10838 (rs1'1, 10839 (rs1'0, 10840 (false, 10841 (false, 10842 (true, 10843 (rd'4, 10844 (rd'3, 10845 (rd'2, 10846 (rd'1, 10847 (rd'0, 10848 (true, 10849 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10850 FArith 10851 (FMAX_S 10852 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10853 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10854 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 10855 | (true, 10856 (false, 10857 (true, 10858 (false, 10859 (false, 10860 (false, 10861 (false, 10862 (rs2'4, 10863 (rs2'3, 10864 (rs2'2, 10865 (rs2'1, 10866 (rs2'0, 10867 (rs1'4, 10868 (rs1'3, 10869 (rs1'2, 10870 (rs1'1, 10871 (rs1'0, 10872 (false, 10873 (true, 10874 (false, 10875 (rd'4, 10876 (rd'3, 10877 (rd'2, 10878 (rd'1, 10879 (rd'0, 10880 (true, 10881 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10882 FArith 10883 (FEQ_S 10884 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10885 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10886 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 10887 | (true, 10888 (false, 10889 (true, 10890 (false, 10891 (false, 10892 (false, 10893 (false, 10894 (rs2'4, 10895 (rs2'3, 10896 (rs2'2, 10897 (rs2'1, 10898 (rs2'0, 10899 (rs1'4, 10900 (rs1'3, 10901 (rs1'2, 10902 (rs1'1, 10903 (rs1'0, 10904 (false, 10905 (false, 10906 (true, 10907 (rd'4, 10908 (rd'3, 10909 (rd'2, 10910 (rd'1, 10911 (rd'0, 10912 (true, 10913 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10914 FArith 10915 (FLT_S 10916 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10917 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10918 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 10919 | (true, 10920 (false, 10921 (true, 10922 (false, 10923 (false, 10924 (false, 10925 (false, 10926 (rs2'4, 10927 (rs2'3, 10928 (rs2'2, 10929 (rs2'1, 10930 (rs2'0, 10931 (rs1'4, 10932 (rs1'3, 10933 (rs1'2, 10934 (rs1'1, 10935 (rs1'0, 10936 (false, 10937 (false, 10938 (false, 10939 (rd'4, 10940 (rd'3, 10941 (rd'2, 10942 (rd'1, 10943 (rd'0, 10944 (true, 10945 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10946 FArith 10947 (FLE_S 10948 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10949 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10950 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 10951 | (false, 10952 (false, 10953 (true, 10954 (false, 10955 (false, 10956 (false, 10957 (false, 10958 (rs2'4, 10959 (rs2'3, 10960 (rs2'2, 10961 (rs2'1, 10962 (rs2'0, 10963 (rs1'4, 10964 (rs1'3, 10965 (rs1'2, 10966 (rs1'1, 10967 (rs1'0, 10968 (false, 10969 (false, 10970 (false, 10971 (rd'4, 10972 (rd'3, 10973 (rd'2, 10974 (rd'1, 10975 (rd'0, 10976 (true, 10977 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 10978 FConv 10979 (FSGNJ_S 10980 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 10981 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 10982 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 10983 | (false, 10984 (false, 10985 (true, 10986 (false, 10987 (false, 10988 (false, 10989 (false, 10990 (rs2'4, 10991 (rs2'3, 10992 (rs2'2, 10993 (rs2'1, 10994 (rs2'0, 10995 (rs1'4, 10996 (rs1'3, 10997 (rs1'2, 10998 (rs1'1, 10999 (rs1'0, 11000 (false, 11001 (false, 11002 (true, 11003 (rd'4, 11004 (rd'3, 11005 (rd'2, 11006 (rd'1, 11007 (rd'0, 11008 (true, 11009 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11010 FConv 11011 (FSGNJN_S 11012 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11013 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11014 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11015 | (false, 11016 (false, 11017 (true, 11018 (false, 11019 (false, 11020 (false, 11021 (false, 11022 (rs2'4, 11023 (rs2'3, 11024 (rs2'2, 11025 (rs2'1, 11026 (rs2'0, 11027 (rs1'4, 11028 (rs1'3, 11029 (rs1'2, 11030 (rs1'1, 11031 (rs1'0, 11032 (false, 11033 (true, 11034 (false, 11035 (rd'4, 11036 (rd'3, 11037 (rd'2, 11038 (rd'1, 11039 (rd'0, 11040 (true, 11041 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11042 FConv 11043 (FSGNJX_S 11044 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11045 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11046 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11047 | (true, 11048 (true, 11049 (false, 11050 (false, 11051 (false, 11052 (false, 11053 (false, 11054 (false, 11055 (false, 11056 (false, 11057 (false, 11058 (false, 11059 (rs1'4, 11060 (rs1'3, 11061 (rs1'2, 11062 (rs1'1, 11063 (rs1'0, 11064 (frm'2, 11065 (frm'1, 11066 (frm'0, 11067 (rd'4, 11068 (rd'3, 11069 (rd'2, 11070 (rd'1, 11071 (rd'0, 11072 (true, 11073 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11074 FConv 11075 (FCVT_W_S 11076 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11077 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11078 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11079 | (true, 11080 (true, 11081 (false, 11082 (false, 11083 (false, 11084 (false, 11085 (false, 11086 (false, 11087 (false, 11088 (false, 11089 (false, 11090 (true, 11091 (rs1'4, 11092 (rs1'3, 11093 (rs1'2, 11094 (rs1'1, 11095 (rs1'0, 11096 (frm'2, 11097 (frm'1, 11098 (frm'0, 11099 (rd'4, 11100 (rd'3, 11101 (rd'2, 11102 (rd'1, 11103 (rd'0, 11104 (true, 11105 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11106 FConv 11107 (FCVT_WU_S 11108 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11109 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11110 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11111 | (true, 11112 (true, 11113 (true, 11114 (false, 11115 (false, 11116 (false, 11117 (false, 11118 (false, 11119 (false, 11120 (false, 11121 (false, 11122 (false, 11123 (rs1'4, 11124 (rs1'3, 11125 (rs1'2, 11126 (rs1'1, 11127 (rs1'0, 11128 (false, 11129 (false, 11130 (false, 11131 (rd'4, 11132 (rd'3, 11133 (rd'2, 11134 (rd'1, 11135 (rd'0, 11136 (true, 11137 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11138 FConv 11139 (FMV_X_S 11140 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11141 BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) 11142 | (true, 11143 (true, 11144 (true, 11145 (false, 11146 (false, 11147 (false, 11148 (false, 11149 (false, 11150 (false, 11151 (false, 11152 (false, 11153 (false, 11154 (rs1'4, 11155 (rs1'3, 11156 (rs1'2, 11157 (rs1'1, 11158 (rs1'0, 11159 (false, 11160 (false, 11161 (true, 11162 (rd'4, 11163 (rd'3, 11164 (rd'2, 11165 (rd'1, 11166 (rd'0, 11167 (true, 11168 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11169 FConv 11170 (FCLASS_S 11171 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11172 BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) 11173 | (true, 11174 (true, 11175 (false, 11176 (true, 11177 (false, 11178 (false, 11179 (false, 11180 (false, 11181 (false, 11182 (false, 11183 (false, 11184 (false, 11185 (rs1'4, 11186 (rs1'3, 11187 (rs1'2, 11188 (rs1'1, 11189 (rs1'0, 11190 (frm'2, 11191 (frm'1, 11192 (frm'0, 11193 (rd'4, 11194 (rd'3, 11195 (rd'2, 11196 (rd'1, 11197 (rd'0, 11198 (true, 11199 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11200 FConv 11201 (FCVT_S_W 11202 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11203 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11204 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11205 | (true, 11206 (true, 11207 (false, 11208 (true, 11209 (false, 11210 (false, 11211 (false, 11212 (false, 11213 (false, 11214 (false, 11215 (false, 11216 (true, 11217 (rs1'4, 11218 (rs1'3, 11219 (rs1'2, 11220 (rs1'1, 11221 (rs1'0, 11222 (frm'2, 11223 (frm'1, 11224 (frm'0, 11225 (rd'4, 11226 (rd'3, 11227 (rd'2, 11228 (rd'1, 11229 (rd'0, 11230 (true, 11231 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11232 FConv 11233 (FCVT_S_WU 11234 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11235 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11236 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11237 | (true, 11238 (true, 11239 (true, 11240 (true, 11241 (false, 11242 (false, 11243 (false, 11244 (false, 11245 (false, 11246 (false, 11247 (false, 11248 (false, 11249 (rs1'4, 11250 (rs1'3, 11251 (rs1'2, 11252 (rs1'1, 11253 (rs1'0, 11254 (false, 11255 (false, 11256 (false, 11257 (rd'4, 11258 (rd'3, 11259 (rd'2, 11260 (rd'1, 11261 (rd'0, 11262 (true, 11263 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11264 FConv 11265 (FMV_S_X 11266 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11267 BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) 11268 | (rs3'4, 11269 (rs3'3, 11270 (rs3'2, 11271 (rs3'1, 11272 (rs3'0, 11273 (false, 11274 (true, 11275 (rs2'4, 11276 (rs2'3, 11277 (rs2'2, 11278 (rs2'1, 11279 (rs2'0, 11280 (rs1'4, 11281 (rs1'3, 11282 (rs1'2, 11283 (rs1'1, 11284 (rs1'0, 11285 (frm'2, 11286 (frm'1, 11287 (frm'0, 11288 (rd'4, 11289 (rd'3, 11290 (rd'2, 11291 (rd'1, 11292 (rd'0, 11293 (true, 11294 (false,(false,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11295 FArith 11296 (FMADD_D 11297 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11298 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11299 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 11300 (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), 11301 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) 11302 | (rs3'4, 11303 (rs3'3, 11304 (rs3'2, 11305 (rs3'1, 11306 (rs3'0, 11307 (false, 11308 (true, 11309 (rs2'4, 11310 (rs2'3, 11311 (rs2'2, 11312 (rs2'1, 11313 (rs2'0, 11314 (rs1'4, 11315 (rs1'3, 11316 (rs1'2, 11317 (rs1'1, 11318 (rs1'0, 11319 (frm'2, 11320 (frm'1, 11321 (frm'0, 11322 (rd'4, 11323 (rd'3, 11324 (rd'2, 11325 (rd'1, 11326 (rd'0, 11327 (true, 11328 (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 11329 FArith 11330 (FMSUB_D 11331 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11332 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11333 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 11334 (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), 11335 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) 11336 | (rs3'4, 11337 (rs3'3, 11338 (rs3'2, 11339 (rs3'1, 11340 (rs3'0, 11341 (false, 11342 (true, 11343 (rs2'4, 11344 (rs2'3, 11345 (rs2'2, 11346 (rs2'1, 11347 (rs2'0, 11348 (rs1'4, 11349 (rs1'3, 11350 (rs1'2, 11351 (rs1'1, 11352 (rs1'0, 11353 (frm'2, 11354 (frm'1, 11355 (frm'0, 11356 (rd'4, 11357 (rd'3, 11358 (rd'2, 11359 (rd'1, 11360 (rd'0, 11361 (true, 11362 (false,(false,(true,(false,(true,true))))))))))))))))))))))))))))))) => 11363 FArith 11364 (FNMSUB_D 11365 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11366 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11367 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 11368 (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), 11369 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) 11370 | (rs3'4, 11371 (rs3'3, 11372 (rs3'2, 11373 (rs3'1, 11374 (rs3'0, 11375 (false, 11376 (true, 11377 (rs2'4, 11378 (rs2'3, 11379 (rs2'2, 11380 (rs2'1, 11381 (rs2'0, 11382 (rs1'4, 11383 (rs1'3, 11384 (rs1'2, 11385 (rs1'1, 11386 (rs1'0, 11387 (frm'2, 11388 (frm'1, 11389 (frm'0, 11390 (rd'4, 11391 (rd'3, 11392 (rd'2, 11393 (rd'1, 11394 (rd'0, 11395 (true, 11396 (false,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 11397 FArith 11398 (FNMADD_D 11399 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11400 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11401 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 11402 (BitsN.fromBitstring([rs3'4,rs3'3,rs3'2,rs3'1,rs3'0],5), 11403 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))))) 11404 | (false, 11405 (false, 11406 (false, 11407 (false, 11408 (false, 11409 (false, 11410 (true, 11411 (rs2'4, 11412 (rs2'3, 11413 (rs2'2, 11414 (rs2'1, 11415 (rs2'0, 11416 (rs1'4, 11417 (rs1'3, 11418 (rs1'2, 11419 (rs1'1, 11420 (rs1'0, 11421 (frm'2, 11422 (frm'1, 11423 (frm'0, 11424 (rd'4, 11425 (rd'3, 11426 (rd'2, 11427 (rd'1, 11428 (rd'0, 11429 (true, 11430 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11431 FArith 11432 (FADD_D 11433 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11434 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11435 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 11436 BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) 11437 | (false, 11438 (false, 11439 (false, 11440 (false, 11441 (true, 11442 (false, 11443 (true, 11444 (rs2'4, 11445 (rs2'3, 11446 (rs2'2, 11447 (rs2'1, 11448 (rs2'0, 11449 (rs1'4, 11450 (rs1'3, 11451 (rs1'2, 11452 (rs1'1, 11453 (rs1'0, 11454 (frm'2, 11455 (frm'1, 11456 (frm'0, 11457 (rd'4, 11458 (rd'3, 11459 (rd'2, 11460 (rd'1, 11461 (rd'0, 11462 (true, 11463 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11464 FArith 11465 (FSUB_D 11466 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11467 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11468 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 11469 BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) 11470 | (false, 11471 (false, 11472 (false, 11473 (true, 11474 (false, 11475 (false, 11476 (true, 11477 (rs2'4, 11478 (rs2'3, 11479 (rs2'2, 11480 (rs2'1, 11481 (rs2'0, 11482 (rs1'4, 11483 (rs1'3, 11484 (rs1'2, 11485 (rs1'1, 11486 (rs1'0, 11487 (frm'2, 11488 (frm'1, 11489 (frm'0, 11490 (rd'4, 11491 (rd'3, 11492 (rd'2, 11493 (rd'1, 11494 (rd'0, 11495 (true, 11496 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11497 FArith 11498 (FMUL_D 11499 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11500 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11501 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 11502 BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) 11503 | (false, 11504 (false, 11505 (false, 11506 (true, 11507 (true, 11508 (false, 11509 (true, 11510 (rs2'4, 11511 (rs2'3, 11512 (rs2'2, 11513 (rs2'1, 11514 (rs2'0, 11515 (rs1'4, 11516 (rs1'3, 11517 (rs1'2, 11518 (rs1'1, 11519 (rs1'0, 11520 (frm'2, 11521 (frm'1, 11522 (frm'0, 11523 (rd'4, 11524 (rd'3, 11525 (rd'2, 11526 (rd'1, 11527 (rd'0, 11528 (true, 11529 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11530 FArith 11531 (FDIV_D 11532 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11533 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11534 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 11535 BitsN.fromBitstring([frm'2,frm'1,frm'0],3))))) 11536 | (false, 11537 (true, 11538 (false, 11539 (true, 11540 (true, 11541 (false, 11542 (true, 11543 (false, 11544 (false, 11545 (false, 11546 (false, 11547 (false, 11548 (rs1'4, 11549 (rs1'3, 11550 (rs1'2, 11551 (rs1'1, 11552 (rs1'0, 11553 (frm'2, 11554 (frm'1, 11555 (frm'0, 11556 (rd'4, 11557 (rd'3, 11558 (rd'2, 11559 (rd'1, 11560 (rd'0, 11561 (true, 11562 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11563 FArith 11564 (FSQRT_D 11565 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11566 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11567 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11568 | (false, 11569 (false, 11570 (true, 11571 (false, 11572 (true, 11573 (false, 11574 (true, 11575 (rs2'4, 11576 (rs2'3, 11577 (rs2'2, 11578 (rs2'1, 11579 (rs2'0, 11580 (rs1'4, 11581 (rs1'3, 11582 (rs1'2, 11583 (rs1'1, 11584 (rs1'0, 11585 (false, 11586 (false, 11587 (false, 11588 (rd'4, 11589 (rd'3, 11590 (rd'2, 11591 (rd'1, 11592 (rd'0, 11593 (true, 11594 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11595 FArith 11596 (FMIN_D 11597 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11598 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11599 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11600 | (false, 11601 (false, 11602 (true, 11603 (false, 11604 (true, 11605 (false, 11606 (true, 11607 (rs2'4, 11608 (rs2'3, 11609 (rs2'2, 11610 (rs2'1, 11611 (rs2'0, 11612 (rs1'4, 11613 (rs1'3, 11614 (rs1'2, 11615 (rs1'1, 11616 (rs1'0, 11617 (false, 11618 (false, 11619 (true, 11620 (rd'4, 11621 (rd'3, 11622 (rd'2, 11623 (rd'1, 11624 (rd'0, 11625 (true, 11626 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11627 FArith 11628 (FMAX_D 11629 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11630 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11631 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11632 | (true, 11633 (false, 11634 (true, 11635 (false, 11636 (false, 11637 (false, 11638 (true, 11639 (rs2'4, 11640 (rs2'3, 11641 (rs2'2, 11642 (rs2'1, 11643 (rs2'0, 11644 (rs1'4, 11645 (rs1'3, 11646 (rs1'2, 11647 (rs1'1, 11648 (rs1'0, 11649 (false, 11650 (true, 11651 (false, 11652 (rd'4, 11653 (rd'3, 11654 (rd'2, 11655 (rd'1, 11656 (rd'0, 11657 (true, 11658 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11659 FArith 11660 (FEQ_D 11661 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11662 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11663 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11664 | (true, 11665 (false, 11666 (true, 11667 (false, 11668 (false, 11669 (false, 11670 (true, 11671 (rs2'4, 11672 (rs2'3, 11673 (rs2'2, 11674 (rs2'1, 11675 (rs2'0, 11676 (rs1'4, 11677 (rs1'3, 11678 (rs1'2, 11679 (rs1'1, 11680 (rs1'0, 11681 (false, 11682 (false, 11683 (true, 11684 (rd'4, 11685 (rd'3, 11686 (rd'2, 11687 (rd'1, 11688 (rd'0, 11689 (true, 11690 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11691 FArith 11692 (FLT_D 11693 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11694 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11695 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11696 | (true, 11697 (false, 11698 (true, 11699 (false, 11700 (false, 11701 (false, 11702 (true, 11703 (rs2'4, 11704 (rs2'3, 11705 (rs2'2, 11706 (rs2'1, 11707 (rs2'0, 11708 (rs1'4, 11709 (rs1'3, 11710 (rs1'2, 11711 (rs1'1, 11712 (rs1'0, 11713 (false, 11714 (false, 11715 (false, 11716 (rd'4, 11717 (rd'3, 11718 (rd'2, 11719 (rd'1, 11720 (rd'0, 11721 (true, 11722 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11723 FArith 11724 (FLE_D 11725 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11726 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11727 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11728 | (false, 11729 (false, 11730 (true, 11731 (false, 11732 (false, 11733 (false, 11734 (true, 11735 (rs2'4, 11736 (rs2'3, 11737 (rs2'2, 11738 (rs2'1, 11739 (rs2'0, 11740 (rs1'4, 11741 (rs1'3, 11742 (rs1'2, 11743 (rs1'1, 11744 (rs1'0, 11745 (false, 11746 (false, 11747 (false, 11748 (rd'4, 11749 (rd'3, 11750 (rd'2, 11751 (rd'1, 11752 (rd'0, 11753 (true, 11754 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11755 FConv 11756 (FSGNJ_D 11757 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11758 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11759 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11760 | (false, 11761 (false, 11762 (true, 11763 (false, 11764 (false, 11765 (false, 11766 (true, 11767 (rs2'4, 11768 (rs2'3, 11769 (rs2'2, 11770 (rs2'1, 11771 (rs2'0, 11772 (rs1'4, 11773 (rs1'3, 11774 (rs1'2, 11775 (rs1'1, 11776 (rs1'0, 11777 (false, 11778 (false, 11779 (true, 11780 (rd'4, 11781 (rd'3, 11782 (rd'2, 11783 (rd'1, 11784 (rd'0, 11785 (true, 11786 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11787 FConv 11788 (FSGNJN_D 11789 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11790 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11791 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11792 | (false, 11793 (false, 11794 (true, 11795 (false, 11796 (false, 11797 (false, 11798 (true, 11799 (rs2'4, 11800 (rs2'3, 11801 (rs2'2, 11802 (rs2'1, 11803 (rs2'0, 11804 (rs1'4, 11805 (rs1'3, 11806 (rs1'2, 11807 (rs1'1, 11808 (rs1'0, 11809 (false, 11810 (true, 11811 (false, 11812 (rd'4, 11813 (rd'3, 11814 (rd'2, 11815 (rd'1, 11816 (rd'0, 11817 (true, 11818 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11819 FConv 11820 (FSGNJX_D 11821 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11822 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11823 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))) 11824 | (true, 11825 (true, 11826 (false, 11827 (false, 11828 (false, 11829 (false, 11830 (true, 11831 (false, 11832 (false, 11833 (false, 11834 (false, 11835 (false, 11836 (rs1'4, 11837 (rs1'3, 11838 (rs1'2, 11839 (rs1'1, 11840 (rs1'0, 11841 (frm'2, 11842 (frm'1, 11843 (frm'0, 11844 (rd'4, 11845 (rd'3, 11846 (rd'2, 11847 (rd'1, 11848 (rd'0, 11849 (true, 11850 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11851 FConv 11852 (FCVT_W_D 11853 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11854 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11855 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11856 | (true, 11857 (true, 11858 (false, 11859 (false, 11860 (false, 11861 (false, 11862 (true, 11863 (false, 11864 (false, 11865 (false, 11866 (false, 11867 (true, 11868 (rs1'4, 11869 (rs1'3, 11870 (rs1'2, 11871 (rs1'1, 11872 (rs1'0, 11873 (frm'2, 11874 (frm'1, 11875 (frm'0, 11876 (rd'4, 11877 (rd'3, 11878 (rd'2, 11879 (rd'1, 11880 (rd'0, 11881 (true, 11882 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11883 FConv 11884 (FCVT_WU_D 11885 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11886 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11887 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11888 | (true, 11889 (true, 11890 (true, 11891 (false, 11892 (false, 11893 (false, 11894 (true, 11895 (false, 11896 (false, 11897 (false, 11898 (false, 11899 (false, 11900 (rs1'4, 11901 (rs1'3, 11902 (rs1'2, 11903 (rs1'1, 11904 (rs1'0, 11905 (false, 11906 (false, 11907 (true, 11908 (rd'4, 11909 (rd'3, 11910 (rd'2, 11911 (rd'1, 11912 (rd'0, 11913 (true, 11914 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11915 FConv 11916 (FCLASS_D 11917 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11918 BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) 11919 | (true, 11920 (true, 11921 (false, 11922 (true, 11923 (false, 11924 (false, 11925 (true, 11926 (false, 11927 (false, 11928 (false, 11929 (false, 11930 (false, 11931 (rs1'4, 11932 (rs1'3, 11933 (rs1'2, 11934 (rs1'1, 11935 (rs1'0, 11936 (frm'2, 11937 (frm'1, 11938 (frm'0, 11939 (rd'4, 11940 (rd'3, 11941 (rd'2, 11942 (rd'1, 11943 (rd'0, 11944 (true, 11945 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11946 FConv 11947 (FCVT_D_W 11948 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11949 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11950 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11951 | (true, 11952 (true, 11953 (false, 11954 (true, 11955 (false, 11956 (false, 11957 (true, 11958 (false, 11959 (false, 11960 (false, 11961 (false, 11962 (true, 11963 (rs1'4, 11964 (rs1'3, 11965 (rs1'2, 11966 (rs1'1, 11967 (rs1'0, 11968 (frm'2, 11969 (frm'1, 11970 (frm'0, 11971 (rd'4, 11972 (rd'3, 11973 (rd'2, 11974 (rd'1, 11975 (rd'0, 11976 (true, 11977 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 11978 FConv 11979 (FCVT_D_WU 11980 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 11981 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 11982 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 11983 | (true, 11984 (true, 11985 (false, 11986 (false, 11987 (false, 11988 (false, 11989 (false, 11990 (false, 11991 (false, 11992 (false, 11993 (true, 11994 (false, 11995 (rs1'4, 11996 (rs1'3, 11997 (rs1'2, 11998 (rs1'1, 11999 (rs1'0, 12000 (frm'2, 12001 (frm'1, 12002 (frm'0, 12003 (rd'4, 12004 (rd'3, 12005 (rd'2, 12006 (rd'1, 12007 (rd'0, 12008 (true, 12009 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12010 FConv 12011 (FCVT_L_S 12012 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12013 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12014 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12015 | (true, 12016 (true, 12017 (false, 12018 (false, 12019 (false, 12020 (false, 12021 (false, 12022 (false, 12023 (false, 12024 (false, 12025 (true, 12026 (true, 12027 (rs1'4, 12028 (rs1'3, 12029 (rs1'2, 12030 (rs1'1, 12031 (rs1'0, 12032 (frm'2, 12033 (frm'1, 12034 (frm'0, 12035 (rd'4, 12036 (rd'3, 12037 (rd'2, 12038 (rd'1, 12039 (rd'0, 12040 (true, 12041 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12042 FConv 12043 (FCVT_LU_S 12044 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12045 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12046 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12047 | (true, 12048 (true, 12049 (false, 12050 (true, 12051 (false, 12052 (false, 12053 (false, 12054 (false, 12055 (false, 12056 (false, 12057 (true, 12058 (false, 12059 (rs1'4, 12060 (rs1'3, 12061 (rs1'2, 12062 (rs1'1, 12063 (rs1'0, 12064 (frm'2, 12065 (frm'1, 12066 (frm'0, 12067 (rd'4, 12068 (rd'3, 12069 (rd'2, 12070 (rd'1, 12071 (rd'0, 12072 (true, 12073 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12074 FConv 12075 (FCVT_S_L 12076 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12077 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12078 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12079 | (true, 12080 (true, 12081 (false, 12082 (true, 12083 (false, 12084 (false, 12085 (false, 12086 (false, 12087 (false, 12088 (false, 12089 (true, 12090 (true, 12091 (rs1'4, 12092 (rs1'3, 12093 (rs1'2, 12094 (rs1'1, 12095 (rs1'0, 12096 (frm'2, 12097 (frm'1, 12098 (frm'0, 12099 (rd'4, 12100 (rd'3, 12101 (rd'2, 12102 (rd'1, 12103 (rd'0, 12104 (true, 12105 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12106 FConv 12107 (FCVT_S_LU 12108 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12109 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12110 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12111 | (true, 12112 (true, 12113 (false, 12114 (false, 12115 (false, 12116 (false, 12117 (true, 12118 (false, 12119 (false, 12120 (false, 12121 (true, 12122 (false, 12123 (rs1'4, 12124 (rs1'3, 12125 (rs1'2, 12126 (rs1'1, 12127 (rs1'0, 12128 (frm'2, 12129 (frm'1, 12130 (frm'0, 12131 (rd'4, 12132 (rd'3, 12133 (rd'2, 12134 (rd'1, 12135 (rd'0, 12136 (true, 12137 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12138 FConv 12139 (FCVT_L_D 12140 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12141 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12142 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12143 | (true, 12144 (true, 12145 (false, 12146 (false, 12147 (false, 12148 (false, 12149 (true, 12150 (false, 12151 (false, 12152 (false, 12153 (true, 12154 (true, 12155 (rs1'4, 12156 (rs1'3, 12157 (rs1'2, 12158 (rs1'1, 12159 (rs1'0, 12160 (frm'2, 12161 (frm'1, 12162 (frm'0, 12163 (rd'4, 12164 (rd'3, 12165 (rd'2, 12166 (rd'1, 12167 (rd'0, 12168 (true, 12169 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12170 FConv 12171 (FCVT_LU_D 12172 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12173 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12174 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12175 | (true, 12176 (true, 12177 (false, 12178 (true, 12179 (false, 12180 (false, 12181 (true, 12182 (false, 12183 (false, 12184 (false, 12185 (true, 12186 (false, 12187 (rs1'4, 12188 (rs1'3, 12189 (rs1'2, 12190 (rs1'1, 12191 (rs1'0, 12192 (frm'2, 12193 (frm'1, 12194 (frm'0, 12195 (rd'4, 12196 (rd'3, 12197 (rd'2, 12198 (rd'1, 12199 (rd'0, 12200 (true, 12201 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12202 FConv 12203 (FCVT_D_L 12204 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12205 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12206 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12207 | (true, 12208 (true, 12209 (false, 12210 (true, 12211 (false, 12212 (false, 12213 (true, 12214 (false, 12215 (false, 12216 (false, 12217 (true, 12218 (true, 12219 (rs1'4, 12220 (rs1'3, 12221 (rs1'2, 12222 (rs1'1, 12223 (rs1'0, 12224 (frm'2, 12225 (frm'1, 12226 (frm'0, 12227 (rd'4, 12228 (rd'3, 12229 (rd'2, 12230 (rd'1, 12231 (rd'0, 12232 (true, 12233 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12234 FConv 12235 (FCVT_D_LU 12236 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12237 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12238 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12239 | (true, 12240 (true, 12241 (true, 12242 (false, 12243 (false, 12244 (false, 12245 (true, 12246 (false, 12247 (false, 12248 (false, 12249 (false, 12250 (false, 12251 (rs1'4, 12252 (rs1'3, 12253 (rs1'2, 12254 (rs1'1, 12255 (rs1'0, 12256 (false, 12257 (false, 12258 (false, 12259 (rd'4, 12260 (rd'3, 12261 (rd'2, 12262 (rd'1, 12263 (rd'0, 12264 (true, 12265 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12266 FConv 12267 (FMV_X_D 12268 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12269 BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) 12270 | (true, 12271 (true, 12272 (true, 12273 (true, 12274 (false, 12275 (false, 12276 (true, 12277 (false, 12278 (false, 12279 (false, 12280 (false, 12281 (false, 12282 (rs1'4, 12283 (rs1'3, 12284 (rs1'2, 12285 (rs1'1, 12286 (rs1'0, 12287 (false, 12288 (false, 12289 (false, 12290 (rd'4, 12291 (rd'3, 12292 (rd'2, 12293 (rd'1, 12294 (rd'0, 12295 (true, 12296 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12297 FConv 12298 (FMV_D_X 12299 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12300 BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) 12301 | (false, 12302 (true, 12303 (false, 12304 (false, 12305 (false, 12306 (false, 12307 (false, 12308 (false, 12309 (false, 12310 (false, 12311 (false, 12312 (true, 12313 (rs1'4, 12314 (rs1'3, 12315 (rs1'2, 12316 (rs1'1, 12317 (rs1'0, 12318 (frm'2, 12319 (frm'1, 12320 (frm'0, 12321 (rd'4, 12322 (rd'3, 12323 (rd'2, 12324 (rd'1, 12325 (rd'0, 12326 (true, 12327 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12328 FConv 12329 (FCVT_S_D 12330 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12331 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12332 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12333 | (false, 12334 (true, 12335 (false, 12336 (false, 12337 (false, 12338 (false, 12339 (true, 12340 (false, 12341 (false, 12342 (false, 12343 (false, 12344 (false, 12345 (rs1'4, 12346 (rs1'3, 12347 (rs1'2, 12348 (rs1'1, 12349 (rs1'0, 12350 (frm'2, 12351 (frm'1, 12352 (frm'0, 12353 (rd'4, 12354 (rd'3, 12355 (rd'2, 12356 (rd'1, 12357 (rd'0, 12358 (true, 12359 (false,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 12360 FConv 12361 (FCVT_D_S 12362 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12363 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12364 BitsN.fromBitstring([frm'2,frm'1,frm'0],3)))) 12365 | (imm'11, 12366 (imm'10, 12367 (imm'9, 12368 (imm'8, 12369 (imm'7, 12370 (imm'6, 12371 (imm'5, 12372 (imm'4, 12373 (imm'3, 12374 (imm'2, 12375 (imm'1, 12376 (imm'0, 12377 (rs1'4, 12378 (rs1'3, 12379 (rs1'2, 12380 (rs1'1, 12381 (rs1'0, 12382 (false, 12383 (true, 12384 (false, 12385 (rd'4, 12386 (rd'3, 12387 (rd'2, 12388 (rd'1, 12389 (rd'0, 12390 (false, 12391 (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 12392 FPLoad 12393 (FLW(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12394 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12395 BitsN.fromBitstring 12396 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 12397 imm'2,imm'1,imm'0],12)))) 12398 | (imm'11, 12399 (imm'10, 12400 (imm'9, 12401 (imm'8, 12402 (imm'7, 12403 (imm'6, 12404 (imm'5, 12405 (imm'4, 12406 (imm'3, 12407 (imm'2, 12408 (imm'1, 12409 (imm'0, 12410 (rs1'4, 12411 (rs1'3, 12412 (rs1'2, 12413 (rs1'1, 12414 (rs1'0, 12415 (false, 12416 (true, 12417 (true, 12418 (rd'4, 12419 (rd'3, 12420 (rd'2, 12421 (rd'1, 12422 (rd'0, 12423 (false, 12424 (false,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 12425 FPLoad 12426 (FLD(BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12427 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12428 BitsN.fromBitstring 12429 ([imm'11,imm'10,imm'9,imm'8,imm'7,imm'6,imm'5,imm'4,imm'3, 12430 imm'2,imm'1,imm'0],12)))) 12431 | (ihi'6, 12432 (ihi'5, 12433 (ihi'4, 12434 (ihi'3, 12435 (ihi'2, 12436 (ihi'1, 12437 (ihi'0, 12438 (rs2'4, 12439 (rs2'3, 12440 (rs2'2, 12441 (rs2'1, 12442 (rs2'0, 12443 (rs1'4, 12444 (rs1'3, 12445 (rs1'2, 12446 (rs1'1, 12447 (rs1'0, 12448 (false, 12449 (true, 12450 (false, 12451 (ilo'4, 12452 (ilo'3, 12453 (ilo'2, 12454 (ilo'1, 12455 (ilo'0, 12456 (false, 12457 (true,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 12458 FPStore 12459 (FSW(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12460 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 12461 asSImm12 12462 (BitsN.fromBitstring 12463 ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), 12464 BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) 12465 | (ihi'6, 12466 (ihi'5, 12467 (ihi'4, 12468 (ihi'3, 12469 (ihi'2, 12470 (ihi'1, 12471 (ihi'0, 12472 (rs2'4, 12473 (rs2'3, 12474 (rs2'2, 12475 (rs2'1, 12476 (rs2'0, 12477 (rs1'4, 12478 (rs1'3, 12479 (rs1'2, 12480 (rs1'1, 12481 (rs1'0, 12482 (false, 12483 (true, 12484 (true, 12485 (ilo'4, 12486 (ilo'3, 12487 (ilo'2, 12488 (ilo'1, 12489 (ilo'0, 12490 (false, 12491 (true,(false,(false,(true,(true,true))))))))))))))))))))))))))))))) => 12492 FPStore 12493 (FSD(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12494 (BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5), 12495 asSImm12 12496 (BitsN.fromBitstring 12497 ([ihi'6,ihi'5,ihi'4,ihi'3,ihi'2,ihi'1,ihi'0],7), 12498 BitsN.fromBitstring([ilo'4,ilo'3,ilo'2,ilo'1,ilo'0],5))))) 12499 | (false, 12500 (false, 12501 (false, 12502 (true, 12503 (false, 12504 (aq'0, 12505 (rl'0, 12506 (false, 12507 (false, 12508 (false, 12509 (false, 12510 (false, 12511 (rs1'4, 12512 (rs1'3, 12513 (rs1'2, 12514 (rs1'1, 12515 (rs1'0, 12516 (false, 12517 (true, 12518 (false, 12519 (rd'4, 12520 (rd'3, 12521 (rd'2, 12522 (rd'1, 12523 (rd'0, 12524 (false, 12525 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12526 AMO(LR_W 12527 (BitsN.fromBitstring([aq'0],1), 12528 (BitsN.fromBitstring([rl'0],1), 12529 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12530 BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))))) 12531 | (false, 12532 (false, 12533 (false, 12534 (true, 12535 (false, 12536 (aq'0, 12537 (rl'0, 12538 (false, 12539 (false, 12540 (false, 12541 (false, 12542 (false, 12543 (rs1'4, 12544 (rs1'3, 12545 (rs1'2, 12546 (rs1'1, 12547 (rs1'0, 12548 (false, 12549 (true, 12550 (true, 12551 (rd'4, 12552 (rd'3, 12553 (rd'2, 12554 (rd'1, 12555 (rd'0, 12556 (false, 12557 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12558 AMO(LR_D 12559 (BitsN.fromBitstring([aq'0],1), 12560 (BitsN.fromBitstring([rl'0],1), 12561 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12562 BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))))) 12563 | (false, 12564 (false, 12565 (false, 12566 (true, 12567 (true, 12568 (aq'0, 12569 (rl'0, 12570 (rs2'4, 12571 (rs2'3, 12572 (rs2'2, 12573 (rs2'1, 12574 (rs2'0, 12575 (rs1'4, 12576 (rs1'3, 12577 (rs1'2, 12578 (rs1'1, 12579 (rs1'0, 12580 (false, 12581 (true, 12582 (false, 12583 (rd'4, 12584 (rd'3, 12585 (rd'2, 12586 (rd'1, 12587 (rd'0, 12588 (false, 12589 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12590 AMO(SC_W 12591 (BitsN.fromBitstring([aq'0],1), 12592 (BitsN.fromBitstring([rl'0],1), 12593 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12594 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12595 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12596 | (false, 12597 (false, 12598 (false, 12599 (true, 12600 (true, 12601 (aq'0, 12602 (rl'0, 12603 (rs2'4, 12604 (rs2'3, 12605 (rs2'2, 12606 (rs2'1, 12607 (rs2'0, 12608 (rs1'4, 12609 (rs1'3, 12610 (rs1'2, 12611 (rs1'1, 12612 (rs1'0, 12613 (false, 12614 (true, 12615 (true, 12616 (rd'4, 12617 (rd'3, 12618 (rd'2, 12619 (rd'1, 12620 (rd'0, 12621 (false, 12622 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12623 AMO(SC_D 12624 (BitsN.fromBitstring([aq'0],1), 12625 (BitsN.fromBitstring([rl'0],1), 12626 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12627 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12628 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12629 | (false, 12630 (false, 12631 (false, 12632 (false, 12633 (true, 12634 (aq'0, 12635 (rl'0, 12636 (rs2'4, 12637 (rs2'3, 12638 (rs2'2, 12639 (rs2'1, 12640 (rs2'0, 12641 (rs1'4, 12642 (rs1'3, 12643 (rs1'2, 12644 (rs1'1, 12645 (rs1'0, 12646 (false, 12647 (true, 12648 (false, 12649 (rd'4, 12650 (rd'3, 12651 (rd'2, 12652 (rd'1, 12653 (rd'0, 12654 (false, 12655 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12656 AMO(AMOSWAP_W 12657 (BitsN.fromBitstring([aq'0],1), 12658 (BitsN.fromBitstring([rl'0],1), 12659 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12660 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12661 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12662 | (false, 12663 (false, 12664 (false, 12665 (false, 12666 (false, 12667 (aq'0, 12668 (rl'0, 12669 (rs2'4, 12670 (rs2'3, 12671 (rs2'2, 12672 (rs2'1, 12673 (rs2'0, 12674 (rs1'4, 12675 (rs1'3, 12676 (rs1'2, 12677 (rs1'1, 12678 (rs1'0, 12679 (false, 12680 (true, 12681 (false, 12682 (rd'4, 12683 (rd'3, 12684 (rd'2, 12685 (rd'1, 12686 (rd'0, 12687 (false, 12688 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12689 AMO(AMOADD_W 12690 (BitsN.fromBitstring([aq'0],1), 12691 (BitsN.fromBitstring([rl'0],1), 12692 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12693 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12694 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12695 | (false, 12696 (false, 12697 (true, 12698 (false, 12699 (false, 12700 (aq'0, 12701 (rl'0, 12702 (rs2'4, 12703 (rs2'3, 12704 (rs2'2, 12705 (rs2'1, 12706 (rs2'0, 12707 (rs1'4, 12708 (rs1'3, 12709 (rs1'2, 12710 (rs1'1, 12711 (rs1'0, 12712 (false, 12713 (true, 12714 (false, 12715 (rd'4, 12716 (rd'3, 12717 (rd'2, 12718 (rd'1, 12719 (rd'0, 12720 (false, 12721 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12722 AMO(AMOXOR_W 12723 (BitsN.fromBitstring([aq'0],1), 12724 (BitsN.fromBitstring([rl'0],1), 12725 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12726 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12727 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12728 | (false, 12729 (true, 12730 (true, 12731 (false, 12732 (false, 12733 (aq'0, 12734 (rl'0, 12735 (rs2'4, 12736 (rs2'3, 12737 (rs2'2, 12738 (rs2'1, 12739 (rs2'0, 12740 (rs1'4, 12741 (rs1'3, 12742 (rs1'2, 12743 (rs1'1, 12744 (rs1'0, 12745 (false, 12746 (true, 12747 (false, 12748 (rd'4, 12749 (rd'3, 12750 (rd'2, 12751 (rd'1, 12752 (rd'0, 12753 (false, 12754 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12755 AMO(AMOAND_W 12756 (BitsN.fromBitstring([aq'0],1), 12757 (BitsN.fromBitstring([rl'0],1), 12758 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12759 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12760 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12761 | (false, 12762 (true, 12763 (false, 12764 (false, 12765 (false, 12766 (aq'0, 12767 (rl'0, 12768 (rs2'4, 12769 (rs2'3, 12770 (rs2'2, 12771 (rs2'1, 12772 (rs2'0, 12773 (rs1'4, 12774 (rs1'3, 12775 (rs1'2, 12776 (rs1'1, 12777 (rs1'0, 12778 (false, 12779 (true, 12780 (false, 12781 (rd'4, 12782 (rd'3, 12783 (rd'2, 12784 (rd'1, 12785 (rd'0, 12786 (false, 12787 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12788 AMO(AMOOR_W 12789 (BitsN.fromBitstring([aq'0],1), 12790 (BitsN.fromBitstring([rl'0],1), 12791 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12792 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12793 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12794 | (true, 12795 (false, 12796 (false, 12797 (false, 12798 (false, 12799 (aq'0, 12800 (rl'0, 12801 (rs2'4, 12802 (rs2'3, 12803 (rs2'2, 12804 (rs2'1, 12805 (rs2'0, 12806 (rs1'4, 12807 (rs1'3, 12808 (rs1'2, 12809 (rs1'1, 12810 (rs1'0, 12811 (false, 12812 (true, 12813 (false, 12814 (rd'4, 12815 (rd'3, 12816 (rd'2, 12817 (rd'1, 12818 (rd'0, 12819 (false, 12820 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12821 AMO(AMOMIN_W 12822 (BitsN.fromBitstring([aq'0],1), 12823 (BitsN.fromBitstring([rl'0],1), 12824 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12825 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12826 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12827 | (true, 12828 (false, 12829 (true, 12830 (false, 12831 (false, 12832 (aq'0, 12833 (rl'0, 12834 (rs2'4, 12835 (rs2'3, 12836 (rs2'2, 12837 (rs2'1, 12838 (rs2'0, 12839 (rs1'4, 12840 (rs1'3, 12841 (rs1'2, 12842 (rs1'1, 12843 (rs1'0, 12844 (false, 12845 (true, 12846 (false, 12847 (rd'4, 12848 (rd'3, 12849 (rd'2, 12850 (rd'1, 12851 (rd'0, 12852 (false, 12853 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12854 AMO(AMOMAX_W 12855 (BitsN.fromBitstring([aq'0],1), 12856 (BitsN.fromBitstring([rl'0],1), 12857 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12858 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12859 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12860 | (true, 12861 (true, 12862 (false, 12863 (false, 12864 (false, 12865 (aq'0, 12866 (rl'0, 12867 (rs2'4, 12868 (rs2'3, 12869 (rs2'2, 12870 (rs2'1, 12871 (rs2'0, 12872 (rs1'4, 12873 (rs1'3, 12874 (rs1'2, 12875 (rs1'1, 12876 (rs1'0, 12877 (false, 12878 (true, 12879 (false, 12880 (rd'4, 12881 (rd'3, 12882 (rd'2, 12883 (rd'1, 12884 (rd'0, 12885 (false, 12886 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12887 AMO(AMOMINU_W 12888 (BitsN.fromBitstring([aq'0],1), 12889 (BitsN.fromBitstring([rl'0],1), 12890 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12891 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12892 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12893 | (true, 12894 (true, 12895 (true, 12896 (false, 12897 (false, 12898 (aq'0, 12899 (rl'0, 12900 (rs2'4, 12901 (rs2'3, 12902 (rs2'2, 12903 (rs2'1, 12904 (rs2'0, 12905 (rs1'4, 12906 (rs1'3, 12907 (rs1'2, 12908 (rs1'1, 12909 (rs1'0, 12910 (false, 12911 (true, 12912 (false, 12913 (rd'4, 12914 (rd'3, 12915 (rd'2, 12916 (rd'1, 12917 (rd'0, 12918 (false, 12919 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12920 AMO(AMOMAXU_W 12921 (BitsN.fromBitstring([aq'0],1), 12922 (BitsN.fromBitstring([rl'0],1), 12923 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12924 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12925 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12926 | (false, 12927 (false, 12928 (false, 12929 (false, 12930 (true, 12931 (aq'0, 12932 (rl'0, 12933 (rs2'4, 12934 (rs2'3, 12935 (rs2'2, 12936 (rs2'1, 12937 (rs2'0, 12938 (rs1'4, 12939 (rs1'3, 12940 (rs1'2, 12941 (rs1'1, 12942 (rs1'0, 12943 (false, 12944 (true, 12945 (true, 12946 (rd'4, 12947 (rd'3, 12948 (rd'2, 12949 (rd'1, 12950 (rd'0, 12951 (false, 12952 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12953 AMO(AMOSWAP_D 12954 (BitsN.fromBitstring([aq'0],1), 12955 (BitsN.fromBitstring([rl'0],1), 12956 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12957 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12958 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12959 | (false, 12960 (false, 12961 (false, 12962 (false, 12963 (false, 12964 (aq'0, 12965 (rl'0, 12966 (rs2'4, 12967 (rs2'3, 12968 (rs2'2, 12969 (rs2'1, 12970 (rs2'0, 12971 (rs1'4, 12972 (rs1'3, 12973 (rs1'2, 12974 (rs1'1, 12975 (rs1'0, 12976 (false, 12977 (true, 12978 (true, 12979 (rd'4, 12980 (rd'3, 12981 (rd'2, 12982 (rd'1, 12983 (rd'0, 12984 (false, 12985 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 12986 AMO(AMOADD_D 12987 (BitsN.fromBitstring([aq'0],1), 12988 (BitsN.fromBitstring([rl'0],1), 12989 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 12990 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 12991 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 12992 | (false, 12993 (false, 12994 (true, 12995 (false, 12996 (false, 12997 (aq'0, 12998 (rl'0, 12999 (rs2'4, 13000 (rs2'3, 13001 (rs2'2, 13002 (rs2'1, 13003 (rs2'0, 13004 (rs1'4, 13005 (rs1'3, 13006 (rs1'2, 13007 (rs1'1, 13008 (rs1'0, 13009 (false, 13010 (true, 13011 (true, 13012 (rd'4, 13013 (rd'3, 13014 (rd'2, 13015 (rd'1, 13016 (rd'0, 13017 (false, 13018 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 13019 AMO(AMOXOR_D 13020 (BitsN.fromBitstring([aq'0],1), 13021 (BitsN.fromBitstring([rl'0],1), 13022 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13023 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13024 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 13025 | (false, 13026 (true, 13027 (true, 13028 (false, 13029 (false, 13030 (aq'0, 13031 (rl'0, 13032 (rs2'4, 13033 (rs2'3, 13034 (rs2'2, 13035 (rs2'1, 13036 (rs2'0, 13037 (rs1'4, 13038 (rs1'3, 13039 (rs1'2, 13040 (rs1'1, 13041 (rs1'0, 13042 (false, 13043 (true, 13044 (true, 13045 (rd'4, 13046 (rd'3, 13047 (rd'2, 13048 (rd'1, 13049 (rd'0, 13050 (false, 13051 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 13052 AMO(AMOAND_D 13053 (BitsN.fromBitstring([aq'0],1), 13054 (BitsN.fromBitstring([rl'0],1), 13055 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13056 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13057 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 13058 | (false, 13059 (true, 13060 (false, 13061 (false, 13062 (false, 13063 (aq'0, 13064 (rl'0, 13065 (rs2'4, 13066 (rs2'3, 13067 (rs2'2, 13068 (rs2'1, 13069 (rs2'0, 13070 (rs1'4, 13071 (rs1'3, 13072 (rs1'2, 13073 (rs1'1, 13074 (rs1'0, 13075 (false, 13076 (true, 13077 (true, 13078 (rd'4, 13079 (rd'3, 13080 (rd'2, 13081 (rd'1, 13082 (rd'0, 13083 (false, 13084 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 13085 AMO(AMOOR_D 13086 (BitsN.fromBitstring([aq'0],1), 13087 (BitsN.fromBitstring([rl'0],1), 13088 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13089 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13090 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 13091 | (true, 13092 (false, 13093 (false, 13094 (false, 13095 (false, 13096 (aq'0, 13097 (rl'0, 13098 (rs2'4, 13099 (rs2'3, 13100 (rs2'2, 13101 (rs2'1, 13102 (rs2'0, 13103 (rs1'4, 13104 (rs1'3, 13105 (rs1'2, 13106 (rs1'1, 13107 (rs1'0, 13108 (false, 13109 (true, 13110 (true, 13111 (rd'4, 13112 (rd'3, 13113 (rd'2, 13114 (rd'1, 13115 (rd'0, 13116 (false, 13117 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 13118 AMO(AMOMIN_D 13119 (BitsN.fromBitstring([aq'0],1), 13120 (BitsN.fromBitstring([rl'0],1), 13121 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13122 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13123 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 13124 | (true, 13125 (false, 13126 (true, 13127 (false, 13128 (false, 13129 (aq'0, 13130 (rl'0, 13131 (rs2'4, 13132 (rs2'3, 13133 (rs2'2, 13134 (rs2'1, 13135 (rs2'0, 13136 (rs1'4, 13137 (rs1'3, 13138 (rs1'2, 13139 (rs1'1, 13140 (rs1'0, 13141 (false, 13142 (true, 13143 (true, 13144 (rd'4, 13145 (rd'3, 13146 (rd'2, 13147 (rd'1, 13148 (rd'0, 13149 (false, 13150 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 13151 AMO(AMOMAX_D 13152 (BitsN.fromBitstring([aq'0],1), 13153 (BitsN.fromBitstring([rl'0],1), 13154 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13155 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13156 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 13157 | (true, 13158 (true, 13159 (false, 13160 (false, 13161 (false, 13162 (aq'0, 13163 (rl'0, 13164 (rs2'4, 13165 (rs2'3, 13166 (rs2'2, 13167 (rs2'1, 13168 (rs2'0, 13169 (rs1'4, 13170 (rs1'3, 13171 (rs1'2, 13172 (rs1'1, 13173 (rs1'0, 13174 (false, 13175 (true, 13176 (true, 13177 (rd'4, 13178 (rd'3, 13179 (rd'2, 13180 (rd'1, 13181 (rd'0, 13182 (false, 13183 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 13184 AMO(AMOMINU_D 13185 (BitsN.fromBitstring([aq'0],1), 13186 (BitsN.fromBitstring([rl'0],1), 13187 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13188 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13189 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 13190 | (true, 13191 (true, 13192 (true, 13193 (false, 13194 (false, 13195 (aq'0, 13196 (rl'0, 13197 (rs2'4, 13198 (rs2'3, 13199 (rs2'2, 13200 (rs2'1, 13201 (rs2'0, 13202 (rs1'4, 13203 (rs1'3, 13204 (rs1'2, 13205 (rs1'1, 13206 (rs1'0, 13207 (false, 13208 (true, 13209 (true, 13210 (rd'4, 13211 (rd'3, 13212 (rd'2, 13213 (rd'1, 13214 (rd'0, 13215 (false, 13216 (true,(false,(true,(true,(true,true))))))))))))))))))))))))))))))) => 13217 AMO(AMOMAXU_D 13218 (BitsN.fromBitstring([aq'0],1), 13219 (BitsN.fromBitstring([rl'0],1), 13220 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13221 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13222 BitsN.fromBitstring([rs2'4,rs2'3,rs2'2,rs2'1,rs2'0],5)))))) 13223 | (csr'11, 13224 (csr'10, 13225 (csr'9, 13226 (csr'8, 13227 (csr'7, 13228 (csr'6, 13229 (csr'5, 13230 (csr'4, 13231 (csr'3, 13232 (csr'2, 13233 (csr'1, 13234 (csr'0, 13235 (rs1'4, 13236 (rs1'3, 13237 (rs1'2, 13238 (rs1'1, 13239 (rs1'0, 13240 (false, 13241 (false, 13242 (true, 13243 (rd'4, 13244 (rd'3, 13245 (rd'2, 13246 (rd'1, 13247 (rd'0, 13248 (true, 13249 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13250 System 13251 (CSRRW 13252 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13253 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13254 BitsN.fromBitstring 13255 ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, 13256 csr'2,csr'1,csr'0],12)))) 13257 | (csr'11, 13258 (csr'10, 13259 (csr'9, 13260 (csr'8, 13261 (csr'7, 13262 (csr'6, 13263 (csr'5, 13264 (csr'4, 13265 (csr'3, 13266 (csr'2, 13267 (csr'1, 13268 (csr'0, 13269 (rs1'4, 13270 (rs1'3, 13271 (rs1'2, 13272 (rs1'1, 13273 (rs1'0, 13274 (false, 13275 (true, 13276 (false, 13277 (rd'4, 13278 (rd'3, 13279 (rd'2, 13280 (rd'1, 13281 (rd'0, 13282 (true, 13283 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13284 System 13285 (CSRRS 13286 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13287 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13288 BitsN.fromBitstring 13289 ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, 13290 csr'2,csr'1,csr'0],12)))) 13291 | (csr'11, 13292 (csr'10, 13293 (csr'9, 13294 (csr'8, 13295 (csr'7, 13296 (csr'6, 13297 (csr'5, 13298 (csr'4, 13299 (csr'3, 13300 (csr'2, 13301 (csr'1, 13302 (csr'0, 13303 (rs1'4, 13304 (rs1'3, 13305 (rs1'2, 13306 (rs1'1, 13307 (rs1'0, 13308 (false, 13309 (true, 13310 (true, 13311 (rd'4, 13312 (rd'3, 13313 (rd'2, 13314 (rd'1, 13315 (rd'0, 13316 (true, 13317 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13318 System 13319 (CSRRC 13320 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13321 (BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5), 13322 BitsN.fromBitstring 13323 ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, 13324 csr'2,csr'1,csr'0],12)))) 13325 | (csr'11, 13326 (csr'10, 13327 (csr'9, 13328 (csr'8, 13329 (csr'7, 13330 (csr'6, 13331 (csr'5, 13332 (csr'4, 13333 (csr'3, 13334 (csr'2, 13335 (csr'1, 13336 (csr'0, 13337 (imm'4, 13338 (imm'3, 13339 (imm'2, 13340 (imm'1, 13341 (imm'0, 13342 (true, 13343 (false, 13344 (true, 13345 (rd'4, 13346 (rd'3, 13347 (rd'2, 13348 (rd'1, 13349 (rd'0, 13350 (true, 13351 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13352 System 13353 (CSRRWI 13354 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13355 (BitsN.fromBitstring([imm'4,imm'3,imm'2,imm'1,imm'0],5), 13356 BitsN.fromBitstring 13357 ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, 13358 csr'2,csr'1,csr'0],12)))) 13359 | (csr'11, 13360 (csr'10, 13361 (csr'9, 13362 (csr'8, 13363 (csr'7, 13364 (csr'6, 13365 (csr'5, 13366 (csr'4, 13367 (csr'3, 13368 (csr'2, 13369 (csr'1, 13370 (csr'0, 13371 (imm'4, 13372 (imm'3, 13373 (imm'2, 13374 (imm'1, 13375 (imm'0, 13376 (true, 13377 (true, 13378 (false, 13379 (rd'4, 13380 (rd'3, 13381 (rd'2, 13382 (rd'1, 13383 (rd'0, 13384 (true, 13385 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13386 System 13387 (CSRRSI 13388 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13389 (BitsN.fromBitstring([imm'4,imm'3,imm'2,imm'1,imm'0],5), 13390 BitsN.fromBitstring 13391 ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, 13392 csr'2,csr'1,csr'0],12)))) 13393 | (csr'11, 13394 (csr'10, 13395 (csr'9, 13396 (csr'8, 13397 (csr'7, 13398 (csr'6, 13399 (csr'5, 13400 (csr'4, 13401 (csr'3, 13402 (csr'2, 13403 (csr'1, 13404 (csr'0, 13405 (imm'4, 13406 (imm'3, 13407 (imm'2, 13408 (imm'1, 13409 (imm'0, 13410 (true, 13411 (true, 13412 (true, 13413 (rd'4, 13414 (rd'3, 13415 (rd'2, 13416 (rd'1, 13417 (rd'0, 13418 (true, 13419 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13420 System 13421 (CSRRCI 13422 (BitsN.fromBitstring([rd'4,rd'3,rd'2,rd'1,rd'0],5), 13423 (BitsN.fromBitstring([imm'4,imm'3,imm'2,imm'1,imm'0],5), 13424 BitsN.fromBitstring 13425 ([csr'11,csr'10,csr'9,csr'8,csr'7,csr'6,csr'5,csr'4,csr'3, 13426 csr'2,csr'1,csr'0],12)))) 13427 | (false, 13428 (false, 13429 (false, 13430 (false, 13431 (false, 13432 (false, 13433 (false, 13434 (false, 13435 (false, 13436 (false, 13437 (false, 13438 (false, 13439 (false, 13440 (false, 13441 (false, 13442 (false, 13443 (false, 13444 (false, 13445 (false, 13446 (false, 13447 (false, 13448 (false, 13449 (false, 13450 (false, 13451 (false, 13452 (true, 13453 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13454 System ECALL 13455 | (false, 13456 (false, 13457 (false, 13458 (false, 13459 (false, 13460 (false, 13461 (false, 13462 (false, 13463 (false, 13464 (false, 13465 (false, 13466 (true, 13467 (false, 13468 (false, 13469 (false, 13470 (false, 13471 (false, 13472 (false, 13473 (false, 13474 (false, 13475 (false, 13476 (false, 13477 (false, 13478 (false, 13479 (false, 13480 (true, 13481 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13482 System EBREAK 13483 | (false, 13484 (false, 13485 (false, 13486 (true, 13487 (false, 13488 (false, 13489 (false, 13490 (false, 13491 (false, 13492 (false, 13493 (false, 13494 (false, 13495 (false, 13496 (false, 13497 (false, 13498 (false, 13499 (false, 13500 (false, 13501 (false, 13502 (false, 13503 (false, 13504 (false, 13505 (false, 13506 (false, 13507 (false, 13508 (true, 13509 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13510 System ERET 13511 | (false, 13512 (false, 13513 (true, 13514 (true, 13515 (false, 13516 (false, 13517 (false, 13518 (false, 13519 (false, 13520 (true, 13521 (false, 13522 (true, 13523 (false, 13524 (false, 13525 (false, 13526 (false, 13527 (false, 13528 (false, 13529 (false, 13530 (false, 13531 (false, 13532 (false, 13533 (false, 13534 (false, 13535 (false, 13536 (true, 13537 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13538 System MRTS 13539 | (false, 13540 (false, 13541 (false, 13542 (true, 13543 (false, 13544 (false, 13545 (false, 13546 (false, 13547 (false, 13548 (false, 13549 (true, 13550 (false, 13551 (false, 13552 (false, 13553 (false, 13554 (false, 13555 (false, 13556 (false, 13557 (false, 13558 (false, 13559 (false, 13560 (false, 13561 (false, 13562 (false, 13563 (false, 13564 (true, 13565 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13566 System WFI 13567 | (false, 13568 (false, 13569 (false, 13570 (true, 13571 (false, 13572 (false, 13573 (false, 13574 (false, 13575 (false, 13576 (false, 13577 (false, 13578 (true, 13579 (rs1'4, 13580 (rs1'3, 13581 (rs1'2, 13582 (rs1'1, 13583 (rs1'0, 13584 (false, 13585 (false, 13586 (false, 13587 (false, 13588 (false, 13589 (false, 13590 (false, 13591 (false, 13592 (true, 13593 (true,(true,(false,(false,(true,true))))))))))))))))))))))))))))))) => 13594 System 13595 (SFENCE_VM(BitsN.fromBitstring([rs1'4,rs1'3,rs1'2,rs1'1,rs1'0],5))) 13596 | _ => UnknownInstruction; 13597 13598fun imm N i = "0x" ^ (BitsN.toHexString i); 13599 13600fun instr o' = L3.padRightString(#" ",(12,o')); 13601 13602fun amotype (aq,rl) = 13603 case (aq,rl) of 13604 (BitsN.B(0x0,_),BitsN.B(0x0,_)) => "" 13605 | (BitsN.B(0x1,_),BitsN.B(0x0,_)) => ".aq" 13606 | (BitsN.B(0x0,_),BitsN.B(0x1,_)) => ".rl" 13607 | (BitsN.B(0x1,_),BitsN.B(0x1,_)) => ".sc"; 13608 13609fun pRtype (o',(rd,(rs1,rs2))) = 13610 String.concat[instr o'," ",reg rd,", ",reg rs1,", ",reg rs2]; 13611 13612fun pARtype (o',(aq,(rl,(rd,(rs1,rs2))))) = 13613 pRtype(o' ^ (amotype(aq,rl)),(rd,(rs1,rs2))); 13614 13615fun pLRtype (o',(aq,(rl,(rd,rs1)))) = 13616 String.concat[instr(o' ^ (amotype(aq,rl)))," ",reg rd,", ",reg rs1]; 13617 13618fun pItype N (o',(rd,(rs1,i))) = 13619 String.concat[instr o'," ",reg rd,", ",reg rs1,", ",imm N i]; 13620 13621fun pCSRtype (o',(rd,(rs1,csr))) = 13622 String.concat[instr o'," ",reg rd,", ",reg rs1,", ",csrName csr]; 13623 13624fun pCSRItype N (o',(rd,(i,csr))) = 13625 String.concat[instr o'," ",reg rd,", ",imm N i,", ",csrName csr]; 13626 13627fun pStype N (o',(rs1,(rs2,i))) = 13628 String.concat[instr o'," ",reg rs2,", ",reg rs1,", ",imm N i]; 13629 13630fun pSBtype N (o',(rs1,(rs2,i))) = 13631 String.concat 13632 [instr o'," ",reg rs1,", ",reg rs2,", ",imm N (BitsN.<<(i,1))]; 13633 13634fun pUtype N (o',(rd,i)) = 13635 String.concat[instr o'," ",reg rd,", ",imm N i]; 13636 13637fun pUJtype N (o',(rd,i)) = 13638 String.concat[instr o'," ",reg rd,", ",imm N (BitsN.<<(i,1))]; 13639 13640fun pN0type o' = instr o'; 13641 13642fun pN1type (o',r) = String.concat[instr o'," ",reg r]; 13643 13644fun pFRtype (o',(rd,(rs1,rs2))) = 13645 String.concat[instr o'," ",fpreg rd,", ",fpreg rs1,", ",fpreg rs2]; 13646 13647fun pFR1type (o',(rd,rs)) = 13648 String.concat[instr o'," ",fpreg rd,", ",fpreg rs]; 13649 13650fun pFR3type (o',(rd,(rs1,(rs2,rs3)))) = 13651 String.concat 13652 [instr o'," ",fpreg rd,", ",fpreg rs1,", ",fpreg rs2,", ",fpreg rs3]; 13653 13654fun pFItype N (o',(rd,(rs1,i))) = 13655 String.concat[instr o'," ",fpreg rd,", ",reg rs1,", ",imm N i]; 13656 13657fun pFStype N (o',(rs1,(rs2,i))) = 13658 String.concat[instr o'," ",fpreg rs2,", ",reg rs1,", ",imm N i]; 13659 13660fun pCFItype (o',(rd,rs)) = 13661 String.concat[instr o'," ",fpreg rd,", ",reg rs]; 13662 13663fun pCIFtype (o',(rd,rs)) = 13664 String.concat[instr o'," ",reg rd,", ",fpreg rs]; 13665 13666fun instructionToString i = 13667 case i of 13668 Branch(BEQ(rs1,(rs2,imm))) => pSBtype 12 ("BEQ",(rs1,(rs2,imm))) 13669 | Branch(BNE(rs1,(rs2,imm))) => pSBtype 12 ("BNE",(rs1,(rs2,imm))) 13670 | Branch(BLT(rs1,(rs2,imm))) => pSBtype 12 ("BLT",(rs1,(rs2,imm))) 13671 | Branch(BGE(rs1,(rs2,imm))) => pSBtype 12 ("BGE",(rs1,(rs2,imm))) 13672 | Branch(BLTU(rs1,(rs2,imm))) => pSBtype 12 ("BLTU",(rs1,(rs2,imm))) 13673 | Branch(BGEU(rs1,(rs2,imm))) => pSBtype 12 ("BGEU",(rs1,(rs2,imm))) 13674 | Branch(JALR(rd,(rs1,imm))) => pItype 12 ("JALR",(rd,(rs1,imm))) 13675 | Branch(JAL(rd,imm)) => pUJtype 20 ("JAL",(rd,imm)) 13676 | ArithI(LUI(rd,imm)) => pUtype 20 ("LUI",(rd,imm)) 13677 | ArithI(AUIPC(rd,imm)) => pUtype 20 ("AUIPC",(rd,imm)) 13678 | ArithI(ADDI(rd,(rs1,imm))) => pItype 12 ("ADDI",(rd,(rs1,imm))) 13679 | Shift(SLLI(rd,(rs1,imm))) => pItype 6 ("SLLI",(rd,(rs1,imm))) 13680 | ArithI(SLTI(rd,(rs1,imm))) => pItype 12 ("SLTI",(rd,(rs1,imm))) 13681 | ArithI(SLTIU(rd,(rs1,imm))) => pItype 12 ("SLTIU",(rd,(rs1,imm))) 13682 | ArithI(XORI(rd,(rs1,imm))) => pItype 12 ("XORI",(rd,(rs1,imm))) 13683 | Shift(SRLI(rd,(rs1,imm))) => pItype 6 ("SRLI",(rd,(rs1,imm))) 13684 | Shift(SRAI(rd,(rs1,imm))) => pItype 6 ("SRAI",(rd,(rs1,imm))) 13685 | ArithI(ORI(rd,(rs1,imm))) => pItype 12 ("ORI",(rd,(rs1,imm))) 13686 | ArithI(ANDI(rd,(rs1,imm))) => pItype 12 ("ANDI",(rd,(rs1,imm))) 13687 | ArithR(ADD(rd,(rs1,rs2))) => pRtype("ADD",(rd,(rs1,rs2))) 13688 | ArithR(SUB(rd,(rs1,rs2))) => pRtype("SUB",(rd,(rs1,rs2))) 13689 | Shift(SLL(rd,(rs1,rs2))) => pRtype("SLL",(rd,(rs1,rs2))) 13690 | ArithR(SLT(rd,(rs1,rs2))) => pRtype("SLT",(rd,(rs1,rs2))) 13691 | ArithR(SLTU(rd,(rs1,rs2))) => pRtype("SLTU",(rd,(rs1,rs2))) 13692 | ArithR(XOR(rd,(rs1,rs2))) => pRtype("XOR",(rd,(rs1,rs2))) 13693 | Shift(SRL(rd,(rs1,rs2))) => pRtype("SRL",(rd,(rs1,rs2))) 13694 | Shift(SRA(rd,(rs1,rs2))) => pRtype("SRA",(rd,(rs1,rs2))) 13695 | ArithR(OR(rd,(rs1,rs2))) => pRtype("OR",(rd,(rs1,rs2))) 13696 | ArithR(AND(rd,(rs1,rs2))) => pRtype("AND",(rd,(rs1,rs2))) 13697 | ArithI(ADDIW(rd,(rs1,imm))) => pItype 12 ("ADDIW",(rd,(rs1,imm))) 13698 | Shift(SLLIW(rd,(rs1,imm))) => pItype 5 ("SLLIW",(rd,(rs1,imm))) 13699 | Shift(SRLIW(rd,(rs1,imm))) => pItype 5 ("SRLIW",(rd,(rs1,imm))) 13700 | Shift(SRAIW(rd,(rs1,imm))) => pItype 5 ("SRAIW",(rd,(rs1,imm))) 13701 | ArithR(ADDW(rd,(rs1,rs2))) => pRtype("ADDW",(rd,(rs1,rs2))) 13702 | ArithR(SUBW(rd,(rs1,rs2))) => pRtype("SUBW",(rd,(rs1,rs2))) 13703 | Shift(SLLW(rd,(rs1,rs2))) => pRtype("SLLW",(rd,(rs1,rs2))) 13704 | Shift(SRLW(rd,(rs1,rs2))) => pRtype("SRLW",(rd,(rs1,rs2))) 13705 | Shift(SRAW(rd,(rs1,rs2))) => pRtype("SRAW",(rd,(rs1,rs2))) 13706 | MulDiv(MUL(rd,(rs1,rs2))) => pRtype("MUL",(rd,(rs1,rs2))) 13707 | MulDiv(MULH(rd,(rs1,rs2))) => pRtype("MULH",(rd,(rs1,rs2))) 13708 | MulDiv(MULHSU(rd,(rs1,rs2))) => pRtype("MULHSU",(rd,(rs1,rs2))) 13709 | MulDiv(MULHU(rd,(rs1,rs2))) => pRtype("MULHU",(rd,(rs1,rs2))) 13710 | MulDiv(DIV(rd,(rs1,rs2))) => pRtype("DIV",(rd,(rs1,rs2))) 13711 | MulDiv(DIVU(rd,(rs1,rs2))) => pRtype("DIVU",(rd,(rs1,rs2))) 13712 | MulDiv(REM(rd,(rs1,rs2))) => pRtype("REM",(rd,(rs1,rs2))) 13713 | MulDiv(REMU(rd,(rs1,rs2))) => pRtype("REMU",(rd,(rs1,rs2))) 13714 | MulDiv(MULW(rd,(rs1,rs2))) => pRtype("MULW",(rd,(rs1,rs2))) 13715 | MulDiv(DIVW(rd,(rs1,rs2))) => pRtype("DIVW",(rd,(rs1,rs2))) 13716 | MulDiv(DIVUW(rd,(rs1,rs2))) => pRtype("DIVUW",(rd,(rs1,rs2))) 13717 | MulDiv(REMW(rd,(rs1,rs2))) => pRtype("REMW",(rd,(rs1,rs2))) 13718 | MulDiv(REMUW(rd,(rs1,rs2))) => pRtype("REMUW",(rd,(rs1,rs2))) 13719 | Load(LB(rd,(rs1,imm))) => pItype 12 ("LB",(rd,(rs1,imm))) 13720 | Load(LH(rd,(rs1,imm))) => pItype 12 ("LH",(rd,(rs1,imm))) 13721 | Load(LW(rd,(rs1,imm))) => pItype 12 ("LW",(rd,(rs1,imm))) 13722 | Load(LD(rd,(rs1,imm))) => pItype 12 ("LD",(rd,(rs1,imm))) 13723 | Load(LBU(rd,(rs1,imm))) => pItype 12 ("LBU",(rd,(rs1,imm))) 13724 | Load(LHU(rd,(rs1,imm))) => pItype 12 ("LHU",(rd,(rs1,imm))) 13725 | Load(LWU(rd,(rs1,imm))) => pItype 12 ("LWU",(rd,(rs1,imm))) 13726 | Store(SB(rs1,(rs2,imm))) => pStype 12 ("SB",(rs1,(rs2,imm))) 13727 | Store(SH(rs1,(rs2,imm))) => pStype 12 ("SH",(rs1,(rs2,imm))) 13728 | Store(SW(rs1,(rs2,imm))) => pStype 12 ("SW",(rs1,(rs2,imm))) 13729 | Store(SD(rs1,(rs2,imm))) => pStype 12 ("SD",(rs1,(rs2,imm))) 13730 | FENCE(rd,(rs1,(pred,succ))) => pN0type "FENCE" 13731 | FENCE_I(rd,(rs1,imm)) => pN0type "FENCE.I" 13732 | FArith(FADD_S(rd,(rs1,(rs2,frm)))) => 13733 pFRtype("FADD.S",(rd,(rs1,rs2))) 13734 | FArith(FSUB_S(rd,(rs1,(rs2,frm)))) => 13735 pFRtype("FSUB.S",(rd,(rs1,rs2))) 13736 | FArith(FMUL_S(rd,(rs1,(rs2,frm)))) => 13737 pFRtype("FMUL.S",(rd,(rs1,rs2))) 13738 | FArith(FDIV_S(rd,(rs1,(rs2,frm)))) => 13739 pFRtype("FDIV.S",(rd,(rs1,rs2))) 13740 | FArith(FSQRT_S(rd,(rs,frm))) => pFR1type("FSQRT.S",(rd,rs)) 13741 | FArith(FMIN_S(rd,(rs1,rs2))) => pFRtype("FMIN.S",(rd,(rs1,rs2))) 13742 | FArith(FMAX_S(rd,(rs1,rs2))) => pFRtype("FMAX.S",(rd,(rs1,rs2))) 13743 | FArith(FEQ_S(rd,(rs1,rs2))) => pFRtype("FEQ.S",(rd,(rs1,rs2))) 13744 | FArith(FLT_S(rd,(rs1,rs2))) => pFRtype("FLT.S",(rd,(rs1,rs2))) 13745 | FArith(FLE_S(rd,(rs1,rs2))) => pFRtype("FLE.S",(rd,(rs1,rs2))) 13746 | FArith(FMADD_S(rd,(rs1,(rs2,(rs3,frm))))) => 13747 pFR3type("FMADD.S",(rd,(rs1,(rs2,rs3)))) 13748 | FArith(FMSUB_S(rd,(rs1,(rs2,(rs3,frm))))) => 13749 pFR3type("FMSUB.S",(rd,(rs1,(rs2,rs3)))) 13750 | FArith(FNMADD_S(rd,(rs1,(rs2,(rs3,frm))))) => 13751 pFR3type("FNMADD.S",(rd,(rs1,(rs2,rs3)))) 13752 | FArith(FNMSUB_S(rd,(rs1,(rs2,(rs3,frm))))) => 13753 pFR3type("FNMSUB.S",(rd,(rs1,(rs2,rs3)))) 13754 | FArith(FADD_D(rd,(rs1,(rs2,frm)))) => 13755 pFRtype("FADD.D",(rd,(rs1,rs2))) 13756 | FArith(FSUB_D(rd,(rs1,(rs2,frm)))) => 13757 pFRtype("FSUB.D",(rd,(rs1,rs2))) 13758 | FArith(FMUL_D(rd,(rs1,(rs2,frm)))) => 13759 pFRtype("FMUL.D",(rd,(rs1,rs2))) 13760 | FArith(FDIV_D(rd,(rs1,(rs2,frm)))) => 13761 pFRtype("FDIV.D",(rd,(rs1,rs2))) 13762 | FArith(FSQRT_D(rd,(rs,frm))) => pFR1type("FSQRT.D",(rd,rs)) 13763 | FArith(FMIN_D(rd,(rs1,rs2))) => pFRtype("FMIN.D",(rd,(rs1,rs2))) 13764 | FArith(FMAX_D(rd,(rs1,rs2))) => pFRtype("FMAX.D",(rd,(rs1,rs2))) 13765 | FArith(FEQ_D(rd,(rs1,rs2))) => pFRtype("FEQ.D",(rd,(rs1,rs2))) 13766 | FArith(FLT_D(rd,(rs1,rs2))) => pFRtype("FLT.D",(rd,(rs1,rs2))) 13767 | FArith(FLE_D(rd,(rs1,rs2))) => pFRtype("FLE.D",(rd,(rs1,rs2))) 13768 | FArith(FMADD_D(rd,(rs1,(rs2,(rs3,frm))))) => 13769 pFR3type("FMADD.D",(rd,(rs1,(rs2,rs3)))) 13770 | FArith(FMSUB_D(rd,(rs1,(rs2,(rs3,frm))))) => 13771 pFR3type("FMSUB.D",(rd,(rs1,(rs2,rs3)))) 13772 | FArith(FNMADD_D(rd,(rs1,(rs2,(rs3,frm))))) => 13773 pFR3type("FNMADD.D",(rd,(rs1,(rs2,rs3)))) 13774 | FArith(FNMSUB_D(rd,(rs1,(rs2,(rs3,frm))))) => 13775 pFR3type("FNMSUB.D",(rd,(rs1,(rs2,rs3)))) 13776 | FConv(FSGNJ_S(rd,(rs1,rs2))) => pFRtype("FSGNJ.S",(rd,(rs1,rs2))) 13777 | FConv(FSGNJN_S(rd,(rs1,rs2))) => pFRtype("FSGNJN.S",(rd,(rs1,rs2))) 13778 | FConv(FSGNJX_S(rd,(rs1,rs2))) => pFRtype("FSGNJX.S",(rd,(rs1,rs2))) 13779 | FConv(FCVT_W_S(rd,(rs,frm))) => pCIFtype("FCVT.W.S",(rd,rs)) 13780 | FConv(FCVT_WU_S(rd,(rs,frm))) => pCIFtype("FCVT.WU.S",(rd,rs)) 13781 | FConv(FMV_X_S(rd,rs)) => pCIFtype("FMV.X.S",(rd,rs)) 13782 | FConv(FCLASS_S(rd,rs)) => pCIFtype("FCLASS.S",(rd,rs)) 13783 | FConv(FCVT_S_W(rd,(rs,frm))) => pCFItype("FCVT.S.W",(rd,rs)) 13784 | FConv(FCVT_S_WU(rd,(rs,frm))) => pCFItype("FCVT.S.WU",(rd,rs)) 13785 | FConv(FMV_S_X(rd,rs)) => pCFItype("FMV.S.X",(rd,rs)) 13786 | FConv(FSGNJ_D(rd,(rs1,rs2))) => pFRtype("FSGNJ.D",(rd,(rs1,rs2))) 13787 | FConv(FSGNJN_D(rd,(rs1,rs2))) => pFRtype("FSGNJN.D",(rd,(rs1,rs2))) 13788 | FConv(FSGNJX_D(rd,(rs1,rs2))) => pFRtype("FSGNJX.D",(rd,(rs1,rs2))) 13789 | FConv(FCVT_W_D(rd,(rs,frm))) => pCIFtype("FCVT.W.D",(rd,rs)) 13790 | FConv(FCVT_WU_D(rd,(rs,frm))) => pCIFtype("FCVT.WU.D",(rd,rs)) 13791 | FConv(FCLASS_D(rd,rs)) => pCIFtype("FCLASS.D",(rd,rs)) 13792 | FConv(FCVT_D_W(rd,(rs,frm))) => pCFItype("FCVT.D.W",(rd,rs)) 13793 | FConv(FCVT_D_WU(rd,(rs,frm))) => pCFItype("FCVT.D.WU",(rd,rs)) 13794 | FConv(FCVT_L_S(rd,(rs,frm))) => pCIFtype("FCVT.L.S",(rd,rs)) 13795 | FConv(FCVT_LU_S(rd,(rs,frm))) => pCIFtype("FCVT.LU.S",(rd,rs)) 13796 | FConv(FCVT_S_L(rd,(rs,frm))) => pCFItype("FCVT.S.L",(rd,rs)) 13797 | FConv(FCVT_S_LU(rd,(rs,frm))) => pCFItype("FCVT.S.LU",(rd,rs)) 13798 | FConv(FCVT_L_D(rd,(rs,frm))) => pCIFtype("FCVT.L.D",(rd,rs)) 13799 | FConv(FCVT_LU_D(rd,(rs,frm))) => pCIFtype("FCVT.LU.D",(rd,rs)) 13800 | FConv(FMV_X_D(rd,rs)) => pCIFtype("FMV.X.D",(rd,rs)) 13801 | FConv(FCVT_D_L(rd,(rs,frm))) => pCFItype("FCVT.D.L",(rd,rs)) 13802 | FConv(FCVT_D_LU(rd,(rs,frm))) => pCFItype("FCVT.D.LU",(rd,rs)) 13803 | FConv(FMV_D_X(rd,rs)) => pCFItype("FMV.D.X",(rd,rs)) 13804 | FConv(FCVT_D_S(rd,(rs,frm))) => pCFItype("FCVT.D.S",(rd,rs)) 13805 | FConv(FCVT_S_D(rd,(rs,frm))) => pCFItype("FCVT.S.D",(rd,rs)) 13806 | FPLoad(FLW(rd,(rs1,imm))) => pFItype 12 ("FLW",(rd,(rs1,imm))) 13807 | FPLoad(FLD(rd,(rs1,imm))) => pFItype 12 ("FLD",(rd,(rs1,imm))) 13808 | FPStore(FSW(rs1,(rs2,imm))) => pFStype 12 ("FSW",(rs1,(rs2,imm))) 13809 | FPStore(FSD(rs1,(rs2,imm))) => pFStype 12 ("FSD",(rs1,(rs2,imm))) 13810 | AMO(LR_W(aq,(rl,(rd,rs1)))) => pLRtype("LR.W",(aq,(rl,(rd,rs1)))) 13811 | AMO(LR_D(aq,(rl,(rd,rs1)))) => pLRtype("LR.D",(aq,(rl,(rd,rs1)))) 13812 | AMO(SC_W(aq,(rl,(rd,(rs1,rs2))))) => 13813 pARtype("SC.W",(aq,(rl,(rd,(rs1,rs2))))) 13814 | AMO(SC_D(aq,(rl,(rd,(rs1,rs2))))) => 13815 pARtype("SC.D",(aq,(rl,(rd,(rs1,rs2))))) 13816 | AMO(AMOSWAP_W(aq,(rl,(rd,(rs1,rs2))))) => 13817 pARtype("AMOSWAP.W",(aq,(rl,(rd,(rs1,rs2))))) 13818 | AMO(AMOADD_W(aq,(rl,(rd,(rs1,rs2))))) => 13819 pARtype("AMOADD.W",(aq,(rl,(rd,(rs1,rs2))))) 13820 | AMO(AMOXOR_W(aq,(rl,(rd,(rs1,rs2))))) => 13821 pARtype("AMOXOR.W",(aq,(rl,(rd,(rs1,rs2))))) 13822 | AMO(AMOAND_W(aq,(rl,(rd,(rs1,rs2))))) => 13823 pARtype("AMOAND.W",(aq,(rl,(rd,(rs1,rs2))))) 13824 | AMO(AMOOR_W(aq,(rl,(rd,(rs1,rs2))))) => 13825 pARtype("AMOOR.W",(aq,(rl,(rd,(rs1,rs2))))) 13826 | AMO(AMOMIN_W(aq,(rl,(rd,(rs1,rs2))))) => 13827 pARtype("AMOMIN.W",(aq,(rl,(rd,(rs1,rs2))))) 13828 | AMO(AMOMAX_W(aq,(rl,(rd,(rs1,rs2))))) => 13829 pARtype("AMOMAX.W",(aq,(rl,(rd,(rs1,rs2))))) 13830 | AMO(AMOMINU_W(aq,(rl,(rd,(rs1,rs2))))) => 13831 pARtype("AMOMINU.W",(aq,(rl,(rd,(rs1,rs2))))) 13832 | AMO(AMOMAXU_W(aq,(rl,(rd,(rs1,rs2))))) => 13833 pARtype("AMOMAXU.W",(aq,(rl,(rd,(rs1,rs2))))) 13834 | AMO(AMOSWAP_D(aq,(rl,(rd,(rs1,rs2))))) => 13835 pARtype("AMOSWAP.D",(aq,(rl,(rd,(rs1,rs2))))) 13836 | AMO(AMOADD_D(aq,(rl,(rd,(rs1,rs2))))) => 13837 pARtype("AMOADD.D",(aq,(rl,(rd,(rs1,rs2))))) 13838 | AMO(AMOXOR_D(aq,(rl,(rd,(rs1,rs2))))) => 13839 pARtype("AMOXOR.D",(aq,(rl,(rd,(rs1,rs2))))) 13840 | AMO(AMOAND_D(aq,(rl,(rd,(rs1,rs2))))) => 13841 pARtype("AMOAND.D",(aq,(rl,(rd,(rs1,rs2))))) 13842 | AMO(AMOOR_D(aq,(rl,(rd,(rs1,rs2))))) => 13843 pARtype("AMOOR.D",(aq,(rl,(rd,(rs1,rs2))))) 13844 | AMO(AMOMIN_D(aq,(rl,(rd,(rs1,rs2))))) => 13845 pARtype("AMOMIN.D",(aq,(rl,(rd,(rs1,rs2))))) 13846 | AMO(AMOMAX_D(aq,(rl,(rd,(rs1,rs2))))) => 13847 pARtype("AMOMAX.D",(aq,(rl,(rd,(rs1,rs2))))) 13848 | AMO(AMOMINU_D(aq,(rl,(rd,(rs1,rs2))))) => 13849 pARtype("AMOMINU.D",(aq,(rl,(rd,(rs1,rs2))))) 13850 | AMO(AMOMAXU_D(aq,(rl,(rd,(rs1,rs2))))) => 13851 pARtype("AMOMAXU.D",(aq,(rl,(rd,(rs1,rs2))))) 13852 | System ECALL => pN0type "ECALL" 13853 | System EBREAK => pN0type "EBREAK" 13854 | System ERET => pN0type "ERET" 13855 | System MRTS => pN0type "MRTS" 13856 | System WFI => pN0type "WFI" 13857 | System(CSRRW(rd,(rs1,csr))) => pCSRtype("CSRRW",(rd,(rs1,csr))) 13858 | System(CSRRS(rd,(rs1,csr))) => pCSRtype("CSRRS",(rd,(rs1,csr))) 13859 | System(CSRRC(rd,(rs1,csr))) => pCSRtype("CSRRC",(rd,(rs1,csr))) 13860 | System(CSRRWI(rd,(imm,csr))) => pCSRItype 5 ("CSRRWI",(rd,(imm,csr))) 13861 | System(CSRRSI(rd,(imm,csr))) => pCSRItype 5 ("CSRRSI",(rd,(imm,csr))) 13862 | System(CSRRCI(rd,(imm,csr))) => pCSRItype 5 ("CSRRCI",(rd,(imm,csr))) 13863 | System(SFENCE_VM rs1) => pN1type("SFENCE.VM",rs1) 13864 | UnknownInstruction => pN0type "UNKNOWN" 13865 | Internal(FETCH_MISALIGNED _) => pN0type "FETCH_MISALIGNED" 13866 | Internal(FETCH_FAULT _) => pN0type "FETCH_FAULT"; 13867 13868fun Rtype (o',(f3,(rd,(rs1,(rs2,f7))))) = 13869 BitsN.concat[f7,rs2,rs1,f3,rd,o']; 13870 13871fun R4type (o',(f3,(rd,(rs1,(rs2,(rs3,f2)))))) = 13872 BitsN.concat[rs3,f2,rs2,rs1,f3,rd,o']; 13873 13874fun Itype (o',(f3,(rd,(rs1,imm)))) = BitsN.concat[imm,rs1,f3,rd,o']; 13875 13876fun Stype (o',(f3,(rs1,(rs2,imm)))) = 13877 BitsN.concat[BitsN.bits(11,5) imm,rs2,rs1,f3,BitsN.bits(4,0) imm,o']; 13878 13879fun SBtype (o',(f3,(rs1,(rs2,imm)))) = 13880 BitsN.concat 13881 [BitsN.fromBit(BitsN.bit(imm,11)),BitsN.bits(9,4) imm,rs2,rs1,f3, 13882 BitsN.bits(3,0) imm,BitsN.fromBit(BitsN.bit(imm,10)),o']; 13883 13884fun Utype (o',(rd,imm)) = BitsN.concat[imm,rd,o']; 13885 13886fun UJtype (o',(rd,imm)) = 13887 BitsN.concat 13888 [BitsN.fromBit(BitsN.bit(imm,19)),BitsN.bits(9,0) imm, 13889 BitsN.fromBit(BitsN.bit(imm,10)),BitsN.bits(18,11) imm,rd,o']; 13890 13891fun opc code = BitsN.@@(BitsN.bits(4,0) code,BitsN.B(0x3,2)); 13892 13893fun amofunc (code,(aq,rl)) = BitsN.concat[code,aq,rl]; 13894 13895fun Encode i = 13896 case i of 13897 Branch(BEQ(rs1,(rs2,imm))) => 13898 SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x0,3),(rs1,(rs2,imm)))) 13899 | Branch(BNE(rs1,(rs2,imm))) => 13900 SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x1,3),(rs1,(rs2,imm)))) 13901 | Branch(BLT(rs1,(rs2,imm))) => 13902 SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x4,3),(rs1,(rs2,imm)))) 13903 | Branch(BGE(rs1,(rs2,imm))) => 13904 SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x5,3),(rs1,(rs2,imm)))) 13905 | Branch(BLTU(rs1,(rs2,imm))) => 13906 SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x6,3),(rs1,(rs2,imm)))) 13907 | Branch(BGEU(rs1,(rs2,imm))) => 13908 SBtype(opc(BitsN.B(0x18,8)),(BitsN.B(0x7,3),(rs1,(rs2,imm)))) 13909 | Branch(JALR(rd,(rs1,imm))) => 13910 Itype(opc(BitsN.B(0x19,8)),(BitsN.B(0x0,3),(rd,(rs1,imm)))) 13911 | Branch(JAL(rd,imm)) => UJtype(opc(BitsN.B(0x1B,8)),(rd,imm)) 13912 | ArithI(LUI(rd,imm)) => Utype(opc(BitsN.B(0xD,8)),(rd,imm)) 13913 | ArithI(AUIPC(rd,imm)) => Utype(opc(BitsN.B(0x5,8)),(rd,imm)) 13914 | ArithI(ADDI(rd,(rs1,imm))) => 13915 Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x0,3),(rd,(rs1,imm)))) 13916 | Shift(SLLI(rd,(rs1,imm))) => 13917 Itype 13918 (opc(BitsN.B(0x4,8)), 13919 (BitsN.B(0x1,3),(rd,(rs1,BitsN.@@(BitsN.B(0x0,6),imm))))) 13920 | ArithI(SLTI(rd,(rs1,imm))) => 13921 Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x2,3),(rd,(rs1,imm)))) 13922 | ArithI(SLTIU(rd,(rs1,imm))) => 13923 Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x3,3),(rd,(rs1,imm)))) 13924 | ArithI(XORI(rd,(rs1,imm))) => 13925 Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x4,3),(rd,(rs1,imm)))) 13926 | Shift(SRLI(rd,(rs1,imm))) => 13927 Itype 13928 (opc(BitsN.B(0x4,8)), 13929 (BitsN.B(0x5,3),(rd,(rs1,BitsN.@@(BitsN.B(0x0,6),imm))))) 13930 | Shift(SRAI(rd,(rs1,imm))) => 13931 Itype 13932 (opc(BitsN.B(0x4,8)), 13933 (BitsN.B(0x5,3),(rd,(rs1,BitsN.@@(BitsN.B(0x10,6),imm))))) 13934 | ArithI(ORI(rd,(rs1,imm))) => 13935 Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x6,3),(rd,(rs1,imm)))) 13936 | ArithI(ANDI(rd,(rs1,imm))) => 13937 Itype(opc(BitsN.B(0x4,8)),(BitsN.B(0x7,3),(rd,(rs1,imm)))) 13938 | ArithR(ADD(rd,(rs1,rs2))) => 13939 Rtype 13940 (opc(BitsN.B(0xC,8)), 13941 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13942 | ArithR(SUB(rd,(rs1,rs2))) => 13943 Rtype 13944 (opc(BitsN.B(0xC,8)), 13945 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x20,7)))))) 13946 | Shift(SLL(rd,(rs1,rs2))) => 13947 Rtype 13948 (opc(BitsN.B(0xC,8)), 13949 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13950 | ArithR(SLT(rd,(rs1,rs2))) => 13951 Rtype 13952 (opc(BitsN.B(0xC,8)), 13953 (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13954 | ArithR(SLTU(rd,(rs1,rs2))) => 13955 Rtype 13956 (opc(BitsN.B(0xC,8)), 13957 (BitsN.B(0x3,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13958 | ArithR(XOR(rd,(rs1,rs2))) => 13959 Rtype 13960 (opc(BitsN.B(0xC,8)), 13961 (BitsN.B(0x4,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13962 | Shift(SRL(rd,(rs1,rs2))) => 13963 Rtype 13964 (opc(BitsN.B(0xC,8)), 13965 (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13966 | Shift(SRA(rd,(rs1,rs2))) => 13967 Rtype 13968 (opc(BitsN.B(0xC,8)), 13969 (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x20,7)))))) 13970 | ArithR(OR(rd,(rs1,rs2))) => 13971 Rtype 13972 (opc(BitsN.B(0xC,8)), 13973 (BitsN.B(0x6,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13974 | ArithR(AND(rd,(rs1,rs2))) => 13975 Rtype 13976 (opc(BitsN.B(0xC,8)), 13977 (BitsN.B(0x7,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13978 | ArithI(ADDIW(rd,(rs1,imm))) => 13979 Itype(opc(BitsN.B(0x6,8)),(BitsN.B(0x0,3),(rd,(rs1,imm)))) 13980 | Shift(SLLIW(rd,(rs1,imm))) => 13981 Itype 13982 (opc(BitsN.B(0x6,8)), 13983 (BitsN.B(0x1,3),(rd,(rs1,BitsN.@@(BitsN.B(0x0,7),imm))))) 13984 | Shift(SRLIW(rd,(rs1,imm))) => 13985 Itype 13986 (opc(BitsN.B(0x6,8)), 13987 (BitsN.B(0x5,3),(rd,(rs1,BitsN.@@(BitsN.B(0x0,7),imm))))) 13988 | Shift(SRAIW(rd,(rs1,imm))) => 13989 Itype 13990 (opc(BitsN.B(0x6,8)), 13991 (BitsN.B(0x5,3),(rd,(rs1,BitsN.@@(BitsN.B(0x20,7),imm))))) 13992 | ArithR(ADDW(rd,(rs1,rs2))) => 13993 Rtype 13994 (opc(BitsN.B(0xE,8)), 13995 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 13996 | ArithR(SUBW(rd,(rs1,rs2))) => 13997 Rtype 13998 (opc(BitsN.B(0xE,8)), 13999 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x20,7)))))) 14000 | Shift(SLLW(rd,(rs1,rs2))) => 14001 Rtype 14002 (opc(BitsN.B(0xE,8)), 14003 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 14004 | Shift(SRLW(rd,(rs1,rs2))) => 14005 Rtype 14006 (opc(BitsN.B(0xE,8)), 14007 (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 14008 | Shift(SRAW(rd,(rs1,rs2))) => 14009 Rtype 14010 (opc(BitsN.B(0xE,8)), 14011 (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x20,7)))))) 14012 | MulDiv(MUL(rd,(rs1,rs2))) => 14013 Rtype 14014 (opc(BitsN.B(0xC,8)), 14015 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14016 | MulDiv(MULH(rd,(rs1,rs2))) => 14017 Rtype 14018 (opc(BitsN.B(0xC,8)), 14019 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14020 | MulDiv(MULHSU(rd,(rs1,rs2))) => 14021 Rtype 14022 (opc(BitsN.B(0xC,8)), 14023 (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14024 | MulDiv(MULHU(rd,(rs1,rs2))) => 14025 Rtype 14026 (opc(BitsN.B(0xC,8)), 14027 (BitsN.B(0x3,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14028 | MulDiv(DIV(rd,(rs1,rs2))) => 14029 Rtype 14030 (opc(BitsN.B(0xC,8)), 14031 (BitsN.B(0x4,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14032 | MulDiv(DIVU(rd,(rs1,rs2))) => 14033 Rtype 14034 (opc(BitsN.B(0xC,8)), 14035 (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14036 | MulDiv(REM(rd,(rs1,rs2))) => 14037 Rtype 14038 (opc(BitsN.B(0xC,8)), 14039 (BitsN.B(0x6,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14040 | MulDiv(REMU(rd,(rs1,rs2))) => 14041 Rtype 14042 (opc(BitsN.B(0xC,8)), 14043 (BitsN.B(0x7,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14044 | MulDiv(MULW(rd,(rs1,rs2))) => 14045 Rtype 14046 (opc(BitsN.B(0xE,8)), 14047 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14048 | MulDiv(DIVW(rd,(rs1,rs2))) => 14049 Rtype 14050 (opc(BitsN.B(0xE,8)), 14051 (BitsN.B(0x4,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14052 | MulDiv(DIVUW(rd,(rs1,rs2))) => 14053 Rtype 14054 (opc(BitsN.B(0xE,8)), 14055 (BitsN.B(0x5,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14056 | MulDiv(REMW(rd,(rs1,rs2))) => 14057 Rtype 14058 (opc(BitsN.B(0xE,8)), 14059 (BitsN.B(0x6,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14060 | MulDiv(REMUW(rd,(rs1,rs2))) => 14061 Rtype 14062 (opc(BitsN.B(0xE,8)), 14063 (BitsN.B(0x7,3),(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14064 | Load(LB(rd,(rs1,imm))) => 14065 Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x0,3),(rd,(rs1,imm)))) 14066 | Load(LH(rd,(rs1,imm))) => 14067 Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x1,3),(rd,(rs1,imm)))) 14068 | Load(LW(rd,(rs1,imm))) => 14069 Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x2,3),(rd,(rs1,imm)))) 14070 | Load(LD(rd,(rs1,imm))) => 14071 Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x3,3),(rd,(rs1,imm)))) 14072 | Load(LBU(rd,(rs1,imm))) => 14073 Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x4,3),(rd,(rs1,imm)))) 14074 | Load(LHU(rd,(rs1,imm))) => 14075 Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x5,3),(rd,(rs1,imm)))) 14076 | Load(LWU(rd,(rs1,imm))) => 14077 Itype(opc(BitsN.B(0x0,8)),(BitsN.B(0x6,3),(rd,(rs1,imm)))) 14078 | Store(SB(rs1,(rs2,imm))) => 14079 Stype(opc(BitsN.B(0x8,8)),(BitsN.B(0x0,3),(rs1,(rs2,imm)))) 14080 | Store(SH(rs1,(rs2,imm))) => 14081 Stype(opc(BitsN.B(0x8,8)),(BitsN.B(0x1,3),(rs1,(rs2,imm)))) 14082 | Store(SW(rs1,(rs2,imm))) => 14083 Stype(opc(BitsN.B(0x8,8)),(BitsN.B(0x2,3),(rs1,(rs2,imm)))) 14084 | Store(SD(rs1,(rs2,imm))) => 14085 Stype(opc(BitsN.B(0x8,8)),(BitsN.B(0x3,3),(rs1,(rs2,imm)))) 14086 | FENCE(rd,(rs1,(pred,succ))) => 14087 Itype 14088 (opc(BitsN.B(0x3,8)), 14089 (BitsN.B(0x0,3),(rd,(rs1,BitsN.concat[BitsN.B(0x0,4),pred,succ])))) 14090 | FENCE_I(rd,(rs1,imm)) => 14091 Itype(opc(BitsN.B(0x3,8)),(BitsN.B(0x1,3),(rd,(rs1,imm)))) 14092 | FArith(FADD_S(rd,(rs1,(rs2,frm)))) => 14093 Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x0,7)))))) 14094 | FArith(FSUB_S(rd,(rs1,(rs2,frm)))) => 14095 Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x4,7)))))) 14096 | FArith(FMUL_S(rd,(rs1,(rs2,frm)))) => 14097 Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x8,7)))))) 14098 | FArith(FDIV_S(rd,(rs1,(rs2,frm)))) => 14099 Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0xC,7)))))) 14100 | FArith(FSQRT_S(rd,(rs,frm))) => 14101 Rtype 14102 (opc(BitsN.B(0x14,8)), 14103 (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x2C,7)))))) 14104 | FArith(FMIN_S(rd,(rs1,rs2))) => 14105 Rtype 14106 (opc(BitsN.B(0x14,8)), 14107 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x14,7)))))) 14108 | FArith(FMAX_S(rd,(rs1,rs2))) => 14109 Rtype 14110 (opc(BitsN.B(0x14,8)), 14111 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x14,7)))))) 14112 | FArith(FEQ_S(rd,(rs1,rs2))) => 14113 Rtype 14114 (opc(BitsN.B(0x14,8)), 14115 (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x50,7)))))) 14116 | FArith(FLT_S(rd,(rs1,rs2))) => 14117 Rtype 14118 (opc(BitsN.B(0x14,8)), 14119 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x50,7)))))) 14120 | FArith(FLE_S(rd,(rs1,rs2))) => 14121 Rtype 14122 (opc(BitsN.B(0x14,8)), 14123 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x50,7)))))) 14124 | FArith(FADD_D(rd,(rs1,(rs2,frm)))) => 14125 Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x1,7)))))) 14126 | FArith(FSUB_D(rd,(rs1,(rs2,frm)))) => 14127 Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x5,7)))))) 14128 | FArith(FMUL_D(rd,(rs1,(rs2,frm)))) => 14129 Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0x9,7)))))) 14130 | FArith(FDIV_D(rd,(rs1,(rs2,frm)))) => 14131 Rtype(opc(BitsN.B(0x14,8)),(frm,(rd,(rs1,(rs2,BitsN.B(0xD,7)))))) 14132 | FArith(FSQRT_D(rd,(rs,frm))) => 14133 Rtype 14134 (opc(BitsN.B(0x14,8)), 14135 (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x2D,7)))))) 14136 | FArith(FMIN_D(rd,(rs1,rs2))) => 14137 Rtype 14138 (opc(BitsN.B(0x14,8)), 14139 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x15,7)))))) 14140 | FArith(FMAX_D(rd,(rs1,rs2))) => 14141 Rtype 14142 (opc(BitsN.B(0x14,8)), 14143 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x15,7)))))) 14144 | FArith(FEQ_D(rd,(rs1,rs2))) => 14145 Rtype 14146 (opc(BitsN.B(0x14,8)), 14147 (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x51,7)))))) 14148 | FArith(FLT_D(rd,(rs1,rs2))) => 14149 Rtype 14150 (opc(BitsN.B(0x14,8)), 14151 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x51,7)))))) 14152 | FArith(FLE_D(rd,(rs1,rs2))) => 14153 Rtype 14154 (opc(BitsN.B(0x14,8)), 14155 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x51,7)))))) 14156 | FPLoad(FLW(rd,(rs1,imm))) => 14157 Itype(opc(BitsN.B(0x1,8)),(BitsN.B(0x2,3),(rd,(rs1,imm)))) 14158 | FPLoad(FLD(rd,(rs1,imm))) => 14159 Itype(opc(BitsN.B(0x1,8)),(BitsN.B(0x3,3),(rd,(rs1,imm)))) 14160 | FPStore(FSW(rs1,(rs2,imm))) => 14161 Stype(opc(BitsN.B(0x9,8)),(BitsN.B(0x2,3),(rs1,(rs2,imm)))) 14162 | FPStore(FSD(rs1,(rs2,imm))) => 14163 Stype(opc(BitsN.B(0x9,8)),(BitsN.B(0x3,3),(rs1,(rs2,imm)))) 14164 | FArith(FMADD_S(rd,(rs1,(rs2,(rs3,frm))))) => 14165 R4type 14166 (opc(BitsN.B(0x10,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x0,2))))))) 14167 | FArith(FMSUB_S(rd,(rs1,(rs2,(rs3,frm))))) => 14168 R4type 14169 (opc(BitsN.B(0x11,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x0,2))))))) 14170 | FArith(FNMSUB_S(rd,(rs1,(rs2,(rs3,frm))))) => 14171 R4type 14172 (opc(BitsN.B(0x12,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x0,2))))))) 14173 | FArith(FNMADD_S(rd,(rs1,(rs2,(rs3,frm))))) => 14174 R4type 14175 (opc(BitsN.B(0x13,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x0,2))))))) 14176 | FArith(FMADD_D(rd,(rs1,(rs2,(rs3,frm))))) => 14177 R4type 14178 (opc(BitsN.B(0x10,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x1,2))))))) 14179 | FArith(FMSUB_D(rd,(rs1,(rs2,(rs3,frm))))) => 14180 R4type 14181 (opc(BitsN.B(0x11,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x1,2))))))) 14182 | FArith(FNMSUB_D(rd,(rs1,(rs2,(rs3,frm))))) => 14183 R4type 14184 (opc(BitsN.B(0x12,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x1,2))))))) 14185 | FArith(FNMADD_D(rd,(rs1,(rs2,(rs3,frm))))) => 14186 R4type 14187 (opc(BitsN.B(0x13,8)),(frm,(rd,(rs1,(rs2,(rs3,BitsN.B(0x1,2))))))) 14188 | FConv(FSGNJ_S(rd,(rs1,rs2))) => 14189 Rtype 14190 (opc(BitsN.B(0x14,8)), 14191 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x10,7)))))) 14192 | FConv(FSGNJN_S(rd,(rs1,rs2))) => 14193 Rtype 14194 (opc(BitsN.B(0x14,8)), 14195 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x10,7)))))) 14196 | FConv(FSGNJX_S(rd,(rs1,rs2))) => 14197 Rtype 14198 (opc(BitsN.B(0x14,8)), 14199 (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x10,7)))))) 14200 | FConv(FCVT_W_S(rd,(rs,frm))) => 14201 Rtype 14202 (opc(BitsN.B(0x14,8)), 14203 (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x60,7)))))) 14204 | FConv(FCVT_WU_S(rd,(rs,frm))) => 14205 Rtype 14206 (opc(BitsN.B(0x14,8)), 14207 (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x60,7)))))) 14208 | FConv(FMV_X_S(rd,rs)) => 14209 Rtype 14210 (opc(BitsN.B(0x14,8)), 14211 (BitsN.B(0x0,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x70,7)))))) 14212 | FConv(FCLASS_S(rd,rs)) => 14213 Rtype 14214 (opc(BitsN.B(0x14,8)), 14215 (BitsN.B(0x1,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x70,7)))))) 14216 | FConv(FCVT_S_W(rd,(rs,frm))) => 14217 Rtype 14218 (opc(BitsN.B(0x14,8)), 14219 (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x68,7)))))) 14220 | FConv(FCVT_S_WU(rd,(rs,frm))) => 14221 Rtype 14222 (opc(BitsN.B(0x14,8)), 14223 (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x68,7)))))) 14224 | FConv(FMV_S_X(rd,rs)) => 14225 Rtype 14226 (opc(BitsN.B(0x14,8)), 14227 (BitsN.B(0x0,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x78,7)))))) 14228 | FConv(FSGNJ_D(rd,(rs1,rs2))) => 14229 Rtype 14230 (opc(BitsN.B(0x14,8)), 14231 (BitsN.B(0x0,3),(rd,(rs1,(rs2,BitsN.B(0x11,7)))))) 14232 | FConv(FSGNJN_D(rd,(rs1,rs2))) => 14233 Rtype 14234 (opc(BitsN.B(0x14,8)), 14235 (BitsN.B(0x1,3),(rd,(rs1,(rs2,BitsN.B(0x11,7)))))) 14236 | FConv(FSGNJX_D(rd,(rs1,rs2))) => 14237 Rtype 14238 (opc(BitsN.B(0x14,8)), 14239 (BitsN.B(0x2,3),(rd,(rs1,(rs2,BitsN.B(0x11,7)))))) 14240 | FConv(FCVT_W_D(rd,(rs,frm))) => 14241 Rtype 14242 (opc(BitsN.B(0x14,8)), 14243 (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x61,7)))))) 14244 | FConv(FCVT_WU_D(rd,(rs,frm))) => 14245 Rtype 14246 (opc(BitsN.B(0x14,8)), 14247 (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x61,7)))))) 14248 | FConv(FCLASS_D(rd,rs)) => 14249 Rtype 14250 (opc(BitsN.B(0x14,8)), 14251 (BitsN.B(0x1,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x71,7)))))) 14252 | FConv(FCVT_D_W(rd,(rs,frm))) => 14253 Rtype 14254 (opc(BitsN.B(0x14,8)), 14255 (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x69,7)))))) 14256 | FConv(FCVT_D_WU(rd,(rs,frm))) => 14257 Rtype 14258 (opc(BitsN.B(0x14,8)), 14259 (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x69,7)))))) 14260 | FConv(FCVT_S_D(rd,(rs,frm))) => 14261 Rtype 14262 (opc(BitsN.B(0x14,8)), 14263 (frm,(rd,(rs,(BitsN.B(0x1,5),BitsN.B(0x20,7)))))) 14264 | FConv(FCVT_D_S(rd,(rs,frm))) => 14265 Rtype 14266 (opc(BitsN.B(0x14,8)), 14267 (frm,(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x21,7)))))) 14268 | FConv(FCVT_L_S(rd,(rs,frm))) => 14269 Rtype 14270 (opc(BitsN.B(0x14,8)), 14271 (frm,(rd,(rs,(BitsN.B(0x2,5),BitsN.B(0x60,7)))))) 14272 | FConv(FCVT_LU_S(rd,(rs,frm))) => 14273 Rtype 14274 (opc(BitsN.B(0x14,8)), 14275 (frm,(rd,(rs,(BitsN.B(0x3,5),BitsN.B(0x60,7)))))) 14276 | FConv(FCVT_S_L(rd,(rs,frm))) => 14277 Rtype 14278 (opc(BitsN.B(0x14,8)), 14279 (frm,(rd,(rs,(BitsN.B(0x2,5),BitsN.B(0x68,7)))))) 14280 | FConv(FCVT_S_LU(rd,(rs,frm))) => 14281 Rtype 14282 (opc(BitsN.B(0x14,8)), 14283 (frm,(rd,(rs,(BitsN.B(0x3,5),BitsN.B(0x68,7)))))) 14284 | FConv(FCVT_L_D(rd,(rs,frm))) => 14285 Rtype 14286 (opc(BitsN.B(0x14,8)), 14287 (frm,(rd,(rs,(BitsN.B(0x2,5),BitsN.B(0x61,7)))))) 14288 | FConv(FCVT_LU_D(rd,(rs,frm))) => 14289 Rtype 14290 (opc(BitsN.B(0x14,8)), 14291 (frm,(rd,(rs,(BitsN.B(0x3,5),BitsN.B(0x61,7)))))) 14292 | FConv(FMV_X_D(rd,rs)) => 14293 Rtype 14294 (opc(BitsN.B(0x14,8)), 14295 (BitsN.B(0x0,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x71,7)))))) 14296 | FConv(FCVT_D_L(rd,(rs,frm))) => 14297 Rtype 14298 (opc(BitsN.B(0x14,8)), 14299 (frm,(rd,(rs,(BitsN.B(0x2,5),BitsN.B(0x69,7)))))) 14300 | FConv(FCVT_D_LU(rd,(rs,frm))) => 14301 Rtype 14302 (opc(BitsN.B(0x14,8)), 14303 (frm,(rd,(rs,(BitsN.B(0x3,5),BitsN.B(0x69,7)))))) 14304 | FConv(FMV_D_X(rd,rs)) => 14305 Rtype 14306 (opc(BitsN.B(0x14,8)), 14307 (BitsN.B(0x0,3),(rd,(rs,(BitsN.B(0x0,5),BitsN.B(0x79,7)))))) 14308 | AMO(LR_W(aq,(rl,(rd,rs1)))) => 14309 Rtype 14310 (opc(BitsN.B(0xB,8)), 14311 (BitsN.B(0x2,3), 14312 (rd,(rs1,(BitsN.B(0x0,5),amofunc(BitsN.B(0x2,5),(aq,rl))))))) 14313 | AMO(LR_D(aq,(rl,(rd,rs1)))) => 14314 Rtype 14315 (opc(BitsN.B(0xB,8)), 14316 (BitsN.B(0x3,3), 14317 (rd,(rs1,(BitsN.B(0x0,5),amofunc(BitsN.B(0x2,5),(aq,rl))))))) 14318 | AMO(SC_W(aq,(rl,(rd,(rs1,rs2))))) => 14319 Rtype 14320 (opc(BitsN.B(0xB,8)), 14321 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x3,5),(aq,rl))))))) 14322 | AMO(SC_D(aq,(rl,(rd,(rs1,rs2))))) => 14323 Rtype 14324 (opc(BitsN.B(0xB,8)), 14325 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x2,5),(aq,rl))))))) 14326 | AMO(AMOSWAP_W(aq,(rl,(rd,(rs1,rs2))))) => 14327 Rtype 14328 (opc(BitsN.B(0xB,8)), 14329 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x1,5),(aq,rl))))))) 14330 | AMO(AMOADD_W(aq,(rl,(rd,(rs1,rs2))))) => 14331 Rtype 14332 (opc(BitsN.B(0xB,8)), 14333 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x0,5),(aq,rl))))))) 14334 | AMO(AMOXOR_W(aq,(rl,(rd,(rs1,rs2))))) => 14335 Rtype 14336 (opc(BitsN.B(0xB,8)), 14337 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x4,5),(aq,rl))))))) 14338 | AMO(AMOAND_W(aq,(rl,(rd,(rs1,rs2))))) => 14339 Rtype 14340 (opc(BitsN.B(0xB,8)), 14341 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0xC,5),(aq,rl))))))) 14342 | AMO(AMOOR_W(aq,(rl,(rd,(rs1,rs2))))) => 14343 Rtype 14344 (opc(BitsN.B(0xB,8)), 14345 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x8,5),(aq,rl))))))) 14346 | AMO(AMOMIN_W(aq,(rl,(rd,(rs1,rs2))))) => 14347 Rtype 14348 (opc(BitsN.B(0xB,8)), 14349 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x10,5),(aq,rl))))))) 14350 | AMO(AMOMAX_W(aq,(rl,(rd,(rs1,rs2))))) => 14351 Rtype 14352 (opc(BitsN.B(0xB,8)), 14353 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x14,5),(aq,rl))))))) 14354 | AMO(AMOMINU_W(aq,(rl,(rd,(rs1,rs2))))) => 14355 Rtype 14356 (opc(BitsN.B(0xB,8)), 14357 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x18,5),(aq,rl))))))) 14358 | AMO(AMOMAXU_W(aq,(rl,(rd,(rs1,rs2))))) => 14359 Rtype 14360 (opc(BitsN.B(0xB,8)), 14361 (BitsN.B(0x2,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x1C,5),(aq,rl))))))) 14362 | AMO(AMOSWAP_D(aq,(rl,(rd,(rs1,rs2))))) => 14363 Rtype 14364 (opc(BitsN.B(0xB,8)), 14365 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x1,5),(aq,rl))))))) 14366 | AMO(AMOADD_D(aq,(rl,(rd,(rs1,rs2))))) => 14367 Rtype 14368 (opc(BitsN.B(0xB,8)), 14369 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x0,5),(aq,rl))))))) 14370 | AMO(AMOXOR_D(aq,(rl,(rd,(rs1,rs2))))) => 14371 Rtype 14372 (opc(BitsN.B(0xB,8)), 14373 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x4,5),(aq,rl))))))) 14374 | AMO(AMOAND_D(aq,(rl,(rd,(rs1,rs2))))) => 14375 Rtype 14376 (opc(BitsN.B(0xB,8)), 14377 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0xC,5),(aq,rl))))))) 14378 | AMO(AMOOR_D(aq,(rl,(rd,(rs1,rs2))))) => 14379 Rtype 14380 (opc(BitsN.B(0xB,8)), 14381 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x8,5),(aq,rl))))))) 14382 | AMO(AMOMIN_D(aq,(rl,(rd,(rs1,rs2))))) => 14383 Rtype 14384 (opc(BitsN.B(0xB,8)), 14385 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x10,5),(aq,rl))))))) 14386 | AMO(AMOMAX_D(aq,(rl,(rd,(rs1,rs2))))) => 14387 Rtype 14388 (opc(BitsN.B(0xB,8)), 14389 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x14,5),(aq,rl))))))) 14390 | AMO(AMOMINU_D(aq,(rl,(rd,(rs1,rs2))))) => 14391 Rtype 14392 (opc(BitsN.B(0xB,8)), 14393 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x18,5),(aq,rl))))))) 14394 | AMO(AMOMAXU_D(aq,(rl,(rd,(rs1,rs2))))) => 14395 Rtype 14396 (opc(BitsN.B(0xB,8)), 14397 (BitsN.B(0x3,3),(rd,(rs1,(rs2,amofunc(BitsN.B(0x1C,5),(aq,rl))))))) 14398 | System ECALL => 14399 Itype 14400 (opc(BitsN.B(0x1C,8)), 14401 (BitsN.B(0x0,3),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x0,12))))) 14402 | System EBREAK => 14403 Itype 14404 (opc(BitsN.B(0x1C,8)), 14405 (BitsN.B(0x0,3),(BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x1,12))))) 14406 | System ERET => 14407 Itype 14408 (opc(BitsN.B(0x1C,8)), 14409 (BitsN.B(0x0,3), 14410 (BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x100,12))))) 14411 | System MRTS => 14412 Itype 14413 (opc(BitsN.B(0x1C,8)), 14414 (BitsN.B(0x0,3), 14415 (BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x305,12))))) 14416 | System WFI => 14417 Itype 14418 (opc(BitsN.B(0x1C,8)), 14419 (BitsN.B(0x0,3), 14420 (BitsN.B(0x0,5),(BitsN.B(0x0,5),BitsN.B(0x102,12))))) 14421 | System(SFENCE_VM rs1) => 14422 Itype 14423 (opc(BitsN.B(0x1C,8)), 14424 (BitsN.B(0x0,3),(BitsN.B(0x0,5),(rs1,BitsN.B(0x101,12))))) 14425 | System(CSRRW(rd,(rs1,csr))) => 14426 Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x1,3),(rd,(rs1,csr)))) 14427 | System(CSRRS(rd,(rs1,csr))) => 14428 Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x2,3),(rd,(rs1,csr)))) 14429 | System(CSRRC(rd,(rs1,csr))) => 14430 Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x3,3),(rd,(rs1,csr)))) 14431 | System(CSRRWI(rd,(imm,csr))) => 14432 Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x5,3),(rd,(imm,csr)))) 14433 | System(CSRRSI(rd,(imm,csr))) => 14434 Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x6,3),(rd,(imm,csr)))) 14435 | System(CSRRCI(rd,(imm,csr))) => 14436 Itype(opc(BitsN.B(0x1C,8)),(BitsN.B(0x7,3),(rd,(imm,csr)))) 14437 | UnknownInstruction => BitsN.B(0x0,32) 14438 | Internal(FETCH_MISALIGNED _) => BitsN.B(0x0,32) 14439 | Internal(FETCH_FAULT _) => BitsN.B(0x0,32); 14440 14441fun log_instruction (w,inst) = 14442 String.concat 14443 ["instr ",BitsN.toHexString (!procID)," ", 14444 Nat.toString 14445 (BitsN.toNat(Map.lookup((!c_instret),BitsN.toNat (!procID)))), 14446 " 0x",hex64(PC ())," : ",hex32 w," ",instructionToString inst]; 14447 14448fun exitCode () = BitsN.toNat(ExitCode ()); 14449 14450val CYCLES_PER_TIMER_TICK = 200 14451 14452fun tickClock () = 14453 let 14454 val cycles = 14455 BitsN.+ 14456 (Map.lookup((!c_cycles),BitsN.toNat (!procID)),BitsN.B(0x1,64)) 14457 in 14458 ( c_cycles := (Map.update((!c_cycles),BitsN.toNat (!procID),cycles)) 14459 ; clock := (BitsN.div(cycles,BitsN.fromNat(CYCLES_PER_TIMER_TICK,64))) 14460 ) 14461 end; 14462 14463fun incrInstret () = 14464 c_instret := 14465 (Map.update 14466 ((!c_instret),BitsN.toNat (!procID), 14467 BitsN.+ 14468 (Map.lookup((!c_instret),BitsN.toNat (!procID)),BitsN.B(0x1,64)))); 14469 14470fun checkTimers () = 14471 ( if BitsN.>+ 14472 ((!clock), 14473 BitsN.+ 14474 (#mtimecmp((MCSR ()) : MachineCSR), 14475 #mtime_delta((MCSR ()) : MachineCSR))) 14476 then let 14477 val x = MCSR () 14478 val x0 = #mip(x : MachineCSR) 14479 in 14480 write'MCSR(MachineCSR_mip_rupd(x,mip_MTIP_rupd(x0,true))) 14481 end 14482 else () 14483 ; if BitsN.>+ 14484 ((!clock), 14485 BitsN.+ 14486 (#stimecmp((SCSR ()) : SupervisorCSR), 14487 #stime_delta((SCSR ()) : SupervisorCSR))) 14488 then let 14489 val x = MCSR () 14490 val x0 = #mip(x : MachineCSR) 14491 in 14492 write'MCSR(MachineCSR_mip_rupd(x,mip_STIP_rupd(x0,true))) 14493 end 14494 else () 14495 ); 14496 14497fun Next () = 14498 ( clear_logs () 14499 ; if not((#mtohost((MCSR ()) : MachineCSR)) = (BitsN.B(0x0,64))) 14500 then ( log := 14501 ((0,log_tohost(#mtohost((MCSR ()) : MachineCSR))) :: (!log)) 14502 ; if BitsN.bit(#mtohost((MCSR ()) : MachineCSR),0) 14503 then ( done := true 14504 ; write'ExitCode 14505 (BitsN.>>(#mtohost((MCSR ()) : MachineCSR),1)) 14506 ) 14507 else let 14508 val x = MCSR () 14509 in 14510 write'MCSR(MachineCSR_mtohost_rupd(x,BitsN.B(0x0,64))) 14511 end 14512 ) 14513 else () 14514 ; case Fetch () of 14515 F_Result w => 14516 let 14517 val inst = Decode w 14518 in 14519 ( log := ((1,log_instruction(w,inst)) :: (!log)); Run inst ) 14520 end 14521 | F_Error inst => 14522 ( log := ((1,log_instruction(BitsN.B(0x0,32),inst)) :: (!log)) 14523 ; Run inst 14524 ) 14525 ; checkTimers () 14526 ; case (NextFetch (),checkInterrupts ()) of 14527 (NONE,NONE) => 14528 ( incrInstret (); write'PC(BitsN.+(PC (),BitsN.B(0x4,64))) ) 14529 | (NONE,Option.SOME(i,p)) => 14530 ( incrInstret () 14531 ; takeTrap 14532 (true, 14533 (interruptIndex i,(BitsN.+(PC (),BitsN.B(0x4,64)),(NONE,p)))) 14534 ) 14535 | (Option.SOME(BranchTo addr),_) => 14536 ( incrInstret (); write'NextFetch NONE; write'PC addr ) 14537 | (Option.SOME Ereturn,_) => 14538 ( incrInstret () 14539 ; write'NextFetch NONE 14540 ; write'PC(curEPC ()) 14541 ; let 14542 val from = curPrivilege () 14543 in 14544 ( let 14545 val x = MCSR () 14546 in 14547 write'MCSR 14548 (MachineCSR_mstatus_rupd 14549 (x,popPrivilegeStack(#mstatus((MCSR ()) : MachineCSR)))) 14550 end 14551 ; let 14552 val to = curPrivilege () 14553 in 14554 log := 14555 ((1, 14556 String.concat 14557 ["exception return from ",privName from," to ", 14558 privName to]) 14559 :: 14560 (!log)) 14561 end 14562 ) 14563 end 14564 ) 14565 | (Option.SOME(Trap t),_) => 14566 ( write'NextFetch NONE 14567 ; takeTrap 14568 (false, 14569 (excCode(#trap(t : SynchronousTrap)), 14570 (PC (),(#badaddr(t : SynchronousTrap),Machine)))) 14571 ) 14572 | (Option.SOME Mrts,_) => 14573 ( incrInstret () 14574 ; write'NextFetch NONE 14575 ; write'PC(#stvec((SCSR ()) : SupervisorCSR)) 14576 ) 14577 ; tickClock () 14578 ); 14579 14580fun initIdent arch = 14581 ( let 14582 val x = MCSR () 14583 val x0 = #mcpuid(x : MachineCSR) 14584 in 14585 write'MCSR 14586 (MachineCSR_mcpuid_rupd(x,mcpuid_ArchBase_rupd(x0,archBase arch))) 14587 end 14588 ; let 14589 val x = MCSR () 14590 val x0 = #mcpuid(x : MachineCSR) 14591 in 14592 write'MCSR(MachineCSR_mcpuid_rupd(x,mcpuid_U_rupd(x0,true))) 14593 end 14594 ; let 14595 val x = MCSR () 14596 val x0 = #mcpuid(x : MachineCSR) 14597 in 14598 write'MCSR(MachineCSR_mcpuid_rupd(x,mcpuid_S_rupd(x0,true))) 14599 end 14600 ; let 14601 val x = MCSR () 14602 val x0 = #mcpuid(x : MachineCSR) 14603 in 14604 write'MCSR(MachineCSR_mcpuid_rupd(x,mcpuid_M_rupd(x0,true))) 14605 end 14606 ; let 14607 val x = MCSR () 14608 val x0 = #mcpuid(x : MachineCSR) 14609 in 14610 write'MCSR(MachineCSR_mcpuid_rupd(x,mcpuid_I_rupd(x0,true))) 14611 end 14612 ; let 14613 val x = MCSR () 14614 val x0 = #mimpid(x : MachineCSR) 14615 in 14616 write'MCSR 14617 (MachineCSR_mimpid_rupd 14618 (x,mimpid_RVSource_rupd(x0,BitsN.B(0x8000,16)))) 14619 end 14620 ; let 14621 val x = MCSR () 14622 val x0 = #mimpid(x : MachineCSR) 14623 in 14624 write'MCSR 14625 (MachineCSR_mimpid_rupd(x,mimpid_RVImpl_rupd(x0,BitsN.B(0x0,48)))) 14626 end 14627 ); 14628 14629fun initMachine hartid = 14630 ( let 14631 val x = MCSR () 14632 val x0 = #mstatus(x : MachineCSR) 14633 in 14634 write'MCSR 14635 (MachineCSR_mstatus_rupd(x,mstatus_VM_rupd(x0,vmMode Mbare))) 14636 end 14637 ; let 14638 val x = MCSR () 14639 val x0 = #mstatus(x : MachineCSR) 14640 in 14641 write'MCSR 14642 (MachineCSR_mstatus_rupd 14643 (x,mstatus_MPRV_rupd(x0,privLevel Machine))) 14644 end 14645 ; let 14646 val x = MCSR () 14647 val x0 = #mstatus(x : MachineCSR) 14648 in 14649 write'MCSR(MachineCSR_mstatus_rupd(x,mstatus_MIE_rupd(x0,false))) 14650 end 14651 ; let 14652 val x = MCSR () 14653 val x0 = #mstatus(x : MachineCSR) 14654 in 14655 write'MCSR 14656 (MachineCSR_mstatus_rupd 14657 (x,mstatus_MFS_rupd(x0,ext_status Initial))) 14658 end 14659 ; let 14660 val x = MCSR () 14661 val x0 = #mstatus(x : MachineCSR) 14662 in 14663 write'MCSR 14664 (MachineCSR_mstatus_rupd(x,mstatus_MXS_rupd(x0,ext_status Off))) 14665 end 14666 ; let 14667 val x = MCSR () 14668 val x0 = #mstatus(x : MachineCSR) 14669 in 14670 write'MCSR(MachineCSR_mstatus_rupd(x,mstatus_MSD_rupd(x0,false))) 14671 end 14672 ; let 14673 val x = MCSR () 14674 in 14675 write'MCSR(MachineCSR_mhartid_rupd(x,BitsN.zeroExtend 64 hartid)) 14676 end 14677 ; let 14678 val x = MCSR () 14679 in 14680 write'MCSR 14681 (MachineCSR_mtvec_rupd(x,BitsN.zeroExtend 64 (BitsN.B(0x100,16)))) 14682 end 14683 ); 14684 14685fun initRegs pc = 14686 ( L3.for 14687 (0,31, 14688 fn i => 14689 let 14690 val x = BitsN.fromNat(i,5) 14691 in 14692 write'gpr(BitsN.B(0x0,64),x) 14693 end) 14694 ; L3.for 14695 (0,31, 14696 fn i => 14697 let 14698 val x = BitsN.fromNat(i,5) 14699 in 14700 write'fpr(BitsN.B(0x0,64),x) 14701 end) 14702 ; write'PC(BitsN.fromNat(pc,64)) 14703 ; write'NextFetch NONE 14704 ; done := false 14705 ); 14706 14707end