1/*
2 * Copyright 2017, Data61
3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
4 * ABN 41 687 119 230.
5 *
6 * This software may be distributed and modified according to the terms of
7 * the BSD 2-Clause license. Note that NO WARRANTY is provided.
8 * See "LICENSE_BSD2.txt" for details.
9 *
10 * @TAG(DATA61_BSD)
11 */
12#pragma once
13
14#include <platsupport/gpio.h>
15#include <platsupport/plat/gpio.h>
16
17/** Sets a pin to either GPIO or SFIO (special function I/O) mode.
18 *
19 * Normally this functionality is provided by a Mux driver and not by a GPIO
20 * driver, but on the TK1, the GPIO controller actually controls this
21 * functionality. So the Mux driver calls on this function.
22 */
23int
24gpio_set_pad_mode(gpio_sys_t *gpio_sys,
25                  enum gpio_pin gpio, enum gpio_pad_mode mode, enum gpio_dir dir);
26
27/* These #defines here are register offsets within the pinmux_misc MMIO frame,
28 * for the pingroups.
29 *
30 * The pingroups are basically hardware-defined groupings of the pins, and
31 * setting attributes on these pingroups will affect all the pins which are part
32 * the targeted group.
33 */
34#define TK1MUX_GROUP_OFFSET_GMACFG                     (0x900)
35#define TK1MUX_GROUP_OFFSET_SDIO1CFG                   (0x8ec)
36#define TK1MUX_GROUP_OFFSET_SDIO3CFG                   (0x8b0)
37#define TK1MUX_GROUP_OFFSET_SDIO4CFG                   (0x9c4)
38#define TK1MUX_GROUP_OFFSET_AOCFG0                     (0x9b0)
39#define TK1MUX_GROUP_OFFSET_AOCFG1                     (0x868)
40#define TK1MUX_GROUP_OFFSET_AOCFG2                     (0x86c)
41#define TK1MUX_GROUP_OFFSET_AOCFG3                     (0x9a8)
42#define TK1MUX_GROUP_OFFSET_AOCFG4                     (0x9c8)
43#define TK1MUX_GROUP_OFFSET_CDEV1CFG                   (0x884)
44#define TK1MUX_GROUP_OFFSET_CDEV2CFG                   (0x888)
45#define TK1MUX_GROUP_OFFSET_CECCFG                     (0x938)
46#define TK1MUX_GROUP_OFFSET_DAP1CFG                    (0x890)
47#define TK1MUX_GROUP_OFFSET_DAP2CFG                    (0x894)
48#define TK1MUX_GROUP_OFFSET_DAP3CFG                    (0x898)
49#define TK1MUX_GROUP_OFFSET_DAP4CFG                    (0x89c)
50#define TK1MUX_GROUP_OFFSET_DAP5CFG                    (0x998)
51#define TK1MUX_GROUP_OFFSET_DBGCFG                     (0x8a0)
52#define TK1MUX_GROUP_OFFSET_DDCCFG                     (0x8fc)
53#define TK1MUX_GROUP_OFFSET_DEV3CFG                    (0x92c)
54#define TK1MUX_GROUP_OFFSET_OWRCFG                     (0x920)
55#define TK1MUX_GROUP_OFFSET_SPICFG                     (0x8b4)
56#define TK1MUX_GROUP_OFFSET_UAACFG                     (0x8b8)
57#define TK1MUX_GROUP_OFFSET_UABCFG                     (0x8bc)
58#define TK1MUX_GROUP_OFFSET_UART2CFG                   (0x8c0)
59#define TK1MUX_GROUP_OFFSET_UART3CFG                   (0x8c4)
60#define TK1MUX_GROUP_OFFSET_UDACFG                     (0x924)
61#define TK1MUX_GROUP_OFFSET_ATCFG1                     (0x870)
62#define TK1MUX_GROUP_OFFSET_ATCFG2                     (0x874)
63#define TK1MUX_GROUP_OFFSET_ATCFG3                     (0x878)
64#define TK1MUX_GROUP_OFFSET_ATCFG4                     (0x87c)
65#define TK1MUX_GROUP_OFFSET_ATCFG5                     (0x880)
66#define TK1MUX_GROUP_OFFSET_ATCFG6                     (0x994)
67#define TK1MUX_GROUP_OFFSET_GMECFG                     (0x910)
68#define TK1MUX_GROUP_OFFSET_GMFCFG                     (0x914)
69#define TK1MUX_GROUP_OFFSET_GMGCFG                     (0x918)
70#define TK1MUX_GROUP_OFFSET_GMHCFG                     (0x91c)
71#define TK1MUX_GROUP_OFFSET_HVCFG0                     (0x9b4)
72#define TK1MUX_GROUP_OFFSET_GPVCFG                     (0x928)
73#define TK1MUX_GROUP_OFFSET_USB_VBUS_EN_CFG            (0x99c)
74
75/* These #defines are shorthand for the above ones so we don't have to use their
76 * long names.
77 */
78#define GMACFG TK1MUX_GROUP_OFFSET_GMACFG
79#define SDIO1CFG TK1MUX_GROUP_OFFSET_SDIO1CFG
80#define SDIO3CFG TK1MUX_GROUP_OFFSET_SDIO3CFG
81#define SDIO4CFG TK1MUX_GROUP_OFFSET_SDIO4CFG
82#define AOCFG0 TK1MUX_GROUP_OFFSET_AOCFG0
83#define AOCFG1 TK1MUX_GROUP_OFFSET_AOCFG1
84#define AOCFG2 TK1MUX_GROUP_OFFSET_AOCFG2
85#define AOCFG3 TK1MUX_GROUP_OFFSET_AOCFG3
86#define AOCFG4 TK1MUX_GROUP_OFFSET_AOCFG4
87#define CDEV1CFG TK1MUX_GROUP_OFFSET_CDEV1CFG
88#define CDEV2CFG TK1MUX_GROUP_OFFSET_CDEV2CFG
89#define CECCFG TK1MUX_GROUP_OFFSET_CECCFG
90#define DAP1CFG TK1MUX_GROUP_OFFSET_DAP1CFG
91#define DAP2CFG TK1MUX_GROUP_OFFSET_DAP2CFG
92#define DAP3CFG TK1MUX_GROUP_OFFSET_DAP3CFG
93#define DAP4CFG TK1MUX_GROUP_OFFSET_DAP4CFG
94#define DAP5CFG TK1MUX_GROUP_OFFSET_DAP5CFG
95#define DBGCFG TK1MUX_GROUP_OFFSET_DBGCFG
96#define DDCCFG TK1MUX_GROUP_OFFSET_DDCCFG
97#define DEV3CFG TK1MUX_GROUP_OFFSET_DEV3CFG
98#define OWRCFG TK1MUX_GROUP_OFFSET_OWRCFG
99#define SPICFG TK1MUX_GROUP_OFFSET_SPICFG
100#define UAACFG TK1MUX_GROUP_OFFSET_UAACFG
101#define UABCFG TK1MUX_GROUP_OFFSET_UABCFG
102#define UART2CFG TK1MUX_GROUP_OFFSET_UART2CFG
103#define UART3CFG TK1MUX_GROUP_OFFSET_UART3CFG
104#define UDACFG TK1MUX_GROUP_OFFSET_UDACFG
105#define ATCFG1 TK1MUX_GROUP_OFFSET_ATCFG1
106#define ATCFG2 TK1MUX_GROUP_OFFSET_ATCFG2
107#define ATCFG3 TK1MUX_GROUP_OFFSET_ATCFG3
108#define ATCFG4 TK1MUX_GROUP_OFFSET_ATCFG4
109#define ATCFG5 TK1MUX_GROUP_OFFSET_ATCFG5
110#define ATCFG6 TK1MUX_GROUP_OFFSET_ATCFG6
111#define GMECFG TK1MUX_GROUP_OFFSET_GMECFG
112#define GMFCFG TK1MUX_GROUP_OFFSET_GMFCFG
113#define GMGCFG TK1MUX_GROUP_OFFSET_GMGCFG
114#define GMHCFG  TK1MUX_GROUP_OFFSET_GMHCFG
115#define HVCFG0 TK1MUX_GROUP_OFFSET_HVCFG0
116#define GPVCFG TK1MUX_GROUP_OFFSET_GPVCFG
117#define USB_VBUS_EN_CFG TK1MUX_GROUP_OFFSET_USB_VBUS_EN_CFG
118
119typedef struct mux_pin_group_mapping_ {
120    uint16_t    mux_reg_index, group_offset;
121} mux_pin_group_mapping_t;
122
123enum mux_group_bitoffset {
124    BITOFF_DRIVEUP,
125    BITOFF_DRIVEDOWN,
126    BITMASK_DRIVEUP,
127    BITMASK_DRIVEDOWN
128};
129
130typedef struct mux_group_bitoff_mapping_ {
131    uint16_t    group_offset;
132    uint8_t     driveup_bitoff, drivedown_bitoff,
133                driveup_mask, drivedown_mask;
134} mux_group_bitoff_mapping_t;
135
136extern const mux_group_bitoff_mapping_t mux_group_bitinfo_mapping_table[];
137extern const mux_pin_group_mapping_t mux_pin_group_mapping_table[];
138
139int array_size_pin_group_mapping_table(void);
140
141/** Lookup the group configuration offset for a pin.
142 * @param[in] mux_reg_index     Index of a mux pin. See tk1/mux.h
143 * @return  -1 on error
144 *          positive integer offset on success.
145 */
146static inline int
147tk1_mux_get_group_offset_for_pin(int mux_reg_index)
148{
149    for (int i = 0; i < array_size_pin_group_mapping_table(); i++) {
150        if (mux_pin_group_mapping_table[i].mux_reg_index == mux_reg_index) {
151            if (mux_pin_group_mapping_table[i].group_offset == 0) {
152                /* If the pin has no group configuration reg, return error. */
153                return -1;
154            }
155
156            return mux_pin_group_mapping_table[i].group_offset;
157        }
158    }
159    return -1;
160}
161
162int array_size_bitinfo_mapping_table(void);
163
164static inline int
165tk1_mux_get_bitinfo_for_group(int group_offset, int desired_bitinfo)
166{
167    for (int i = 0; i < array_size_bitinfo_mapping_table(); i++) {
168        if (mux_group_bitinfo_mapping_table[i].group_offset == group_offset) {
169            switch (desired_bitinfo) {
170            case BITMASK_DRIVEDOWN:
171                return mux_group_bitinfo_mapping_table[i].drivedown_mask;
172            case BITMASK_DRIVEUP:
173                return mux_group_bitinfo_mapping_table[i].driveup_mask;
174            case BITOFF_DRIVEDOWN:
175                return mux_group_bitinfo_mapping_table[i].drivedown_bitoff;
176            case BITOFF_DRIVEUP:
177                return mux_group_bitinfo_mapping_table[i].driveup_bitoff;
178            default:
179                ZF_LOGE("Invalid bitinfo %d requested for groupoffset %d.",
180                        desired_bitinfo, group_offset);
181                return -1;
182            }
183        }
184    }
185    return -1;
186}
187