1/* 2 * Copyright 2017, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#include <stdlib.h> 14#include <platsupport/serial.h> 15#include <platsupport/plat/serial.h> 16#include <string.h> 17 18#include "../../chardev.h" 19 20#define UART_REF_CLK 50000000 21 22/* CR */ 23#define UART_CR_RXRES BIT( 0) 24#define UART_CR_TXRES BIT( 1) 25#define UART_CR_RXEN BIT( 2) 26#define UART_CR_RXDIS BIT( 3) 27#define UART_CR_TXEN BIT( 4) 28#define UART_CR_TXDIS BIT( 5) 29#define UART_CR_RSTTO BIT( 6) 30#define UART_CR_STTBRK BIT( 7) 31#define UART_CR_STPBRK BIT( 8) 32/* MR */ 33#define UART_MR_CLKS BIT( 0) 34#define UART_MR_CHRL(x) ((x) * BIT(1)) 35#define UART_MR_CHRL_MASK UART_MR_CHRL(0x3) 36#define UART_MR_PAR(x) ((x) * BIT(3)) 37#define UART_MR_PAR_MASK UART_MR_PAR(0x7) 38#define UART_MR_NBSTOP(x) ((x) * BIT(6)) 39#define UART_MR_NBSTOP_MASK UART_MR_NBSTOP(0x3) 40#define UART_MR_CHMODE(x) ((x) * BIT(8)) 41#define UART_MR_CHMODE_MASK UART_MR_CHMODE(0x3) 42/* IER */ 43#define UART_IER_RTRIG BIT( 0) 44#define UART_IER_REMPTY BIT( 1) 45#define UART_IER_RFUL BIT( 2) 46#define UART_IER_TEMPTY BIT( 3) 47#define UART_IER_TFUL BIT( 4) 48#define UART_IER_ROVR BIT( 5) 49#define UART_IER_FRAME BIT( 6) 50#define UART_IER_PARE BIT( 7) 51#define UART_IER_TIMEOUT BIT( 8) 52#define UART_IER_DMSI BIT( 9) 53#define UART_IER_TTRIG BIT(10) 54#define UART_IER_TNFUL BIT(11) 55#define UART_IER_TOVR BIT(12) 56/* IDR */ 57#define UART_IDR_RTRIG BIT( 0) 58#define UART_IDR_REMPTY BIT( 1) 59#define UART_IDR_RFUL BIT( 2) 60#define UART_IDR_TEMPTY BIT( 3) 61#define UART_IDR_TFUL BIT( 4) 62#define UART_IDR_ROVR BIT( 5) 63#define UART_IDR_FRAME BIT( 6) 64#define UART_IDR_PARE BIT( 7) 65#define UART_IDR_TIMEOUT BIT( 8) 66#define UART_IDR_DMSI BIT( 9) 67#define UART_IDR_TTRIG BIT(10) 68#define UART_IDR_TNFUL BIT(11) 69#define UART_IDR_TOVR BIT(12) 70/* IMR */ 71#define UART_IMR_RTRIG BIT( 0) 72#define UART_IMR_REMPTY BIT( 1) 73#define UART_IMR_RFUL BIT( 2) 74#define UART_IMR_TEMPTY BIT( 3) 75#define UART_IMR_TFUL BIT( 4) 76#define UART_IMR_ROVR BIT( 5) 77#define UART_IMR_FRAME BIT( 6) 78#define UART_IMR_PARE BIT( 7) 79#define UART_IMR_TIMEOUT BIT( 8) 80#define UART_IMR_DMSI BIT( 9) 81#define UART_IMR_TTRIG BIT(10) 82#define UART_IMR_TNFUL BIT(11) 83#define UART_IMR_TOVR BIT(12) 84/* ISR */ 85#define UART_ISR_RTRIG BIT( 0) 86#define UART_ISR_REMPTY BIT( 1) 87#define UART_ISR_RFUL BIT( 2) 88#define UART_ISR_TEMPTY BIT( 3) 89#define UART_ISR_TFUL BIT( 4) 90#define UART_ISR_ROVR BIT( 5) 91#define UART_ISR_FRAME BIT( 6) 92#define UART_ISR_PARE BIT( 7) 93#define UART_ISR_TIMEOUT BIT( 8) 94#define UART_ISR_DMSI BIT( 9) 95#define UART_ISR_TTRIG BIT(10) 96#define UART_ISR_TNFUL BIT(11) 97#define UART_ISR_TOVR BIT(12) 98/* RXTOUT */ 99#define UART_RXTOUT_RTO(x) ((x) * BIT(0)) 100#define UART_RXTOUT_RTO_MASK UART_RXTOUT_RTO(0xFF) 101/* RXWM */ 102#define UART_RXWM_RTRIG(x) ((x) * BIT(0)) 103#define UART_RXWM_RTRIG_MASK UART_RXWM_RTRIG(0x3F) 104/* MODEMCR */ 105#define UART_MODEMCR_DTR BIT( 0) 106#define UART_MODEMCR_RTS BIT( 1) 107#define UART_MODEMCR_FCM BIT( 5) 108/* MODEMSR */ 109#define UART_MODEMSR_DCTS BIT( 0) 110#define UART_MODEMSR_DDSR BIT( 1) 111#define UART_MODEMSR_TERI BIT( 2) 112#define UART_MODEMSR_DDCD BIT( 3) 113#define UART_MODEMSR_CTS BIT( 4) 114#define UART_MODEMSR_DSR BIT( 5) 115#define UART_MODEMSR_RI BIT( 6) 116#define UART_MODEMSR_DCD BIT( 7) 117#define UART_MODEMSR_FCMS BIT( 8) 118/* SR */ 119#define UART_SR_RTRIG BIT( 0) 120#define UART_SR_REMPTY BIT( 1) 121#define UART_SR_RFUL BIT( 2) 122#define UART_SR_TEMPTY BIT( 3) 123#define UART_SR_TFUL BIT( 4) 124#define UART_SR_RACTIVE BIT(10) 125#define UART_SR_TACTIVE BIT(11) 126#define UART_SR_FDELT BIT(12) 127#define UART_SR_TTRIG BIT(13) 128#define UART_SR_TNFUL BIT(14) 129/* FLOWDIV */ 130#define UART_FLOWDIV_FDEL(x) ((x) * BIT(0)) 131#define UART_FLOWDIV_FDEL_MASK UART_FLOWDIV_FDEL(0x3F) 132/* TXWM */ 133#define UART_TXWM_TTRIG(x) ((x) * BIT(0)) 134#define UART_TXWM_TTRIG_MASK UART_TXWM_TTRIG(0x3F) 135 136/* Baud rate dividers */ 137#define UART_BAUDDIV_BDIV_MIN 4 138#define UART_BAUDDIV_BDIV_MAX 255 139#define UART_BAUDGEN_CD_MIN 1 140#define UART_BAUDGEN_CD_MAX 65535 141 142/* Fifo size */ 143#define UART_TX_FIFO_SIZE 64 144#define UART_RX_FIFO_SIZE 64 145 146struct zynq_uart_regs { 147 uint32_t cr; /* 0x00 Control Register */ 148 uint32_t mr; /* 0x04 Mode Register */ 149 uint32_t ier; /* 0x08 Interrupt Enable Register */ 150 uint32_t idr; /* 0x0C Interrupt Disable Register */ 151 uint32_t imr; /* 0x10 Interrupt Mask Register (read-only) */ 152 uint32_t isr; /* 0x14 Channel Interrupt Status Register (write a 1 to clear) */ 153 uint32_t baudgen; /* 0x18 Baud Rate Generator Register */ 154 uint32_t rxtout; /* 0x1C Receiver Timeout Register */ 155 uint32_t rxwm; /* 0x20 Receiver FIFO Trigger Level Register */ 156 uint32_t modemcr; /* 0x24 Modem Control Register */ 157 uint32_t modemsr; /* 0x28 Modem Status Register */ 158 uint32_t sr; /* 0x2C Channel Status Register (read-only) */ 159 uint32_t fifo; /* 0x30 Transmit and Receive FIFO */ 160 uint32_t bauddiv; /* 0x34 Baud Rate Divider Register */ 161 uint32_t flowdel; /* 0x38 Flow Control Delay Register */ 162 uint32_t pad[2]; 163 uint32_t txwm; /* 0x44 Transmitter FIFO Trigger Level Register */ 164}; 165typedef volatile struct zynq_uart_regs zynq_uart_regs_t; 166 167static inline zynq_uart_regs_t *zynq_uart_get_priv(ps_chardevice_t *d) 168{ 169 return (zynq_uart_regs_t *)d->vaddr; 170} 171 172static inline void zynq_uart_enable_tx( 173 zynq_uart_regs_t *regs) 174{ 175 regs->cr &= ~UART_CR_TXDIS; 176 regs->cr |= UART_CR_TXEN; 177} 178 179static inline void zynq_uart_enable_rx( 180 zynq_uart_regs_t *regs) 181{ 182 regs->cr &= ~UART_CR_RXDIS; 183 regs->cr |= UART_CR_RXEN; 184} 185 186int uart_getchar( 187 ps_chardevice_t *d) 188{ 189 zynq_uart_regs_t *regs = zynq_uart_get_priv(d); 190 int c = -1; 191 192 uint32_t imr = regs->imr; 193 regs->idr = imr; 194 195 if (!(regs->sr & UART_SR_REMPTY)) { 196 c = regs->fifo; 197 198 /* Clear the Rx timeout interrupt status bit if set. Register 199 * implements the "write a 1 to clear" semantic. 200 */ 201 if (regs->isr & UART_ISR_TIMEOUT) { 202 regs->isr = UART_ISR_TIMEOUT; 203 } 204 } 205 206 regs->ier = imr; 207 208 return c; 209} 210 211int uart_putchar( 212 ps_chardevice_t *d, 213 int c) 214{ 215 int ret = -1; 216 zynq_uart_regs_t *regs = zynq_uart_get_priv(d); 217 218 uint32_t imr = regs->imr; 219 regs->idr = imr; 220 221 if (c == '\n' && (d->flags & SERIAL_AUTO_CR)) { 222 /* check if 2 bytes are free - tx trigger level is 63 and 223 * this bit is set if the fifo level is >= the trigger level 224 */ 225 if (!(regs->sr & UART_SR_TTRIG)) { 226 227 regs->fifo = '\r'; 228 regs->fifo = '\n'; 229 230 ret = '\n'; 231 } 232 } else if (!(regs->sr & UART_SR_TFUL)) { 233 regs->fifo = c; 234 ret = c; 235 } 236 237 while ((regs->sr & (UART_SR_TEMPTY | UART_SR_TACTIVE)) != UART_SR_TEMPTY); 238 239 regs->ier = imr; 240 241 return ret; 242} 243 244static void uart_handle_irq( 245 ps_chardevice_t *d) 246{ 247 zynq_uart_regs_t *regs = zynq_uart_get_priv(d); 248 regs->isr = UART_ISR_RTRIG; 249} 250 251/* 252 * Calculate the baud rate divisors 253 * @param clk: UART module input clock 254 * @param baud: Desired baud rate 255 * @param rdiv8: Calculated MR[CLKS] clock source select value (returned) 256 * @param rcd: Calculated BAUDGEN[CD] baud rate clock divisor value (returned) 257 * @param rbdiv: Calculated BAUDDIV[BDIV] baud rate divider value (returned) 258 * @return : The actual baud rate based on the calculated values 259 */ 260static long zynq_uart_calc_baud_divs( 261 long clk, 262 long baud, 263 unsigned int *rdiv8, 264 uint32_t *rcd, 265 uint32_t *rbdiv) 266{ 267 /* Safety checks */ 268 assert(rdiv8 != NULL); 269 assert(rcd != NULL); 270 assert(rbdiv != NULL); 271 272 uint32_t cd, bdiv; 273 long rbaud; 274 unsigned int calc_baud, baud_error, best_baud_error = ~0; 275 276 /* Calculate the UART clock divisor */ 277 if (baud < clk / ((UART_BAUDDIV_BDIV_MAX + 1) * UART_BAUDGEN_CD_MAX)) { 278 *rdiv8 = 1; 279 clk /= 8; 280 } else { 281 *rdiv8 = 0; 282 } 283 284 /* Calculate values for CD and BDIV based on the desired baud rate */ 285 for (bdiv = UART_BAUDDIV_BDIV_MIN; bdiv <= UART_BAUDDIV_BDIV_MAX; bdiv++) { 286 cd = clk / (baud * (bdiv + 1)); 287 if (cd < UART_BAUDGEN_CD_MIN || cd > UART_BAUDGEN_CD_MAX) { 288 continue; 289 } 290 291 calc_baud = clk / (cd * (bdiv + 1)); 292 293 if (baud > calc_baud) { 294 baud_error = baud - calc_baud; 295 } else { 296 baud_error = calc_baud - baud; 297 } 298 299 if (baud_error < best_baud_error) { 300 best_baud_error = baud_error; 301 *rcd = cd; 302 *rbdiv = bdiv; 303 rbaud = calc_baud; 304 305 /* Short-circuit */ 306 if (baud_error == 0) { 307 break; 308 } 309 } 310 } 311 312 return rbaud; 313} 314 315/* 316 * baud rate = clk / BAUDGEN.CD * (BAUDDIV.BDIV + 1) 317 * BAUDGEN.CD is 16 bit, BAUDDIV.BDIV is 8 bit 318 */ 319static void zynq_uart_set_baud( 320 ps_chardevice_t *d, 321 long bps) 322{ 323 zynq_uart_regs_t *regs = zynq_uart_get_priv(d); 324 uint32_t cd = 0; 325 uint32_t bdiv = 0; 326 unsigned int div8; 327 328 zynq_uart_calc_baud_divs(UART_REF_CLK, bps, &div8, &cd, &bdiv); 329 330 /* Disable the Rx path */ 331 regs->cr &= ~UART_CR_RXEN; 332 333 /* Disable the Tx path */ 334 regs->cr &= ~UART_CR_TXEN; 335 336 /* Apply the calculated values */ 337 if (div8) { 338 regs->mr |= UART_MR_CLKS; 339 } else { 340 regs->mr &= ~UART_MR_CLKS; 341 } 342 343 regs->baudgen = cd; 344 regs->bauddiv = bdiv; 345 346 /* Reset the Tx and Rx paths */ 347 regs->cr |= UART_CR_TXRES | UART_CR_RXRES; 348 while (regs->cr & (UART_CR_TXRES | UART_CR_RXRES)); 349 350 /* Enable the Rx path */ 351 zynq_uart_enable_rx(regs); 352 353 /* Enable the Tx path */ 354 zynq_uart_enable_tx(regs); 355} 356 357int serial_configure( 358 ps_chardevice_t *d, 359 long bps, 360 int char_size, 361 enum serial_parity parity, 362 int stop_bits) 363{ 364 zynq_uart_regs_t *regs = zynq_uart_get_priv(d); 365 uint32_t mr; 366 367 /* Character size */ 368 mr = regs->mr; 369 if (char_size == 6) { 370 mr &= ~UART_MR_CHRL_MASK; 371 mr |= UART_MR_CHRL(0x3); 372 } else if (char_size == 7) { 373 mr &= ~UART_MR_CHRL_MASK; 374 mr |= UART_MR_CHRL(0x2); 375 } else if (char_size == 8) { 376 mr &= ~UART_MR_CHRL_MASK; 377 } else { 378 return -1; 379 } 380 /* Stop bits */ 381 if (stop_bits == 1) { 382 mr &= ~UART_MR_NBSTOP_MASK; 383 } else if (stop_bits == 2) { 384 mr &= ~UART_MR_NBSTOP_MASK; 385 mr |= UART_MR_NBSTOP(0x2); 386 /* Do not handle 1.5 stop bits for now */ 387 } else { 388 return -1; 389 } 390 /* Parity */ 391 if (parity == PARITY_EVEN) { 392 mr &= ~UART_MR_PAR_MASK; 393 } else if (parity == PARITY_ODD) { 394 mr &= ~UART_MR_PAR_MASK; 395 mr |= UART_MR_PAR(0x1); 396 /* Do not handle forced to 0 parity (space) for now */ 397 /* Do not handle forced to 1 parity (mark) for now */ 398 } else if (parity == PARITY_NONE) { 399 mr &= ~UART_MR_PAR_MASK; 400 mr |= UART_MR_PAR(0x7); 401 } else { 402 return -1; 403 } 404 /* Apply the changes */ 405 regs->mr = mr; 406#ifndef CONFIG_PLAT_ZYNQMP 407 /* TODO: We don't have a correct reference clock on zynqmp and 408 * therefore rely on the board having been initialised by earlier 409 * loaders. 410 */ 411 /* Now set the board rate */ 412 zynq_uart_set_baud(d, bps); 413#endif 414 return 0; 415} 416 417static void zynq_uart_dev_init( 418 ps_chardevice_t *dev, 419 const ps_io_ops_t *ops, 420 enum chardev_id id, 421 void *vaddr, 422 const int *irqs) 423{ 424 assert(NULL != dev); 425 426 memset(dev, 0, sizeof(*dev)); 427 428 /* Set up all the device properties. */ 429 dev->id = id; 430 dev->vaddr = vaddr; 431 dev->irqs = irqs; 432 433 dev->read = &uart_read; 434 dev->write = &uart_write; 435 dev->handle_irq = &uart_handle_irq; 436 dev->ioops = *ops; 437 438 dev->flags = SERIAL_AUTO_CR; 439} 440 441static int zynq_uart_init( 442 ps_chardevice_t *dev) 443{ 444 zynq_uart_regs_t *regs = zynq_uart_get_priv(dev); 445 446 /* Software reset */ 447 // TODO - UART software reset is done through a different register (UART_RST_CTRL) 448 // TODO - does the I/O signal routing have to be configured here too? 449 450 /* Configure UART character frame */ 451 serial_configure(dev, 115200, 8, PARITY_NONE, 1); 452 453 /* Set the level of the RxFIFO trigger level */ 454 regs->rxwm &= ~UART_RXWM_RTRIG_MASK; /* Clear the Rx trigger level */ 455 regs->rxwm |= UART_RXWM_RTRIG(1); /* Set the Rx trigger level to 1 */ 456 457 /* Enable the RTRIG interrupt */ 458 regs->ier |= UART_IER_RTRIG; /* Set the interrupt enable bit */ 459 regs->idr &= ~UART_IDR_RTRIG; /* Clear the interrupt disable bit */ 460 if (!(regs->imr & UART_IMR_RTRIG)) { /* Verify the interrupt mask value */ 461 return -1; 462 } 463 464 /* Enable the controller */ 465 regs->cr |= UART_CR_TXRES; /* Reset Tx path */ 466 regs->cr |= UART_CR_RXRES; /* Reset Rx path */ 467 zynq_uart_enable_rx(regs); /* Enable the Rx path */ 468 zynq_uart_enable_tx(regs); /* Enable the Tx path */ 469 regs->cr |= UART_CR_RSTTO; /* Restart the receiver timeout counter */ 470 regs->cr &= ~UART_CR_STTBRK; /* Do not start to transmit a break */ 471 regs->cr |= UART_CR_STPBRK; /* Stop break transmitter */ 472 473 /* Program the receiver timeout mechanism */ 474 regs->rxtout &= ~UART_RXTOUT_RTO_MASK; /* Disable the timeout mechanism */ 475 476 /* set the tx trigger to one less than the fifo size so it's possible to check 477 * if there are 2 bytes free 478 */ 479 regs->txwm = UART_TXWM_TTRIG(UART_TX_FIFO_SIZE - 1) & UART_TXWM_TTRIG_MASK; 480 481 return 0; 482} 483 484int uart_static_init( 485 void *vaddr, 486 const ps_io_ops_t *ops, 487 ps_chardevice_t *dev) 488{ 489 assert(NULL != vaddr); 490 assert(NULL != ops); 491 assert(NULL != dev); 492 493 /* There is a design quirk here, no context information is passed which 494 * UART this is and what interrupt it uses. So we have set something now 495 * to make this well defined. ZYNQ_UART0 seem a good choice, because this 496 * is what the callers usually want. The contents of the interrupt field 497 * are not used in the driver, so we set this to NULL. 498 */ 499 500 zynq_uart_dev_init(dev, ops, ZYNQ_UART0, vaddr, NULL); 501 502 return zynq_uart_init(dev); 503 504} 505 506int uart_init( 507 const struct dev_defn *defn, 508 const ps_io_ops_t *ops, 509 ps_chardevice_t *dev) 510{ 511 assert(NULL != defn); 512 assert(NULL != ops); 513 assert(NULL != dev); 514 515 /* Attempt to map the virtual address, assure this works */ 516 void *vaddr = chardev_map(defn, ops); 517 if (vaddr == NULL) { 518 return -1; 519 } 520 521 zynq_uart_dev_init(dev, ops, defn->id, vaddr, defn->irqs); 522 523 return zynq_uart_init(dev); 524} 525