1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Andy Fleming <afleming@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h 8 */ 9 10#ifndef _PHY_H 11#define _PHY_H 12 13#include "list.h" 14#include <stdio.h> 15#include "mii.h" 16#include "ethtool.h" 17#include "mdio.h" 18 19#define PHY_MAX_ADDR 32 20 21#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ 22 23#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ 24 SUPPORTED_TP | \ 25 SUPPORTED_MII) 26 27#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ 28 SUPPORTED_10baseT_Full) 29 30#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ 31 SUPPORTED_100baseT_Full) 32 33#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ 34 SUPPORTED_1000baseT_Full) 35 36#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ 37 PHY_100BT_FEATURES | \ 38 PHY_DEFAULT_FEATURES) 39 40#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ 41 PHY_1000BT_FEATURES) 42 43#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ 44 SUPPORTED_10000baseT_Full) 45 46#ifndef PHY_ANEG_TIMEOUT 47#define PHY_ANEG_TIMEOUT 4000 48#endif 49 50 51typedef enum { 52 PHY_INTERFACE_MODE_MII, 53 PHY_INTERFACE_MODE_GMII, 54 PHY_INTERFACE_MODE_SGMII, 55 PHY_INTERFACE_MODE_SGMII_2500, 56 PHY_INTERFACE_MODE_QSGMII, 57 PHY_INTERFACE_MODE_TBI, 58 PHY_INTERFACE_MODE_RMII, 59 PHY_INTERFACE_MODE_RGMII, 60 PHY_INTERFACE_MODE_RGMII_ID, 61 PHY_INTERFACE_MODE_RGMII_RXID, 62 PHY_INTERFACE_MODE_RGMII_TXID, 63 PHY_INTERFACE_MODE_RTBI, 64 PHY_INTERFACE_MODE_XGMII, 65 PHY_INTERFACE_MODE_NONE, /* Must be last */ 66 67 PHY_INTERFACE_MODE_COUNT, 68} phy_interface_t; 69 70static const char *phy_interface_strings[] = { 71 [PHY_INTERFACE_MODE_MII] = "mii", 72 [PHY_INTERFACE_MODE_GMII] = "gmii", 73 [PHY_INTERFACE_MODE_SGMII] = "sgmii", 74 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", 75 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", 76 [PHY_INTERFACE_MODE_TBI] = "tbi", 77 [PHY_INTERFACE_MODE_RMII] = "rmii", 78 [PHY_INTERFACE_MODE_RGMII] = "rgmii", 79 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", 80 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", 81 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", 82 [PHY_INTERFACE_MODE_RTBI] = "rtbi", 83 [PHY_INTERFACE_MODE_XGMII] = "xgmii", 84 [PHY_INTERFACE_MODE_NONE] = "", 85}; 86 87static inline const char *phy_string_for_interface(phy_interface_t i) 88{ 89 /* Default to unknown */ 90 if (i > PHY_INTERFACE_MODE_NONE) 91 i = PHY_INTERFACE_MODE_NONE; 92 93 return phy_interface_strings[i]; 94} 95 96 97struct phy_device; 98 99#define MDIO_NAME_LEN 32 100 101struct mii_dev { 102 struct list_head link; 103 char name[MDIO_NAME_LEN]; 104 void *priv; 105 int (*read)(struct mii_dev *bus, int addr, int devad, int reg); 106 int (*write)(struct mii_dev *bus, int addr, int devad, int reg, 107 uint16_t val); 108 int (*reset)(struct mii_dev *bus); 109 struct phy_device *phymap[PHY_MAX_ADDR]; 110 u32 phy_mask; 111}; 112 113/* struct phy_driver: a structure which defines PHY behavior 114 * 115 * uid will contain a number which represents the PHY. During 116 * startup, the driver will poll the PHY to find out what its 117 * UID--as defined by registers 2 and 3--is. The 32-bit result 118 * gotten from the PHY will be masked to 119 * discard any bits which may change based on revision numbers 120 * unimportant to functionality 121 * 122 */ 123struct phy_driver { 124 char *name; 125 unsigned int uid; 126 unsigned int mask; 127 unsigned int mmds; 128 129 uint32_t features; 130 131 /* Called to do any driver startup necessities */ 132 /* Will be called during phy_connect */ 133 int (*probe)(struct phy_device *phydev); 134 135 /* Called to configure the PHY, and modify the controller 136 * based on the results. Should be called after phy_connect */ 137 int (*config)(struct phy_device *phydev); 138 139 /* Called when starting up the controller */ 140 int (*startup)(struct phy_device *phydev); 141 142 /* Called when bringing down the controller */ 143 int (*shutdown)(struct phy_device *phydev); 144 145 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); 146 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, 147 u16 val); 148 struct list_head list; 149}; 150 151struct phy_device { 152 /* Information about the PHY type */ 153 /* And management functions */ 154 struct mii_dev *bus; 155 struct phy_driver *drv; 156 void *priv; 157 158#ifdef CONFIG_DM_ETH 159 struct udevice *dev; 160#else 161 struct eth_device *dev; 162#endif 163 164 /* forced speed & duplex (no autoneg) 165 * partner speed & duplex & pause (autoneg) 166 */ 167 int speed; 168 int duplex; 169 170 /* The most recently read link state */ 171 int link; 172 int port; 173 phy_interface_t interface; 174 175 uint32_t advertising; 176 uint32_t supported; 177 uint32_t mmds; 178 179 int autoneg; 180 int addr; 181 int pause; 182 int asym_pause; 183 uint32_t phy_id; 184 uint32_t flags; 185}; 186 187struct fixed_link { 188 int phy_id; 189 int duplex; 190 int link_speed; 191 int pause; 192 int asym_pause; 193}; 194 195static inline int phy_read(struct phy_device *phydev, int devad, int regnum) 196{ 197 struct mii_dev *bus = phydev->bus; 198 199 return bus->read(bus, phydev->addr, devad, regnum); 200} 201 202static inline int phy_write(struct phy_device *phydev, int devad, int regnum, 203 uint16_t val) 204{ 205 struct mii_dev *bus = phydev->bus; 206 207 return bus->write(bus, phydev->addr, devad, regnum, val); 208} 209 210#ifdef CONFIG_PHYLIB_10G 211extern struct phy_driver gen10g_driver; 212 213/* For now, XGMII is the only 10G interface */ 214static inline int is_10g_interface(phy_interface_t interface) 215{ 216 return interface == PHY_INTERFACE_MODE_XGMII; 217} 218 219#endif 220 221int phy_init(void); 222int phy_reset(struct phy_device *phydev); 223struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, 224 phy_interface_t interface); 225#ifdef CONFIG_DM_ETH 226void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); 227struct phy_device *phy_connect(struct mii_dev *bus, int addr, 228 struct udevice *dev, 229 phy_interface_t interface); 230#else 231void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); 232struct phy_device *phy_connect(struct mii_dev *bus, int addr, 233 struct eth_device *dev, 234 phy_interface_t interface); 235#endif 236int phy_startup(struct phy_device *phydev); 237int phy_config(struct phy_device *phydev); 238int phy_shutdown(struct phy_device *phydev); 239int phy_register(struct phy_driver *drv); 240int phy_set_supported(struct phy_device *phydev, u32 max_speed); 241int genphy_config_aneg(struct phy_device *phydev); 242int genphy_restart_aneg(struct phy_device *phydev); 243int genphy_update_link(struct phy_device *phydev); 244int genphy_parse_link(struct phy_device *phydev); 245int genphy_config(struct phy_device *phydev); 246int genphy_startup(struct phy_device *phydev); 247int genphy_shutdown(struct phy_device *phydev); 248int gen10g_config(struct phy_device *phydev); 249int gen10g_startup(struct phy_device *phydev); 250int gen10g_shutdown(struct phy_device *phydev); 251int gen10g_discover_mmds(struct phy_device *phydev); 252 253int phy_mv88e61xx_init(void); 254int phy_aquantia_init(void); 255int phy_atheros_init(void); 256int phy_broadcom_init(void); 257int phy_cortina_init(void); 258int phy_davicom_init(void); 259int phy_et1011c_init(void); 260int phy_lxt_init(void); 261int phy_marvell_init(void); 262int phy_micrel_init(void); 263int phy_natsemi_init(void); 264int phy_realtek_init(void); 265int phy_smsc_init(void); 266int phy_teranetics_init(void); 267int phy_ti_init(void); 268int phy_vitesse_init(void); 269int phy_xilinx_init(void); 270 271int board_phy_config(struct phy_device *phydev); 272int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); 273 274/** 275 * phy_get_interface_by_name() - Look up a PHY interface name 276 * 277 * @str: PHY interface name, e.g. "mii" 278 * @return PHY_INTERFACE_MODE_... value, or -1 if not found 279 */ 280int phy_get_interface_by_name(const char *str); 281 282/** 283 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 284 * is RGMII (all variants) 285 * @phydev: the phy_device struct 286 */ 287static inline u8 phy_interface_is_rgmii(struct phy_device *phydev) 288{ 289 return phydev->interface >= PHY_INTERFACE_MODE_RGMII && 290 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; 291} 292 293/** 294 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface 295 * is SGMII (all variants) 296 * @phydev: the phy_device struct 297 */ 298static inline u8 phy_interface_is_sgmii(struct phy_device *phydev) 299{ 300 return phydev->interface >= PHY_INTERFACE_MODE_SGMII && 301 phydev->interface <= PHY_INTERFACE_MODE_QSGMII; 302} 303 304/* PHY UIDs for various PHYs that are referenced in external code */ 305#define PHY_UID_CS4340 0x13e51002 306#define PHY_UID_TN2020 0x00a19410 307 308#endif 309