1/* 2 * Marvell PHY drivers 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Copyright 2010-2011 Freescale Semiconductor, Inc. 7 * author Andy Fleming 8 */ 9#include "config.h" 10#include "common.h" 11#include "phy.h" 12 13#define PHY_AUTONEGOTIATE_TIMEOUT 5000 14 15/* 88E1011 PHY Status Register */ 16#define MIIM_88E1xxx_PHY_STATUS 0x11 17#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 18#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 19#define MIIM_88E1xxx_PHYSTAT_100 0x4000 20#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 21#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 22#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 23 24#define MIIM_88E1xxx_PHY_SCR 0x10 25#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 26 27/* 88E1111 PHY LED Control Register */ 28#define MIIM_88E1111_PHY_LED_CONTROL 24 29#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 30#define MIIM_88E1111_PHY_LED_COMBINE 0x411C 31 32/* 88E1111 Extended PHY Specific Control Register */ 33#define MIIM_88E1111_PHY_EXT_CR 0x14 34#define MIIM_88E1111_RX_DELAY 0x80 35#define MIIM_88E1111_TX_DELAY 0x2 36 37/* 88E1111 Extended PHY Specific Status Register */ 38#define MIIM_88E1111_PHY_EXT_SR 0x1b 39#define MIIM_88E1111_HWCFG_MODE_MASK 0xf 40#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb 41#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 42#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 43#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 44#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 45#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 46 47#define MIIM_88E1111_COPPER 0 48#define MIIM_88E1111_FIBER 1 49 50/* 88E1118 PHY defines */ 51#define MIIM_88E1118_PHY_PAGE 22 52#define MIIM_88E1118_PHY_LED_PAGE 3 53 54/* 88E1121 PHY LED Control Register */ 55#define MIIM_88E1121_PHY_LED_CTRL 16 56#define MIIM_88E1121_PHY_LED_PAGE 3 57#define MIIM_88E1121_PHY_LED_DEF 0x0030 58 59/* 88E1121 PHY IRQ Enable/Status Register */ 60#define MIIM_88E1121_PHY_IRQ_EN 18 61#define MIIM_88E1121_PHY_IRQ_STATUS 19 62 63#define MIIM_88E1121_PHY_PAGE 22 64 65/* 88E1145 Extended PHY Specific Control Register */ 66#define MIIM_88E1145_PHY_EXT_CR 20 67#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 68#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 69 70#define MIIM_88E1145_PHY_LED_CONTROL 24 71#define MIIM_88E1145_PHY_LED_DIRECT 0x4100 72 73#define MIIM_88E1145_PHY_PAGE 29 74#define MIIM_88E1145_PHY_CAL_OV 30 75 76#define MIIM_88E1149_PHY_PAGE 29 77 78/* 88E1310 PHY defines */ 79#define MIIM_88E1310_PHY_LED_CTRL 16 80#define MIIM_88E1310_PHY_IRQ_EN 18 81#define MIIM_88E1310_PHY_RGMII_CTRL 21 82#define MIIM_88E1310_PHY_PAGE 22 83 84/* Marvell 88E1011S */ 85static int m88e1011s_config(struct phy_device *phydev) 86{ 87 /* Reset and configure the PHY */ 88 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 89 90 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 91 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 92 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 93 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); 94 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 95 96 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 97 98 genphy_config_aneg(phydev); 99 100 return 0; 101} 102 103/* Parse the 88E1011's status register for speed and duplex 104 * information 105 */ 106static uint m88e1xxx_parse_status(struct phy_device *phydev) 107{ 108 unsigned int speed; 109 unsigned int mii_reg; 110 111 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); 112 113 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && 114 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 115 int i = 0; 116 117 puts("Waiting for PHY realtime link"); 118 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 119 /* Timeout reached ? */ 120 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 121 puts(" TIMEOUT !\n"); 122 phydev->link = 0; 123 break; 124 } 125 126 if ((i++ % 1000) == 0) 127 puts("."); 128 udelay(1000); 129 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, 130 MIIM_88E1xxx_PHY_STATUS); 131 } 132 puts(" done\n"); 133 udelay(500000); /* another 500 ms (results in faster booting) */ 134 } else { 135 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) 136 phydev->link = 1; 137 else 138 phydev->link = 0; 139 } 140 141 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX) 142 phydev->duplex = DUPLEX_FULL; 143 else 144 phydev->duplex = DUPLEX_HALF; 145 146 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED; 147 148 switch (speed) { 149 case MIIM_88E1xxx_PHYSTAT_GBIT: 150 phydev->speed = SPEED_1000; 151 break; 152 case MIIM_88E1xxx_PHYSTAT_100: 153 phydev->speed = SPEED_100; 154 break; 155 default: 156 phydev->speed = SPEED_10; 157 break; 158 } 159 160 return 0; 161} 162 163static int m88e1011s_startup(struct phy_device *phydev) 164{ 165 genphy_update_link(phydev); 166 m88e1xxx_parse_status(phydev); 167 168 return 0; 169} 170 171/* Marvell 88E1111S */ 172static int m88e1111s_config(struct phy_device *phydev) 173{ 174 int reg; 175 int timeout; 176 177 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 178 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || 179 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || 180 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 181 reg = phy_read(phydev, 182 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 183 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 184 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { 185 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 186 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 187 reg &= ~MIIM_88E1111_TX_DELAY; 188 reg |= MIIM_88E1111_RX_DELAY; 189 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 190 reg &= ~MIIM_88E1111_RX_DELAY; 191 reg |= MIIM_88E1111_TX_DELAY; 192 } 193 194 phy_write(phydev, 195 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 196 197 reg = phy_read(phydev, 198 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 199 200 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 201 202 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) 203 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; 204 else 205 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; 206 207 phy_write(phydev, 208 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); 209 } 210 211 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 212 reg = phy_read(phydev, 213 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 214 215 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 216 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; 217 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 218 219 phy_write(phydev, MDIO_DEVAD_NONE, 220 MIIM_88E1111_PHY_EXT_SR, reg); 221 } 222 223 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { 224 reg = phy_read(phydev, 225 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 226 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 227 phy_write(phydev, 228 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 229 230 reg = phy_read(phydev, MDIO_DEVAD_NONE, 231 MIIM_88E1111_PHY_EXT_SR); 232 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 233 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 234 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 235 phy_write(phydev, MDIO_DEVAD_NONE, 236 MIIM_88E1111_PHY_EXT_SR, reg); 237 238 /* soft reset */ 239 timeout = 1000; 240 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 241 udelay(1000); 242 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 243 while ((reg & BMCR_RESET) && --timeout) { 244 udelay(1000); 245 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 246 } 247 if (!timeout) 248 printf("%s: phy soft reset timeout\n", __func__); 249 250 reg = phy_read(phydev, MDIO_DEVAD_NONE, 251 MIIM_88E1111_PHY_EXT_SR); 252 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 253 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 254 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | 255 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 256 phy_write(phydev, MDIO_DEVAD_NONE, 257 MIIM_88E1111_PHY_EXT_SR, reg); 258 } 259 260 /* soft reset */ 261 timeout = 1000; 262 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 263 udelay(1000); 264 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 265 while ((reg & BMCR_RESET) && --timeout) { 266 udelay(1000); 267 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 268 } 269 if (!timeout) 270 printf("%s: phy soft reset timeout\n", __func__); 271 272 genphy_config_aneg(phydev); 273 274 return 0; 275} 276 277/** 278 * m88e1518_phy_writebits - write bits to a register 279 */ 280void m88e1518_phy_writebits(struct phy_device *phydev, 281 u8 reg_num, u16 offset, u16 len, u16 data) 282{ 283 u16 reg, mask; 284 285 if ((len + offset) >= 16) 286 mask = 0 - (1 << offset); 287 else 288 mask = (1 << (len + offset)) - (1 << offset); 289 290 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); 291 292 reg &= ~mask; 293 reg |= data << offset; 294 295 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); 296} 297 298static int m88e1518_config(struct phy_device *phydev) 299{ 300 /* 301 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 302 * /88E1514 Rev A0, Errata Section 3.1 303 */ 304 305 /* EEE initialization */ 306 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); 307 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); 308 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); 309 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); 310 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); 311 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); 312 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); 313 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); 314 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); 315 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); 316 317 /* SGMII-to-Copper mode initialization */ 318 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 319 /* Select page 18 */ 320 phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); 321 322 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ 323 m88e1518_phy_writebits(phydev, 20, 0, 3, 1); 324 325 /* PHY reset is necessary after changing MODE[2:0] */ 326 m88e1518_phy_writebits(phydev, 20, 15, 1, 1); 327 328 /* Reset page selection */ 329 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 330 331 udelay(100); 332 } 333 334 return m88e1111s_config(phydev); 335} 336 337/* Marvell 88E1510 */ 338static int m88e1510_config(struct phy_device *phydev) 339{ 340 /* Select page 3 */ 341 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 342 343 /* Enable INTn output on LED[2] */ 344 m88e1518_phy_writebits(phydev, 18, 7, 1, 1); 345 346 /* Configure LEDs */ 347 m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */ 348 m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */ 349 350 /* Reset page selection */ 351 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 352 353 return m88e1518_config(phydev); 354} 355 356/* Marvell 88E1118 */ 357static int m88e1118_config(struct phy_device *phydev) 358{ 359 /* Change Page Number */ 360 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); 361 /* Delay RGMII TX and RX */ 362 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); 363 /* Change Page Number */ 364 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); 365 /* Adjust LED control */ 366 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); 367 /* Change Page Number */ 368 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 369 370 return genphy_config_aneg(phydev); 371} 372 373static int m88e1118_startup(struct phy_device *phydev) 374{ 375 int ret = 0; 376 /* Change Page Number */ 377 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 378 379 ret = genphy_update_link(phydev); 380 m88e1xxx_parse_status(phydev); 381 382 return ret; 383} 384 385/* Marvell 88E1121R */ 386static int m88e1121_config(struct phy_device *phydev) 387{ 388 int pg; 389 390 /* Configure the PHY */ 391 genphy_config_aneg(phydev); 392 393 /* Switch the page to access the led register */ 394 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); 395 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, 396 MIIM_88E1121_PHY_LED_PAGE); 397 /* Configure leds */ 398 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, 399 MIIM_88E1121_PHY_LED_DEF); 400 /* Restore the page pointer */ 401 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); 402 403 /* Disable IRQs and de-assert interrupt */ 404 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); 405 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); 406 407 return 0; 408} 409 410/* Marvell 88E1145 */ 411static int m88e1145_config(struct phy_device *phydev) 412{ 413 int reg; 414 415 /* Errata E0, E1 */ 416 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); 417 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); 418 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); 419 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); 420 421 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, 422 MIIM_88E1xxx_PHY_MDI_X_AUTO); 423 424 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); 425 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 426 reg |= MIIM_M88E1145_RGMII_RX_DELAY | 427 MIIM_M88E1145_RGMII_TX_DELAY; 428 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); 429 430 genphy_config_aneg(phydev); 431 432 phy_reset(phydev); 433 434 return 0; 435} 436 437static int m88e1145_startup(struct phy_device *phydev) 438{ 439 genphy_update_link(phydev); 440 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, 441 MIIM_88E1145_PHY_LED_DIRECT); 442 m88e1xxx_parse_status(phydev); 443 444 return 0; 445} 446 447/* Marvell 88E1149S */ 448static int m88e1149_config(struct phy_device *phydev) 449{ 450 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); 451 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 452 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); 453 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); 454 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 455 456 genphy_config_aneg(phydev); 457 458 phy_reset(phydev); 459 460 return 0; 461} 462 463/* Marvell 88E1310 */ 464static int m88e1310_config(struct phy_device *phydev) 465{ 466 u16 reg; 467 468 /* LED link and activity */ 469 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 470 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); 471 reg = (reg & ~0xf) | 0x1; 472 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); 473 474 /* Set LED2/INT to INT mode, low active */ 475 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 476 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); 477 reg = (reg & 0x77ff) | 0x0880; 478 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); 479 480 /* Set RGMII delay */ 481 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); 482 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); 483 reg |= 0x0030; 484 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); 485 486 /* Ensure to return to page 0 */ 487 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); 488 489 genphy_config_aneg(phydev); 490 phy_reset(phydev); 491 492 return 0; 493} 494 495static struct phy_driver M88E1011S_driver = { 496 .name = "Marvell 88E1011S", 497 .uid = 0x1410c60, 498 .mask = 0xffffff0, 499 .features = PHY_GBIT_FEATURES, 500 .config = &m88e1011s_config, 501 .startup = &m88e1011s_startup, 502 .shutdown = &genphy_shutdown, 503}; 504 505static struct phy_driver M88E1111S_driver = { 506 .name = "Marvell 88E1111S", 507 .uid = 0x1410cc0, 508 .mask = 0xffffff0, 509 .features = PHY_GBIT_FEATURES, 510 .config = &m88e1111s_config, 511 .startup = &m88e1011s_startup, 512 .shutdown = &genphy_shutdown, 513}; 514 515static struct phy_driver M88E1118_driver = { 516 .name = "Marvell 88E1118", 517 .uid = 0x1410e10, 518 .mask = 0xffffff0, 519 .features = PHY_GBIT_FEATURES, 520 .config = &m88e1118_config, 521 .startup = &m88e1118_startup, 522 .shutdown = &genphy_shutdown, 523}; 524 525static struct phy_driver M88E1118R_driver = { 526 .name = "Marvell 88E1118R", 527 .uid = 0x1410e40, 528 .mask = 0xffffff0, 529 .features = PHY_GBIT_FEATURES, 530 .config = &m88e1118_config, 531 .startup = &m88e1118_startup, 532 .shutdown = &genphy_shutdown, 533}; 534 535static struct phy_driver M88E1121R_driver = { 536 .name = "Marvell 88E1121R", 537 .uid = 0x1410cb0, 538 .mask = 0xffffff0, 539 .features = PHY_GBIT_FEATURES, 540 .config = &m88e1121_config, 541 .startup = &genphy_startup, 542 .shutdown = &genphy_shutdown, 543}; 544 545static struct phy_driver M88E1145_driver = { 546 .name = "Marvell 88E1145", 547 .uid = 0x1410cd0, 548 .mask = 0xffffff0, 549 .features = PHY_GBIT_FEATURES, 550 .config = &m88e1145_config, 551 .startup = &m88e1145_startup, 552 .shutdown = &genphy_shutdown, 553}; 554 555static struct phy_driver M88E1149S_driver = { 556 .name = "Marvell 88E1149S", 557 .uid = 0x1410ca0, 558 .mask = 0xffffff0, 559 .features = PHY_GBIT_FEATURES, 560 .config = &m88e1149_config, 561 .startup = &m88e1011s_startup, 562 .shutdown = &genphy_shutdown, 563}; 564 565static struct phy_driver M88E1510_driver = { 566 .name = "Marvell 88E1510", 567 .uid = 0x1410dd0, 568 .mask = 0xffffff0, 569 .features = PHY_GBIT_FEATURES, 570 .config = &m88e1510_config, 571 .startup = &m88e1011s_startup, 572 .shutdown = &genphy_shutdown, 573}; 574 575static struct phy_driver M88E1518_driver = { 576 .name = "Marvell 88E1518", 577 .uid = 0x1410dd1, 578 .mask = 0xffffff0, 579 .features = PHY_GBIT_FEATURES, 580 .config = &m88e1518_config, 581 .startup = &m88e1011s_startup, 582 .shutdown = &genphy_shutdown, 583}; 584 585static struct phy_driver M88E1310_driver = { 586 .name = "Marvell 88E1310", 587 .uid = 0x01410e90, 588 .mask = 0xffffff0, 589 .features = PHY_GBIT_FEATURES, 590 .config = &m88e1310_config, 591 .startup = &m88e1011s_startup, 592 .shutdown = &genphy_shutdown, 593}; 594 595int phy_marvell_init(void) 596{ 597 phy_register(&M88E1310_driver); 598 phy_register(&M88E1149S_driver); 599 phy_register(&M88E1145_driver); 600 phy_register(&M88E1121R_driver); 601 phy_register(&M88E1118_driver); 602 phy_register(&M88E1118R_driver); 603 phy_register(&M88E1111S_driver); 604 phy_register(&M88E1011S_driver); 605 phy_register(&M88E1510_driver); 606 phy_register(&M88E1518_driver); 607 608 return 0; 609} 610