1/* 2 * @TAG(OTHER_GPL) 3 */ 4 5/* 6 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 7 * 8 * Configuration settings for the Freescale i.MX6Q Sabre Lite board. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#pragma once 27 28#define CONFIG_MX6 29#define CONFIG_MX6Q 30 31#define CONFIG_MACH_TYPE 3769 32 33#include "imx-regs.h" 34#include "gpio.h" 35 36#include <stdint.h> 37 38#define CONFIG_BOARD_EARLY_INIT_F 39#define CONFIG_MISC_INIT_R 40#define CONFIG_MXC_GPIO 41 42#define CONFIG_FEC_MXC 43#define CONFIG_MII 44#define IMX_FEC_BASE ENET_BASE_ADDR 45#define CONFIG_FEC_XCV_TYPE RGMII 46#define CONFIG_ETHPRIME "FEC" 47#define CONFIG_FEC_MXC_PHYMASK (0xf << 4) /* scan phy 4,5,6,7 */ 48#define CONFIG_PHYLIB 49#define CONFIG_PHY_MICREL 50#define CONFIG_PHY_MICREL_KSZ9021 51 52/* Command definition */ 53#include "config.h" 54 55#define CONFIG_MX6 56#define CONFIG_MX6Q 57 58#include "imx-regs.h" 59 60#define CONFIG_BOARD_EARLY_INIT_F 61#define CONFIG_MXC_GPIO 62 63#define CONFIG_MXC_UART 64#define CONFIG_FEC_MXC 65#define CONFIG_MII 66#define IMX_FEC_BASE ENET_BASE_ADDR 67#define CONFIG_FEC_XCV_TYPE RGMII 68#define CONFIG_ETHPRIME "FEC" 69#define CONFIG_FEC_MXC_PHYADDR 1 70 71#define CONFIG_PHYLIB 72#define CONFIG_PHY_ATHEROS 73 74/* Command definition */ 75#include "config.h" 76typedef uint64_t iomux_v3_cfg_t; 77 78#define MUX_CTRL_OFS_SHIFT 0 79#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) 80#define MUX_PAD_CTRL_OFS_SHIFT 12 81#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ 82 MUX_PAD_CTRL_OFS_SHIFT) 83#define MUX_SEL_INPUT_OFS_SHIFT 24 84#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ 85 MUX_SEL_INPUT_OFS_SHIFT) 86 87#define MUX_MODE_SHIFT 36 88#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT) 89#define MUX_PAD_CTRL_SHIFT 42 90#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) 91#define MUX_SEL_INPUT_SHIFT 60 92#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) 93 94#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) 95 96#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ 97 sel_input, pad_ctrl) \ 98 (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ 99 ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ 100 ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ 101 ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ 102 ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ 103 ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) 104 105#define NO_PAD_CTRL (BIT(17)) 106#define GPIO_PIN_MASK 0x1f 107#define GPIO_PORT_SHIFT 5 108#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) 109#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) 110#define GPIO_PORTB (BIT(GPIO_PORT_SHIFT)) 111#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) 112#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) 113#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) 114#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) 115 116#define MUX_CONFIG_SION (BIT(4)) 117 118