1/* 2 * Copyright 2019, Data61, CSIRO (ABN 41 687 119 230) 3 * 4 * SPDX-License-Identifier: BSD-2-Clause 5 */ 6 7#pragma once 8 9/* GPIO */ 10#if defined CONFIG_PLAT_EXYNOS54XX /* Odroid-XU/XU3 */ 11#define GPIO_LEFT_PADDR 0x14000000 12#elif defined CONFIG_PLAT_EXYNOS5250 /* Arndale */ 13#define GPIO_LEFT_PADDR 0x11400000 14#else 15#error UNKNOWN SoC 16#endif 17#define GPIO_RIGHT_PADDR 0x13400000 18 19/* DMA */ 20#define NS_MDMA1_PADDR 0x11C10000 21#define NS_MDMA0_PADDR 0x10800000 22#define PDMA1_PADDR 0x121B0000 23#define PDMA0_PADDR 0x121A0000 24 25/* Video */ 26#define I2C_HDMI_PADDR 0x12CE0000 27#define TV_MIXER_PADDR 0x14450000 28#define HDMI_0_PADDR 0x14530000 29#define HDMI_1_PADDR 0x14540000 30#define HDMI_2_PADDR 0x14550000 31#define HDMI_3_PADDR 0x14560000 32#define HDMI_4_PADDR 0x14570000 33#define HDMI_5_PADDR 0x14580000 34#define HDMI_6_PADDR 0x14590000 35 36/* I2C */ 37#define I2C1_PADDR 0x12C70000 38#define I2C2_PADDR 0x12C80000 39#define I2C4_PADDR 0x12CA0000 40 41/* USB */ 42#define USB2_HOST_OHCI_PADDR 0x12120000 43#define USB2_HOST_EHCI_PADDR 0x12110000 44#define USB2_HOST_CTRL_PADDR 0x12130000 45 46/* UART */ 47#define UART0_PADDR 0x12C00000 48#define UART1_PADDR 0x12C10000 49#define UART2_PADDR 0x12C20000 50#define UART3_PADDR 0x12C30000 51 52/* System */ 53#define CHIP_ID_PADDR 0x10000000 54#define ALIVE_PADDR 0x10040000 55#define SYSREG_PADDR 0x10050000 56#define IRQ_COMBINER_PADDR 0x10440000 57#define MCT_ADDR 0x101C0000 58#define PWM_PADDR 0x12DD0000 59 60/* Clocks */ 61#define CMU_CPU_PADDR 0x10010000 62#define CMU_CORE_PADDR 0x10014000 63#define CMU_TOP_PADDR 0x10020000 64#define CMU_CDREX_PADDR 0x10030000 65#define CMU_MEM_PADDR 0x10038000 66#define CMU_ISP_PADDR 0x1001C000 67#define CMU_ACP_PADDR 0x10018000 68 69/* SD/eMMC */ 70#define MSH0_PADDR 0x12200000 71#define MSH2_PADDR 0x12220000 72 73/* Timers */ 74#define WDT_PADDR 0x101d0000 75 76/* System MMU's */ 77#define SYSMMU_MDMA0_PADDR 0x10A40000 78#define SYSMMU_SSS_PADDR 0x10A50000 79#define SYSMMU_2D_PADDR 0x10A60000 80#define SYSMMU_MFC0_PADDR 0x11200000 81#define SYSMMU_MFC1_PADDR 0x11210000 82#define SYSMMU_ROTATOR_PADDR 0x11D40000 83#define SYSMMU_MDMA1_PADDR 0x11D50000 84#define SYSMMU_JPEG_PADDR 0x11F20000 85#define SYSMMU_IOPROC_PADDR 0x12360000 86#define SYSMMU_RTIC_PADDR 0x12370000 87#define SYSMMU_GPS_PADDR 0x12630000 88#define SYSMMU_FIMCISP_PADDR 0x13260000 89#define SYSMMU_FIMCDRC_PADDR 0x13270000 90#define SYSMMU_FIMCSCLC_PADDR 0x13280000 91#define SYSMMU_FIMCSCLP_PADDR 0x13290000 92#define SYSMMU_FIMCFD_PADDR 0x132A0000 93#define SYSMMU_ISPCPU_PADDR 0x132B0000 94#define SYSMMU_FIMCODC_PADDR 0x132C0000 95#define SYSMMU_FIMCDIS0_PADDR 0x132D0000 96#define SYSMMU_FIMCDIS1_PADDR 0x132E0000 97#define SYSMMU_FIMC3DNR_PADDR 0x132F0000 98#define SYSMMU_FIMCLT0_PADDR 0x13C40000 99#define SYSMMU_FIMCLT1_PADDR 0x13C50000 100#define SYSMMU_FIMCLT2_PADDR 0x13CA0000 101#define SYSMMU_GSCALER0_PADDR 0x13E80000 102#define SYSMMU_GSCALER1_PADDR 0x13E90000 103#define SYSMMU_GSCALER2_PADDR 0x13EA0000 104#define SYSMMU_GSCALER3_PADDR 0x13EB0000 105#define SYSMMU_DISP1_PADDR 0x14640000 106#define SYSMMU_TV_PADDR 0x14650000 107