1/* 2 * Copyright 2017, Data61, CSIRO (ABN 41 687 119 230) 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7/* This file contains definitions related with features in x86 platform 8 * Authors: 9 * Qian Ge 10 */ 11 12#pragma once 13 14/* Exception vector. */ 15 16#define DE_VECTOR 0 17#define DB_VECTOR 1 18#define BP_VECTOR 3 19#define OF_VECTOR 4 20#define BR_VECTOR 5 21#define UD_VECTOR 6 22#define NM_VECTOR 7 23#define DF_VECTOR 8 24#define TS_VECTOR 10 25#define NP_VECTOR 11 26#define SS_VECTOR 12 27#define GP_VECTOR 13 28#define PF_VECTOR 14 29#define MF_VECTOR 16 30#define MC_VECTOR 18 31 32/* Processor flags. */ 33 34/* 35 * EFLAGS bits 36 */ 37#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ 38#define X86_EFLAGS_BIT1 0x00000002 /* Bit 1 - always on */ 39#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ 40#define X86_EFLAGS_AF 0x00000010 /* Auxiliary carry Flag */ 41#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ 42#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ 43#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ 44#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ 45#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ 46#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ 47#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ 48#define X86_EFLAGS_NT 0x00004000 /* Nested Task */ 49#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ 50#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ 51#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ 52#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 53#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 54#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ 55 56/* 57 * Basic CPU control in CR0 58 */ 59#define X86_CR0_PE 0x00000001 /* Protection Enable */ 60#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ 61#define X86_CR0_EM 0x00000004 /* Emulation */ 62#define X86_CR0_TS 0x00000008 /* Task Switched */ 63#define X86_CR0_ET 0x00000010 /* Extension Type */ 64#define X86_CR0_NE 0x00000020 /* Numeric Error */ 65#define X86_CR0_WP 0x00010000 /* Write Protect */ 66#define X86_CR0_AM 0x00040000 /* Alignment Mask */ 67#define X86_CR0_NW 0x20000000 /* Not Write-through */ 68#define X86_CR0_CD 0x40000000 /* Cache Disable */ 69#define X86_CR0_PG 0x80000000 /* Paging */ 70 71/* 72 * Paging options in CR3 73 */ 74#define X86_CR3_PWT 0x00000008 /* Page Write Through */ 75#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ 76#define X86_CR3_PCID_MASK 0x00000fff /* PCID Mask */ 77 78/* 79 * Intel CPU features in CR4 80 */ 81#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ 82#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ 83#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ 84#define X86_CR4_DE 0x00000008 /* enable debugging extensions */ 85#define X86_CR4_PSE 0x00000010 /* enable page size extensions */ 86#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ 87#define X86_CR4_MCE 0x00000040 /* Machine check enable */ 88#define X86_CR4_PGE 0x00000080 /* enable global pages */ 89#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ 90#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ 91#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 92#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ 93#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */ 94#define X86_CR4_PCIDE 0x00020000 /* enable PCID support */ 95#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 96#define X86_CR4_SMEP 0x00100000 /* enable SMEP support */ 97#define X86_CR4_SMAP 0x00200000 /* enable SMAP support */ 98 99/* 100 * x86-64 Task Priority Register, CR8 101 */ 102#define X86_CR8_TPR 0x0000000F /* task priority register */ 103 104/* Reserved bits for CR registers. */ 105#define CR0_RESERVED_BITS \ 106 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ 107 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ 108 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) 109 110#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) 111#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) 112#define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL 113#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \ 114 0xFFFFFF0000000000ULL) 115#define CR4_RESERVED_BITS \ 116 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ 117 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ 118 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ 119 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \ 120 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) 121 122#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) 123 124/* 125 * Definitions of Primary Processor-Based VM-Execution Controls. 126 */ 127#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 128#define CPU_BASED_USE_TSC_OFFSETING 0x00000008 129#define CPU_BASED_HLT_EXITING 0x00000080 130#define CPU_BASED_INVLPG_EXITING 0x00000200 131#define CPU_BASED_MWAIT_EXITING 0x00000400 132#define CPU_BASED_RDPMC_EXITING 0x00000800 133#define CPU_BASED_RDTSC_EXITING 0x00001000 134#define CPU_BASED_CR3_LOAD_EXITING 0x00008000 135#define CPU_BASED_CR3_STORE_EXITING 0x00010000 136#define CPU_BASED_CR8_LOAD_EXITING 0x00080000 137#define CPU_BASED_CR8_STORE_EXITING 0x00100000 138#define CPU_BASED_TPR_SHADOW 0x00200000 139#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 140#define CPU_BASED_MOV_DR_EXITING 0x00800000 141#define CPU_BASED_UNCOND_IO_EXITING 0x01000000 142#define CPU_BASED_USE_IO_BITMAPS 0x02000000 143#define CPU_BASED_USE_MSR_BITMAPS 0x10000000 144#define CPU_BASED_MONITOR_EXITING 0x20000000 145#define CPU_BASED_PAUSE_EXITING 0x40000000 146#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 147/* 148 * Definitions of Secondary Processor-Based VM-Execution Controls. 149 */ 150#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 151#define SECONDARY_EXEC_ENABLE_EPT 0x00000002 152#define SECONDARY_EXEC_RDTSCP 0x00000008 153#define SECONDARY_EXEC_ENABLE_VPID 0x00000020 154#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 155#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 156#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 157#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 158 159#define PIN_BASED_EXT_INTR_MASK 0x00000001 160#define PIN_BASED_NMI_EXITING 0x00000008 161#define PIN_BASED_VIRTUAL_NMIS 0x00000020 162 163#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000002 164#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 165#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 166#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 167#define VM_EXIT_SAVE_IA32_PAT 0x00040000 168#define VM_EXIT_LOAD_IA32_PAT 0x00080000 169#define VM_EXIT_SAVE_IA32_EFER 0x00100000 170#define VM_EXIT_LOAD_IA32_EFER 0x00200000 171#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 172 173#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000002 174#define VM_ENTRY_IA32E_MODE 0x00000200 175#define VM_ENTRY_SMM 0x00000400 176#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 177#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 178#define VM_ENTRY_LOAD_IA32_PAT 0x00004000 179#define VM_ENTRY_LOAD_IA32_EFER 0x00008000 180 181/* Interruption-information format. */ 182 183#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 184#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 185#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 186#define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */ 187#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 188#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 189 190#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK 191#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK 192#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK 193#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK 194 195#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ 196#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ 197#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ 198#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ 199#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ 200 201/* GUEST_INTERRUPTIBILITY_INFO flags. */ 202#define GUEST_INTR_STATE_STI 0x00000001 203#define GUEST_INTR_STATE_MOV_SS 0x00000002 204#define GUEST_INTR_STATE_SMI 0x00000004 205#define GUEST_INTR_STATE_NMI 0x00000008 206 207/* GUEST_ACTIVITY_STATE flags */ 208#define GUEST_ACTIVITY_ACTIVE 0 209#define GUEST_ACTIVITY_HLT 1 210#define GUEST_ACTIVITY_SHUTDOWN 2 211#define GUEST_ACTIVITY_WAIT_SIPI 3 212 213/* Exit Qualifications for MOV for Control Register Access. */ 214#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/ 215#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */ 216#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */ 217#define LMSW_SOURCE_DATA_SHIFT 16 218#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */ 219#define REG_EAX (0 << 8) 220#define REG_ECX (1 << 8) 221#define REG_EDX (2 << 8) 222#define REG_EBX (3 << 8) 223#define REG_ESP (4 << 8) 224#define REG_EBP (5 << 8) 225#define REG_ESI (6 << 8) 226#define REG_EDI (7 << 8) 227#define REG_R8 (8 << 8) 228#define REG_R9 (9 << 8) 229#define REG_R10 (10 << 8) 230#define REG_R11 (11 << 8) 231#define REG_R12 (12 << 8) 232#define REG_R13 (13 << 8) 233#define REG_R14 (14 << 8) 234#define REG_R15 (15 << 8) 235 236/* VM-instruction error numbers. */ 237enum vm_instruction_error_number { 238 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 239 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 240 VMXERR_VMCLEAR_VMXON_POINTER = 3, 241 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 242 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 243 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 244 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 245 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 246 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 247 VMXERR_VMPTRLD_VMXON_POINTER = 10, 248 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 249 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 250 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 251 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 252 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 253 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 254 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 255 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 256 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 257 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 258 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 259 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 260 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 261 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 262 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 263}; 264 265