1// SPDX-License-Identifier: GPL-2.0-or-later 2// Copyright Linux 3 4/* This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19#pragma once 20 21/* 22 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) 23 * 24 * Alan Cox <Alan.Cox@linux.org>, 1995. 25 * Ingo Molnar <mingo@redhat.com>, 1999, 2000 26 */ 27 28/* 29 * This is the IO-APIC register space as specified 30 * by Intel docs: 31 */ 32#define IO_APIC_SLOT_SIZE 1024 33 34#define APIC_ID 0x20 35 36#define APIC_LVR 0x30 37#define APIC_LVR_MASK 0xFF00FF 38#define APIC_LVR_DIRECTED_EOI (BIT(24)) 39#define GET_APIC_VERSION(x) ((x) & 0xFFu) 40#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) 41#ifdef CONFIG_X86_32 42# define APIC_INTEGRATED(x) ((x) & 0xF0u) 43#else 44# define APIC_INTEGRATED(x) (1) 45#endif 46#define APIC_XAPIC(x) ((x) >= 0x14) 47#define APIC_EXT_SPACE(x) ((x) & 0x80000000) 48#define APIC_TASKPRI 0x80 49#define APIC_TPRI_MASK 0xFFu 50#define APIC_ARBPRI 0x90 51#define APIC_ARBPRI_MASK 0xFFu 52#define APIC_PROCPRI 0xA0 53#define APIC_EOI 0xB0 54#define APIC_EOI_ACK 0x0 /* Docs say 0 for future compat. */ 55#define APIC_RRR 0xC0 56#define APIC_LDR 0xD0 57#define APIC_LDR_MASK (0xFFu << 24) 58#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) 59#define SET_APIC_LOGICAL_ID(x) (((x) << 24)) 60#define APIC_ALL_CPUS 0xFFu 61#define APIC_DFR 0xE0 62#define APIC_DFR_CLUSTER 0x0FFFFFFFul 63#define APIC_DFR_FLAT 0xFFFFFFFFul 64#define APIC_SPIV 0xF0 65#define APIC_SPIV_DIRECTED_EOI (BIT(12)) 66#define APIC_SPIV_FOCUS_DISABLED (BIT(9)) 67#define APIC_SPIV_APIC_ENABLED (BIT(8)) 68#define APIC_ISR 0x100 69#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ 70#define APIC_TMR 0x180 71#define APIC_IRR 0x200 72#define APIC_ESR 0x280 73#define APIC_ESR_SEND_CS 0x00001 74#define APIC_ESR_RECV_CS 0x00002 75#define APIC_ESR_SEND_ACC 0x00004 76#define APIC_ESR_RECV_ACC 0x00008 77#define APIC_ESR_SENDILL 0x00020 78#define APIC_ESR_RECVILL 0x00040 79#define APIC_ESR_ILLREGA 0x00080 80#define APIC_LVTCMCI 0x2f0 81#define APIC_ICR 0x300 82#define APIC_DEST_SELF 0x40000 83#define APIC_DEST_ALLINC 0x80000 84#define APIC_DEST_ALLBUT 0xC0000 85#define APIC_ICR_RR_MASK 0x30000 86#define APIC_ICR_RR_INVALID 0x00000 87#define APIC_ICR_RR_INPROG 0x10000 88#define APIC_ICR_RR_VALID 0x20000 89#define APIC_INT_LEVELTRIG 0x08000 90#define APIC_INT_ASSERT 0x04000 91#define APIC_ICR_BUSY 0x01000 92#define APIC_DEST_LOGICAL 0x00800 93#define APIC_DEST_PHYSICAL 0x00000 94#define APIC_DM_FIXED 0x00000 95#define APIC_DM_FIXED_MASK 0x00700 96#define APIC_DM_LOWEST 0x00100 97#define APIC_DM_SMI 0x00200 98#define APIC_DM_REMRD 0x00300 99#define APIC_DM_NMI 0x00400 100#define APIC_DM_INIT 0x00500 101#define APIC_DM_STARTUP 0x00600 102#define APIC_DM_EXTINT 0x00700 103#define APIC_VECTOR_MASK 0x000FF 104#define APIC_ICR2 0x310 105#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) 106#define SET_APIC_DEST_FIELD(x) ((x) << 24) 107#define APIC_LVTT 0x320 108#define APIC_LVTTHMR 0x330 109#define APIC_LVTPC 0x340 110#define APIC_LVT0 0x350 111#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) 112#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) 113#define SET_APIC_TIMER_BASE(x) (((x) << 18)) 114#define APIC_TIMER_BASE_CLKIN 0x0 115#define APIC_TIMER_BASE_TMBASE 0x1 116#define APIC_TIMER_BASE_DIV 0x2 117#define APIC_LVT_TIMER_ONESHOT (0 << 17) 118#define APIC_LVT_TIMER_PERIODIC (BIT(17)) 119#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) 120#define APIC_LVT_MASKED (BIT(16)) 121#define APIC_LVT_LEVEL_TRIGGER (BIT(15)) 122#define APIC_LVT_REMOTE_IRR (BIT(14)) 123#define APIC_INPUT_POLARITY (BIT(13)) 124#define APIC_SEND_PENDING (BIT(12)) 125#define APIC_MODE_MASK 0x700 126#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) 127#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) 128#define APIC_MODE_FIXED 0x0 129#define APIC_MODE_NMI 0x4 130#define APIC_MODE_EXTINT 0x7 131#define APIC_LVT1 0x360 132#define APIC_LVTERR 0x370 133#define APIC_TMICT 0x380 134#define APIC_TMCCT 0x390 135#define APIC_TDCR 0x3E0 136#define APIC_SELF_IPI 0x3F0 137#define APIC_TDR_DIV_TMBASE (BIT(2)) 138#define APIC_TDR_DIV_1 0xB 139#define APIC_TDR_DIV_2 0x0 140#define APIC_TDR_DIV_4 0x1 141#define APIC_TDR_DIV_8 0x2 142#define APIC_TDR_DIV_16 0x3 143#define APIC_TDR_DIV_32 0x8 144#define APIC_TDR_DIV_64 0x9 145#define APIC_TDR_DIV_128 0xA 146#define APIC_EFEAT 0x400 147#define APIC_ECTRL 0x410 148#define APIC_EILVTn(n) (0x500 + 0x10 * n) 149#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ 150#define APIC_EILVT_NR_AMD_10H 4 151#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H 152#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) 153#define APIC_EILVT_MSG_FIX 0x0 154#define APIC_EILVT_MSG_SMI 0x2 155#define APIC_EILVT_MSG_NMI 0x4 156#define APIC_EILVT_MSG_EXT 0x7 157#define APIC_EILVT_MASKED (BIT(16)) 158 159#define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) 160#define APIC_BASE_MSR 0x800 161#define XAPIC_ENABLE (1UL << 11) 162#define X2APIC_ENABLE (1UL << 10) 163 164#ifdef CONFIG_X86_32 165# define MAX_IO_APICS 64 166# define MAX_LOCAL_APIC 256 167#else 168# define MAX_IO_APICS 128 169# define MAX_LOCAL_APIC 32768 170#endif 171 172/* 173 * All x86-64 systems are xAPIC compatible. 174 * In the following, "apicid" is a physical APIC ID. 175 */ 176#define XAPIC_DEST_CPUS_SHIFT 4 177#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) 178#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) 179#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) 180#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) 181#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) 182#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) 183 184/* 185 * the local APIC register structure, memory mapped. Not terribly well 186 * tested, but we might eventually use this one in the future - the 187 * problem why we cannot use it right now is the P5 APIC, it has an 188 * errata which cannot take 8-bit reads and writes, only 32-bit ones ... 189 */ 190#define u32 unsigned int 191 192struct local_apic_regs { 193 194 /*000*/ struct { 195 u32 __reserved[4]; 196 } __reserved_01; 197 198 /*010*/ struct { 199 u32 __reserved[4]; 200 } __reserved_02; 201 202 /*020*/ struct { /* APIC ID Register */ 203 u32 __reserved_1 : 24, 204 phys_apic_id : 4, 205 __reserved_2 : 4; 206 u32 __reserved[3]; 207 } id; 208 209 /*030*/ const 210 struct { /* APIC Version Register */ 211 u32 version : 8, 212 __reserved_1 : 8, 213 max_lvt : 8, 214 __reserved_2 : 8; 215 u32 __reserved[3]; 216 } version; 217 218 /*040*/ struct { 219 u32 __reserved[4]; 220 } __reserved_03; 221 222 /*050*/ struct { 223 u32 __reserved[4]; 224 } __reserved_04; 225 226 /*060*/ struct { 227 u32 __reserved[4]; 228 } __reserved_05; 229 230 /*070*/ struct { 231 u32 __reserved[4]; 232 } __reserved_06; 233 234 /*080*/ struct { /* Task Priority Register */ 235 u32 priority : 8, 236 __reserved_1 : 24; 237 u32 __reserved_2[3]; 238 } tpr; 239 240 /*090*/ const 241 struct { /* Arbitration Priority Register */ 242 u32 priority : 8, 243 __reserved_1 : 24; 244 u32 __reserved_2[3]; 245 } apr; 246 247 /*0A0*/ const 248 struct { /* Processor Priority Register */ 249 u32 priority : 8, 250 __reserved_1 : 24; 251 u32 __reserved_2[3]; 252 } ppr; 253 254 /*0B0*/ struct { /* End Of Interrupt Register */ 255 u32 eoi; 256 u32 __reserved[3]; 257 } eoi; 258 259 /*0C0*/ struct { 260 u32 __reserved[4]; 261 } __reserved_07; 262 263 /*0D0*/ struct { /* Logical Destination Register */ 264 u32 __reserved_1 : 24, 265 logical_dest : 8; 266 u32 __reserved_2[3]; 267 } ldr; 268 269 /*0E0*/ struct { /* Destination Format Register */ 270 u32 __reserved_1 : 28, 271 model : 4; 272 u32 __reserved_2[3]; 273 } dfr; 274 275 /*0F0*/ struct { /* Spurious Interrupt Vector Register */ 276 u32 spurious_vector : 8, 277 apic_enabled : 1, 278 focus_cpu : 1, 279 __reserved_2 : 22; 280 u32 __reserved_3[3]; 281 } svr; 282 283 /*100*/ struct { /* In Service Register */ 284 /*170*/ u32 bitfield; 285 u32 __reserved[3]; 286 } isr [8]; 287 288 /*180*/ struct { /* Trigger Mode Register */ 289 /*1F0*/ u32 bitfield; 290 u32 __reserved[3]; 291 } tmr [8]; 292 293 /*200*/ struct { /* Interrupt Request Register */ 294 /*270*/ u32 bitfield; 295 u32 __reserved[3]; 296 } irr [8]; 297 298 /*280*/ union { /* Error Status Register */ 299 struct { 300 u32 send_cs_error : 1, 301 receive_cs_error : 1, 302 send_accept_error : 1, 303 receive_accept_error : 1, 304 __reserved_1 : 1, 305 send_illegal_vector : 1, 306 receive_illegal_vector : 1, 307 illegal_register_address : 1, 308 __reserved_2 : 24; 309 u32 __reserved_3[3]; 310 } error_bits; 311 struct { 312 u32 errors; 313 u32 __reserved_3[3]; 314 } all_errors; 315 } esr; 316 317 /*290*/ struct { 318 u32 __reserved[4]; 319 } __reserved_08; 320 321 /*2A0*/ struct { 322 u32 __reserved[4]; 323 } __reserved_09; 324 325 /*2B0*/ struct { 326 u32 __reserved[4]; 327 } __reserved_10; 328 329 /*2C0*/ struct { 330 u32 __reserved[4]; 331 } __reserved_11; 332 333 /*2D0*/ struct { 334 u32 __reserved[4]; 335 } __reserved_12; 336 337 /*2E0*/ struct { 338 u32 __reserved[4]; 339 } __reserved_13; 340 341 /*2F0*/ struct { 342 u32 __reserved[4]; 343 } __reserved_14; 344 345 /*300*/ struct { /* Interrupt Command Register 1 */ 346 u32 vector : 8, 347 delivery_mode : 3, 348 destination_mode : 1, 349 delivery_status : 1, 350 __reserved_1 : 1, 351 level : 1, 352 trigger : 1, 353 __reserved_2 : 2, 354 shorthand : 2, 355 __reserved_3 : 12; 356 u32 __reserved_4[3]; 357 } icr1; 358 359 /*310*/ struct { /* Interrupt Command Register 2 */ 360 union { 361 u32 __reserved_1 : 24, 362 phys_dest : 4, 363 __reserved_2 : 4; 364 u32 __reserved_3 : 24, 365 logical_dest : 8; 366 } dest; 367 u32 __reserved_4[3]; 368 } icr2; 369 370 /*320*/ struct { /* LVT - Timer */ 371 u32 vector : 8, 372 __reserved_1 : 4, 373 delivery_status : 1, 374 __reserved_2 : 3, 375 mask : 1, 376 timer_mode : 1, 377 __reserved_3 : 14; 378 u32 __reserved_4[3]; 379 } lvt_timer; 380 381 /*330*/ struct { /* LVT - Thermal Sensor */ 382 u32 vector : 8, 383 delivery_mode : 3, 384 __reserved_1 : 1, 385 delivery_status : 1, 386 __reserved_2 : 3, 387 mask : 1, 388 __reserved_3 : 15; 389 u32 __reserved_4[3]; 390 } lvt_thermal; 391 392 /*340*/ struct { /* LVT - Performance Counter */ 393 u32 vector : 8, 394 delivery_mode : 3, 395 __reserved_1 : 1, 396 delivery_status : 1, 397 __reserved_2 : 3, 398 mask : 1, 399 __reserved_3 : 15; 400 u32 __reserved_4[3]; 401 } lvt_pc; 402 403 /*350*/ struct { /* LVT - LINT0 */ 404 u32 vector : 8, 405 delivery_mode : 3, 406 __reserved_1 : 1, 407 delivery_status : 1, 408 polarity : 1, 409 remote_irr : 1, 410 trigger : 1, 411 mask : 1, 412 __reserved_2 : 15; 413 u32 __reserved_3[3]; 414 } lvt_lint0; 415 416 /*360*/ struct { /* LVT - LINT1 */ 417 u32 vector : 8, 418 delivery_mode : 3, 419 __reserved_1 : 1, 420 delivery_status : 1, 421 polarity : 1, 422 remote_irr : 1, 423 trigger : 1, 424 mask : 1, 425 __reserved_2 : 15; 426 u32 __reserved_3[3]; 427 } lvt_lint1; 428 429 /*370*/ struct { /* LVT - Error */ 430 u32 vector : 8, 431 __reserved_1 : 4, 432 delivery_status : 1, 433 __reserved_2 : 3, 434 mask : 1, 435 __reserved_3 : 15; 436 u32 __reserved_4[3]; 437 } lvt_error; 438 439 /*380*/ struct { /* Timer Initial Count Register */ 440 u32 initial_count; 441 u32 __reserved_2[3]; 442 } timer_icr; 443 444 /*390*/ const 445 struct { /* Timer Current Count Register */ 446 u32 curr_count; 447 u32 __reserved_2[3]; 448 } timer_ccr; 449 450 /*3A0*/ struct { 451 u32 __reserved[4]; 452 } __reserved_16; 453 454 /*3B0*/ struct { 455 u32 __reserved[4]; 456 } __reserved_17; 457 458 /*3C0*/ struct { 459 u32 __reserved[4]; 460 } __reserved_18; 461 462 /*3D0*/ struct { 463 u32 __reserved[4]; 464 } __reserved_19; 465 466 /*3E0*/ struct { /* Timer Divide Configuration Register */ 467 u32 divisor : 4, 468 __reserved_1 : 28; 469 u32 __reserved_2[3]; 470 } timer_dcr; 471 472 /*3F0*/ struct { 473 u32 __reserved[4]; 474 } __reserved_20; 475 476} __attribute__((packed)); 477 478#undef u32 479 480#ifdef CONFIG_X86_32 481#define BAD_APICID 0xFFu 482#else 483#define BAD_APICID 0xFFFFu 484#endif 485 486enum ioapic_irq_destination_types { 487 dest_Fixed = 0, 488 dest_LowestPrio = 1, 489 dest_SMI = 2, 490 dest__reserved_1 = 3, 491 dest_NMI = 4, 492 dest_INIT = 5, 493 dest__reserved_2 = 6, 494 dest_ExtINT = 7 495}; 496 497