1/* 2 * Atheros AR71XX/AR724X/AR913X SoC register definitions 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7 * 8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 */ 14 15#ifndef __ASM_MACH_AR71XX_REGS_H 16#define __ASM_MACH_AR71XX_REGS_H 17 18#define BIT(_x) (1UL << (_x)) 19 20#define AR71XX_APB_BASE 0x18000000 21#define AR71XX_GE0_BASE 0x19000000 22#define AR71XX_GE0_SIZE 0x10000 23#define AR71XX_GE1_BASE 0x1a000000 24#define AR71XX_GE1_SIZE 0x10000 25#define AR71XX_EHCI_BASE 0x1b000000 26#define AR71XX_EHCI_SIZE 0x1000 27#define AR71XX_OHCI_BASE 0x1c000000 28#define AR71XX_OHCI_SIZE 0x1000 29#define AR71XX_SPI_BASE 0x1f000000 30#define AR71XX_SPI_SIZE 0x01000000 31 32#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) 33#define AR71XX_DDR_CTRL_SIZE 0x100 34#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) 35#define AR71XX_UART_SIZE 0x100 36#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 37#define AR71XX_USB_CTRL_SIZE 0x100 38#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) 39#define AR71XX_GPIO_SIZE 0x100 40#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) 41#define AR71XX_PLL_SIZE 0x100 42#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 43#define AR71XX_RESET_SIZE 0x100 44#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) 45#define AR71XX_MII_SIZE 0x100 46 47#define AR71XX_PCI_MEM_BASE 0x10000000 48#define AR71XX_PCI_MEM_SIZE 0x07000000 49 50#define AR71XX_PCI_WIN0_OFFS 0x10000000 51#define AR71XX_PCI_WIN1_OFFS 0x11000000 52#define AR71XX_PCI_WIN2_OFFS 0x12000000 53#define AR71XX_PCI_WIN3_OFFS 0x13000000 54#define AR71XX_PCI_WIN4_OFFS 0x14000000 55#define AR71XX_PCI_WIN5_OFFS 0x15000000 56#define AR71XX_PCI_WIN6_OFFS 0x16000000 57#define AR71XX_PCI_WIN7_OFFS 0x07000000 58 59#define AR71XX_PCI_CFG_BASE \ 60 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) 61#define AR71XX_PCI_CFG_SIZE 0x100 62 63#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 64#define AR7240_USB_CTRL_SIZE 0x100 65#define AR7240_OHCI_BASE 0x1b000000 66#define AR7240_OHCI_SIZE 0x1000 67 68#define AR724X_PCI_MEM_BASE 0x10000000 69#define AR724X_PCI_MEM_SIZE 0x04000000 70 71#define AR724X_PCI_CFG_BASE 0x14000000 72#define AR724X_PCI_CFG_SIZE 0x1000 73#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) 74#define AR724X_PCI_CRP_SIZE 0x1000 75#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) 76#define AR724X_PCI_CTRL_SIZE 0x100 77 78#define AR724X_EHCI_BASE 0x1b000000 79#define AR724X_EHCI_SIZE 0x1000 80 81#define AR913X_EHCI_BASE 0x1b000000 82#define AR913X_EHCI_SIZE 0x1000 83#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) 84#define AR913X_WMAC_SIZE 0x30000 85 86#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) 87#define AR933X_UART_SIZE 0x14 88#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 89#define AR933X_GMAC_SIZE 0x04 90#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 91#define AR933X_WMAC_SIZE 0x20000 92#define AR933X_EHCI_BASE 0x1b000000 93#define AR933X_EHCI_SIZE 0x1000 94 95#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 96#define AR934X_GMAC_SIZE 0x14 97#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 98#define AR934X_WMAC_SIZE 0x20000 99#define AR934X_EHCI_BASE 0x1b000000 100#define AR934X_EHCI_SIZE 0x200 101 102#define QCA955X_PCI_MEM_BASE0 0x10000000 103#define QCA955X_PCI_MEM_BASE1 0x12000000 104#define QCA955X_PCI_MEM_SIZE 0x02000000 105#define QCA955X_PCI_CFG_BASE0 0x14000000 106#define QCA955X_PCI_CFG_BASE1 0x16000000 107#define QCA955X_PCI_CFG_SIZE 0x1000 108#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) 109#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) 110#define QCA955X_PCI_CRP_SIZE 0x1000 111#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) 112#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) 113#define QCA955X_PCI_CTRL_SIZE 0x100 114 115#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 116#define QCA955X_WMAC_SIZE 0x20000 117#define QCA955X_EHCI0_BASE 0x1b000000 118#define QCA955X_EHCI1_BASE 0x1b400000 119#define QCA955X_EHCI_SIZE 0x1000 120#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 121#define QCA955X_GMAC_SIZE 0x40 122 123#define AR9300_OTP_BASE 0x14000 124#define AR9300_OTP_STATUS 0x15f18 125#define AR9300_OTP_STATUS_TYPE 0x7 126#define AR9300_OTP_STATUS_VALID 0x4 127#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 128#define AR9300_OTP_STATUS_SM_BUSY 0x1 129#define AR9300_OTP_READ_DATA 0x15f1c 130 131/* 132 * DDR_CTRL block 133 */ 134#define AR71XX_DDR_REG_PCI_WIN0 0x7c 135#define AR71XX_DDR_REG_PCI_WIN1 0x80 136#define AR71XX_DDR_REG_PCI_WIN2 0x84 137#define AR71XX_DDR_REG_PCI_WIN3 0x88 138#define AR71XX_DDR_REG_PCI_WIN4 0x8c 139#define AR71XX_DDR_REG_PCI_WIN5 0x90 140#define AR71XX_DDR_REG_PCI_WIN6 0x94 141#define AR71XX_DDR_REG_PCI_WIN7 0x98 142#define AR71XX_DDR_REG_FLUSH_GE0 0x9c 143#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 144#define AR71XX_DDR_REG_FLUSH_USB 0xa4 145#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 146 147#define AR724X_DDR_REG_FLUSH_GE0 0x7c 148#define AR724X_DDR_REG_FLUSH_GE1 0x80 149#define AR724X_DDR_REG_FLUSH_USB 0x84 150#define AR724X_DDR_REG_FLUSH_PCIE 0x88 151 152#define AR913X_DDR_REG_FLUSH_GE0 0x7c 153#define AR913X_DDR_REG_FLUSH_GE1 0x80 154#define AR913X_DDR_REG_FLUSH_USB 0x84 155#define AR913X_DDR_REG_FLUSH_WMAC 0x88 156 157#define AR933X_DDR_REG_FLUSH_GE0 0x7c 158#define AR933X_DDR_REG_FLUSH_GE1 0x80 159#define AR933X_DDR_REG_FLUSH_USB 0x84 160#define AR933X_DDR_REG_FLUSH_WMAC 0x88 161 162#define AR934X_DDR_REG_FLUSH_GE0 0x9c 163#define AR934X_DDR_REG_FLUSH_GE1 0xa0 164#define AR934X_DDR_REG_FLUSH_USB 0xa4 165#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 166#define AR934X_DDR_REG_FLUSH_WMAC 0xac 167 168/* 169 * PLL block 170 */ 171#define AR71XX_PLL_REG_CPU_CONFIG 0x00 172#define AR71XX_PLL_REG_SEC_CONFIG 0x04 173#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 174#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 175 176#define AR71XX_PLL_DIV_SHIFT 3 177#define AR71XX_PLL_DIV_MASK 0x1f 178#define AR71XX_CPU_DIV_SHIFT 16 179#define AR71XX_CPU_DIV_MASK 0x3 180#define AR71XX_DDR_DIV_SHIFT 18 181#define AR71XX_DDR_DIV_MASK 0x3 182#define AR71XX_AHB_DIV_SHIFT 20 183#define AR71XX_AHB_DIV_MASK 0x7 184 185#define AR71XX_ETH0_PLL_SHIFT 17 186#define AR71XX_ETH1_PLL_SHIFT 19 187 188#define AR724X_PLL_REG_CPU_CONFIG 0x00 189#define AR724X_PLL_REG_PCIE_CONFIG 0x18 190 191#define AR724X_PLL_DIV_SHIFT 0 192#define AR724X_PLL_DIV_MASK 0x3ff 193#define AR724X_PLL_REF_DIV_SHIFT 10 194#define AR724X_PLL_REF_DIV_MASK 0xf 195#define AR724X_AHB_DIV_SHIFT 19 196#define AR724X_AHB_DIV_MASK 0x1 197#define AR724X_DDR_DIV_SHIFT 22 198#define AR724X_DDR_DIV_MASK 0x3 199 200#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c 201 202#define AR913X_PLL_REG_CPU_CONFIG 0x00 203#define AR913X_PLL_REG_ETH_CONFIG 0x04 204#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 205#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 206 207#define AR913X_PLL_DIV_SHIFT 0 208#define AR913X_PLL_DIV_MASK 0x3ff 209#define AR913X_DDR_DIV_SHIFT 22 210#define AR913X_DDR_DIV_MASK 0x3 211#define AR913X_AHB_DIV_SHIFT 19 212#define AR913X_AHB_DIV_MASK 0x1 213 214#define AR913X_ETH0_PLL_SHIFT 20 215#define AR913X_ETH1_PLL_SHIFT 22 216 217#define AR933X_PLL_CPU_CONFIG_REG 0x00 218#define AR933X_PLL_CLOCK_CTRL_REG 0x08 219 220#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 221#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f 222#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 223#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 224#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 225#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 226 227#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) 228#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 229#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 230#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 231#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 232#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 233#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 234 235#define AR934X_PLL_CPU_CONFIG_REG 0x00 236#define AR934X_PLL_DDR_CONFIG_REG 0x04 237#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 238#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c 239 240#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 241#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 242#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 243#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f 244#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 245#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 246#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 247#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 248 249#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 250#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 251#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 252#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f 253#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 254#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 255#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 256#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 257 258#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 259#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 260#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 261#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 262#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 263#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 264#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 265#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 266#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 267#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 268#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 269#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 270 271#define QCA955X_PLL_CPU_CONFIG_REG 0x00 272#define QCA955X_PLL_DDR_CONFIG_REG 0x04 273#define QCA955X_PLL_CLK_CTRL_REG 0x08 274 275#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 276#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 277#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 278#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f 279#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 280#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 281#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 282#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 283 284#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 285#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 286#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 287#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f 288#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 289#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 290#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 291#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 292 293#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 294#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 295#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 296#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 297#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 298#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 299#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 300#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 301#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 302#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 303#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 304#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 305 306/* 307 * USB_CONFIG block 308 */ 309#define AR71XX_USB_CTRL_REG_FLADJ 0x00 310#define AR71XX_USB_CTRL_REG_CONFIG 0x04 311 312/* 313 * RESET block 314 */ 315#define AR71XX_RESET_REG_TIMER 0x00 316#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 317#define AR71XX_RESET_REG_WDOG_CTRL 0x08 318#define AR71XX_RESET_REG_WDOG 0x0c 319#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 320#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 321#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 322#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c 323#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 324#define AR71XX_RESET_REG_RESET_MODULE 0x24 325#define AR71XX_RESET_REG_PERFC_CTRL 0x2c 326#define AR71XX_RESET_REG_PERFC0 0x30 327#define AR71XX_RESET_REG_PERFC1 0x34 328#define AR71XX_RESET_REG_REV_ID 0x90 329 330#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 331#define AR913X_RESET_REG_RESET_MODULE 0x1c 332#define AR913X_RESET_REG_PERF_CTRL 0x20 333#define AR913X_RESET_REG_PERFC0 0x24 334#define AR913X_RESET_REG_PERFC1 0x28 335 336#define AR724X_RESET_REG_RESET_MODULE 0x1c 337 338#define AR933X_RESET_REG_RESET_MODULE 0x1c 339#define AR933X_RESET_REG_BOOTSTRAP 0xac 340 341#define AR934X_RESET_REG_RESET_MODULE 0x1c 342#define AR934X_RESET_REG_BOOTSTRAP 0xb0 343#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 344 345#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 346#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac 347 348#define MISC_INT_ETHSW BIT(12) 349#define MISC_INT_TIMER4 BIT(10) 350#define MISC_INT_TIMER3 BIT(9) 351#define MISC_INT_TIMER2 BIT(8) 352#define MISC_INT_DMA BIT(7) 353#define MISC_INT_OHCI BIT(6) 354#define MISC_INT_PERFC BIT(5) 355#define MISC_INT_WDOG BIT(4) 356#define MISC_INT_UART BIT(3) 357#define MISC_INT_GPIO BIT(2) 358#define MISC_INT_ERROR BIT(1) 359#define MISC_INT_TIMER BIT(0) 360 361#define AR71XX_RESET_EXTERNAL BIT(28) 362#define AR71XX_RESET_FULL_CHIP BIT(24) 363#define AR71XX_RESET_CPU_NMI BIT(21) 364#define AR71XX_RESET_CPU_COLD BIT(20) 365#define AR71XX_RESET_DMA BIT(19) 366#define AR71XX_RESET_SLIC BIT(18) 367#define AR71XX_RESET_STEREO BIT(17) 368#define AR71XX_RESET_DDR BIT(16) 369#define AR71XX_RESET_GE1_MAC BIT(13) 370#define AR71XX_RESET_GE1_PHY BIT(12) 371#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) 372#define AR71XX_RESET_GE0_MAC BIT(9) 373#define AR71XX_RESET_GE0_PHY BIT(8) 374#define AR71XX_RESET_USB_OHCI_DLL BIT(6) 375#define AR71XX_RESET_USB_HOST BIT(5) 376#define AR71XX_RESET_USB_PHY BIT(4) 377#define AR71XX_RESET_PCI_BUS BIT(1) 378#define AR71XX_RESET_PCI_CORE BIT(0) 379 380#define AR7240_RESET_USB_HOST BIT(5) 381#define AR7240_RESET_OHCI_DLL BIT(3) 382 383#define AR724X_RESET_GE1_MDIO BIT(23) 384#define AR724X_RESET_GE0_MDIO BIT(22) 385#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 386#define AR724X_RESET_PCIE_PHY BIT(7) 387#define AR724X_RESET_PCIE BIT(6) 388#define AR724X_RESET_USB_HOST BIT(5) 389#define AR724X_RESET_USB_PHY BIT(4) 390#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) 391 392#define AR913X_RESET_AMBA2WMAC BIT(22) 393#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) 394#define AR913X_RESET_USB_HOST BIT(5) 395#define AR913X_RESET_USB_PHY BIT(4) 396 397#define AR933X_RESET_GE1_MDIO BIT(23) 398#define AR933X_RESET_GE0_MDIO BIT(22) 399#define AR933X_RESET_GE1_MAC BIT(13) 400#define AR933X_RESET_WMAC BIT(11) 401#define AR933X_RESET_GE0_MAC BIT(9) 402#define AR933X_RESET_USB_HOST BIT(5) 403#define AR933X_RESET_USB_PHY BIT(4) 404#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) 405 406#define AR934X_RESET_HOST BIT(31) 407#define AR934X_RESET_SLIC BIT(30) 408#define AR934X_RESET_HDMA BIT(29) 409#define AR934X_RESET_EXTERNAL BIT(28) 410#define AR934X_RESET_RTC BIT(27) 411#define AR934X_RESET_PCIE_EP_INT BIT(26) 412#define AR934X_RESET_CHKSUM_ACC BIT(25) 413#define AR934X_RESET_FULL_CHIP BIT(24) 414#define AR934X_RESET_GE1_MDIO BIT(23) 415#define AR934X_RESET_GE0_MDIO BIT(22) 416#define AR934X_RESET_CPU_NMI BIT(21) 417#define AR934X_RESET_CPU_COLD BIT(20) 418#define AR934X_RESET_HOST_RESET_INT BIT(19) 419#define AR934X_RESET_PCIE_EP BIT(18) 420#define AR934X_RESET_UART1 BIT(17) 421#define AR934X_RESET_DDR BIT(16) 422#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 423#define AR934X_RESET_NANDF BIT(14) 424#define AR934X_RESET_GE1_MAC BIT(13) 425#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) 426#define AR934X_RESET_USB_PHY_ANALOG BIT(11) 427#define AR934X_RESET_HOST_DMA_INT BIT(10) 428#define AR934X_RESET_GE0_MAC BIT(9) 429#define AR934X_RESET_ETH_SWITCH BIT(8) 430#define AR934X_RESET_PCIE_PHY BIT(7) 431#define AR934X_RESET_PCIE BIT(6) 432#define AR934X_RESET_USB_HOST BIT(5) 433#define AR934X_RESET_USB_PHY BIT(4) 434#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) 435#define AR934X_RESET_LUT BIT(2) 436#define AR934X_RESET_MBOX BIT(1) 437#define AR934X_RESET_I2S BIT(0) 438 439#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) 440#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) 441#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) 442 443#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) 444#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) 445#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) 446#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) 447#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) 448#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) 449#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) 450#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) 451#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) 452#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) 453#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) 454#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) 455#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) 456#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 457#define AR934X_BOOTSTRAP_DDR1 BIT(0) 458 459#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) 460 461#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 462#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 463#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 464#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) 465#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) 466#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) 467#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) 468#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) 469#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) 470#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ 471 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ 472 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) 473 474#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ 475 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ 476 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 477 AR934X_PCIE_WMAC_INT_PCIE_RC3) 478 479#define QCA955X_EXT_INT_WMAC_MISC BIT(0) 480#define QCA955X_EXT_INT_WMAC_TX BIT(1) 481#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) 482#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) 483#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) 484#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) 485#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) 486#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) 487#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) 488#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) 489#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) 490#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) 491#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) 492#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) 493#define QCA955X_EXT_INT_USB1 BIT(24) 494#define QCA955X_EXT_INT_USB2 BIT(28) 495 496#define QCA955X_EXT_INT_WMAC_ALL \ 497 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ 498 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) 499 500#define QCA955X_EXT_INT_PCIE_RC1_ALL \ 501 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ 502 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ 503 QCA955X_EXT_INT_PCIE_RC1_INT3) 504 505#define QCA955X_EXT_INT_PCIE_RC2_ALL \ 506 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ 507 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ 508 QCA955X_EXT_INT_PCIE_RC2_INT3) 509 510#define REV_ID_MAJOR_MASK 0xfff0 511#define REV_ID_MAJOR_AR71XX 0x00a0 512#define REV_ID_MAJOR_AR913X 0x00b0 513#define REV_ID_MAJOR_AR7240 0x00c0 514#define REV_ID_MAJOR_AR7241 0x0100 515#define REV_ID_MAJOR_AR7242 0x1100 516#define REV_ID_MAJOR_AR9330 0x0110 517#define REV_ID_MAJOR_AR9331 0x1110 518#define REV_ID_MAJOR_AR9341 0x0120 519#define REV_ID_MAJOR_AR9342 0x1120 520#define REV_ID_MAJOR_AR9344 0x2120 521#define REV_ID_MAJOR_QCA9558 0x1130 522 523#define AR71XX_REV_ID_MINOR_MASK 0x3 524#define AR71XX_REV_ID_MINOR_AR7130 0x0 525#define AR71XX_REV_ID_MINOR_AR7141 0x1 526#define AR71XX_REV_ID_MINOR_AR7161 0x2 527#define AR71XX_REV_ID_REVISION_MASK 0x3 528#define AR71XX_REV_ID_REVISION_SHIFT 2 529 530#define AR913X_REV_ID_MINOR_MASK 0x3 531#define AR913X_REV_ID_MINOR_AR9130 0x0 532#define AR913X_REV_ID_MINOR_AR9132 0x1 533#define AR913X_REV_ID_REVISION_MASK 0x3 534#define AR913X_REV_ID_REVISION_SHIFT 2 535 536#define AR933X_REV_ID_REVISION_MASK 0x3 537 538#define AR724X_REV_ID_REVISION_MASK 0x3 539 540#define AR934X_REV_ID_REVISION_MASK 0xf 541 542#define AR944X_REV_ID_REVISION_MASK 0xf 543 544/* 545 * SPI block 546 */ 547#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ 548#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ 549#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ 550#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ 551 552#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ 553 554#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ 555#define AR71XX_SPI_CTRL_DIV_MASK 0x3f 556 557#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ 558#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ 559#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 560#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) 561#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) 562#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) 563#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ 564 AR71XX_SPI_IOC_CS2) 565 566/* 567 * GPIO block 568 */ 569#define AR71XX_GPIO_REG_OE 0x00 570#define AR71XX_GPIO_REG_IN 0x04 571#define AR71XX_GPIO_REG_OUT 0x08 572#define AR71XX_GPIO_REG_SET 0x0c 573#define AR71XX_GPIO_REG_CLEAR 0x10 574#define AR71XX_GPIO_REG_INT_MODE 0x14 575#define AR71XX_GPIO_REG_INT_TYPE 0x18 576#define AR71XX_GPIO_REG_INT_POLARITY 0x1c 577#define AR71XX_GPIO_REG_INT_PENDING 0x20 578#define AR71XX_GPIO_REG_INT_ENABLE 0x24 579#define AR71XX_GPIO_REG_FUNC 0x28 580 581#define AR934X_GPIO_REG_OUT_FUNC0 0x2c 582#define AR934X_GPIO_REG_OUT_FUNC1 0x30 583#define AR934X_GPIO_REG_OUT_FUNC2 0x34 584#define AR934X_GPIO_REG_OUT_FUNC3 0x38 585#define AR934X_GPIO_REG_OUT_FUNC4 0x3c 586#define AR934X_GPIO_REG_OUT_FUNC5 0x40 587#define AR934X_GPIO_REG_FUNC 0x6c 588 589#define AR71XX_GPIO_COUNT 16 590#define AR724X_GPIO_COUNT 18 591#define AR913X_GPIO_COUNT 22 592#define AR933X_GPIO_COUNT 30 593#define AR934X_GPIO_COUNT 23 594#define QCA955X_GPIO_COUNT 24 595 596#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) 597#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) 598#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) 599#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) 600#define AR71XX_GPIO_FUNC_UART_EN BIT(8) 601#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) 602#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) 603 604#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) 605#define AR724X_GPIO_FUNC_SPI_EN BIT(18) 606#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 607#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 608#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) 609#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) 610#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) 611#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) 612#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) 613#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 614#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 615#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 616#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 617#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 618#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 619#define AR724X_GPIO_FUNC_UART_EN BIT(1) 620#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) 621 622#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) 623#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) 624#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) 625#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) 626#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) 627#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) 628#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) 629#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) 630#define AR913X_GPIO_FUNC_UART_EN BIT(8) 631#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) 632 633#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) 634#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) 635#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) 636#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) 637#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) 638#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) 639#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) 640#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) 641#define AR933X_GPIO_FUNC_SPI_EN BIT(18) 642#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) 643#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) 644#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) 645#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) 646#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) 647#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) 648#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) 649#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) 650#define AR933X_GPIO_FUNC_UART_EN BIT(1) 651#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) 652 653#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) 654#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) 655#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) 656 657#define AR934X_GPIO_OUT_GPIO 0x00 658 659/* 660 * MII_CTRL block 661 */ 662#define AR71XX_MII_REG_MII0_CTRL 0x00 663#define AR71XX_MII_REG_MII1_CTRL 0x04 664 665#define AR71XX_MII_CTRL_IF_MASK 3 666#define AR71XX_MII_CTRL_SPEED_SHIFT 4 667#define AR71XX_MII_CTRL_SPEED_MASK 3 668#define AR71XX_MII_CTRL_SPEED_10 0 669#define AR71XX_MII_CTRL_SPEED_100 1 670#define AR71XX_MII_CTRL_SPEED_1000 2 671 672#define AR71XX_MII0_CTRL_IF_GMII 0 673#define AR71XX_MII0_CTRL_IF_MII 1 674#define AR71XX_MII0_CTRL_IF_RGMII 2 675#define AR71XX_MII0_CTRL_IF_RMII 3 676 677#define AR71XX_MII1_CTRL_IF_RGMII 0 678#define AR71XX_MII1_CTRL_IF_RMII 1 679 680/* 681 * AR933X GMAC interface 682 */ 683#define AR933X_GMAC_REG_ETH_CFG 0x00 684 685#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) 686#define AR933X_ETH_CFG_MII_GE0 BIT(1) 687#define AR933X_ETH_CFG_GMII_GE0 BIT(2) 688#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) 689#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) 690#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) 691#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) 692#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) 693#define AR933X_ETH_CFG_RMII_GE0 BIT(9) 694#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 695#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) 696 697/* 698 * AR934X GMAC Interface 699 */ 700#define AR934X_GMAC_REG_ETH_CFG 0x00 701 702#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) 703#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) 704#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) 705#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) 706#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) 707#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) 708#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) 709#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) 710#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) 711#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) 712#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) 713#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) 714#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) 715 716/* 717 * QCA955X GMAC Interface 718 */ 719 720#define QCA955X_GMAC_REG_ETH_CFG 0x00 721 722#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0) 723#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6) 724 725#endif /* __ASM_MACH_AR71XX_REGS_H */ 726