1/*
2 *  Atheros AR71xx SoC specific platform data definitions
3 *
4 *  Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
5 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 *  This program is free software; you can redistribute it and/or modify it
8 *  under the terms of the GNU General Public License version 2 as published
9 *  by the Free Software Foundation.
10 */
11
12#ifndef __ASM_MACH_ATH79_PLATFORM_H
13#define __ASM_MACH_ATH79_PLATFORM_H
14
15#include <linux/if_ether.h>
16#include <linux/skbuff.h>
17#include <linux/phy.h>
18#include <linux/spi/spi.h>
19
20struct ag71xx_switch_platform_data {
21	u8		phy4_mii_en:1;
22	u8		phy_poll_mask;
23};
24
25struct ag71xx_platform_data {
26	phy_interface_t	phy_if_mode;
27	u32		phy_mask;
28	int		speed;
29	int		duplex;
30	u32		reset_bit;
31	u8		mac_addr[ETH_ALEN];
32	struct device	*mii_bus_dev;
33
34	u8		has_gbit:1;
35	u8		is_ar91xx:1;
36	u8		is_ar7240:1;
37	u8		is_ar724x:1;
38	u8		has_ar8216:1;
39	u8		use_flow_control:1;
40
41	struct ag71xx_switch_platform_data *switch_data;
42
43	void		(*ddr_flush)(void);
44	void		(*set_speed)(int speed);
45
46	u32		fifo_cfg1;
47	u32		fifo_cfg2;
48	u32		fifo_cfg3;
49
50	unsigned int	max_frame_len;
51	unsigned int	desc_pktlen_mask;
52};
53
54struct ag71xx_mdio_platform_data {
55	u32		phy_mask;
56	u8		builtin_switch:1;
57	u8		is_ar7240:1;
58	u8		is_ar9330:1;
59	u8		is_ar934x:1;
60	unsigned long	mdio_clock;
61	unsigned long	ref_clock;
62
63	void		(*reset)(struct mii_bus *bus);
64};
65
66#endif /* __ASM_MACH_ATH79_PLATFORM_H */
67