1/* 2 * OpenMesh OM5P-ACv2 support 3 * 4 * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com> 5 * Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com> 6 * Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published 10 * by the Free Software Foundation. 11 */ 12 13#include <linux/gpio.h> 14#include <linux/version.h> 15#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) 16#include <linux/mdio-gpio.h> 17#else 18#include <linux/platform_data/mdio-gpio.h> 19#endif 20#include <linux/mtd/mtd.h> 21#include <linux/mtd/partitions.h> 22#include <linux/platform_device.h> 23#include <linux/i2c.h> 24#include <linux/i2c-algo-bit.h> 25#include <linux/i2c-gpio.h> 26#include <linux/platform_data/phy-at803x.h> 27 28#include <asm/mach-ath79/ar71xx_regs.h> 29#include <asm/mach-ath79/ath79.h> 30 31#include "common.h" 32#include "dev-ap9x-pci.h" 33#include "dev-eth.h" 34#include "dev-gpio-buttons.h" 35#include "dev-leds-gpio.h" 36#include "dev-m25p80.h" 37#include "dev-wmac.h" 38#include "machtypes.h" 39#include "pci.h" 40 41#define OM5PACV2_GPIO_LED_POWER 14 42#define OM5PACV2_GPIO_LED_GREEN 13 43#define OM5PACV2_GPIO_LED_RED 23 44#define OM5PACV2_GPIO_LED_YELLOW 15 45#define OM5PACV2_GPIO_BTN_RESET 1 46#define OM5PACV2_GPIO_I2C_SCL 18 47#define OM5PACV2_GPIO_I2C_SDA 19 48#define OM5PACV2_GPIO_PA_DCDC 2 49#define OM5PACV2_GPIO_PA_HIGH 16 50 51#define OM5PACV2_KEYS_POLL_INTERVAL 20 /* msecs */ 52#define OM5PACV2_KEYS_DEBOUNCE_INTERVAL (3 * OM5PACV2_KEYS_POLL_INTERVAL) 53 54#define OM5PACV2_WMAC_CALDATA_OFFSET 0x1000 55 56static struct gpio_led om5pacv2_leds_gpio[] __initdata = { 57 { 58 .name = "om5pac:blue:power", 59 .gpio = OM5PACV2_GPIO_LED_POWER, 60 .active_low = 1, 61 }, { 62 .name = "om5pac:red:wifi", 63 .gpio = OM5PACV2_GPIO_LED_RED, 64 .active_low = 1, 65 }, { 66 .name = "om5pac:yellow:wifi", 67 .gpio = OM5PACV2_GPIO_LED_YELLOW, 68 .active_low = 1, 69 }, { 70 .name = "om5pac:green:wifi", 71 .gpio = OM5PACV2_GPIO_LED_GREEN, 72 .active_low = 1, 73 } 74}; 75 76static struct gpio_keys_button om5pacv2_gpio_keys[] __initdata = { 77 { 78 .desc = "reset", 79 .type = EV_KEY, 80 .code = KEY_RESTART, 81 .debounce_interval = OM5PACV2_KEYS_DEBOUNCE_INTERVAL, 82 .gpio = OM5PACV2_GPIO_BTN_RESET, 83 .active_low = 1, 84 } 85}; 86 87static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata = { 88 .sda_pin = OM5PACV2_GPIO_I2C_SDA, 89 .scl_pin = OM5PACV2_GPIO_I2C_SCL, 90 .udelay = 10, 91 .sda_is_open_drain = 1, 92 .scl_is_open_drain = 1, 93}; 94 95static struct platform_device om5pacv2_i2c_device = { 96 .name = "i2c-gpio", 97 .id = 0, 98 .dev = { 99 .platform_data = &om5pacv2_i2c_device_platdata, 100 }, 101}; 102 103static struct i2c_board_info om5pacv2_i2c_devs[] __initdata = { 104 { 105 I2C_BOARD_INFO("tmp423", 0x4e), 106 }, 107}; 108 109static struct flash_platform_data om5pacv2_flash_data = { 110 .type = "mx25l12805d", 111}; 112 113static struct at803x_platform_data om5pacv2_an_at803x_data = { 114 .disable_smarteee = 1, 115 .enable_rgmii_rx_delay = 1, 116 .enable_rgmii_tx_delay = 1, 117}; 118 119static struct at803x_platform_data om5pacv2_an_at8031_data = { 120 .disable_smarteee = 1, 121 .enable_rgmii_rx_delay = 1, 122 .enable_rgmii_tx_delay = 1, 123}; 124 125static struct mdio_board_info om5pacv2_an_mdio0_info[] = { 126 { 127 .bus_id = "ag71xx-mdio.0", 128 .phy_addr = 4, 129 .platform_data = &om5pacv2_an_at803x_data, 130 }, 131 { 132 .bus_id = "ag71xx-mdio.1", 133 .phy_addr = 1, 134 .platform_data = &om5pacv2_an_at8031_data, 135 }, 136}; 137 138static void __init om5p_acv2_setup_qca955x_eth_cfg(u32 mask, 139 unsigned int rxd, 140 unsigned int rxdv, 141 unsigned int txd, 142 unsigned int txe) 143{ 144 void __iomem *base; 145 u32 t; 146 147 base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); 148 149 t = mask; 150 t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; 151 t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; 152 t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; 153 t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; 154 155 __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); 156 157 iounmap(base); 158} 159 160static void __init om5p_acv2_setup(void) 161{ 162 u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); 163 u8 mac[6]; 164 165 /* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */ 166 ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE); 167 ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO); 168 ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO); 169 gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH, 170 "PA DC/DC"); 171 gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH"); 172 173 /* temperature sensor */ 174 platform_device_register(&om5pacv2_i2c_device); 175 i2c_register_board_info(0, om5pacv2_i2c_devs, 176 ARRAY_SIZE(om5pacv2_i2c_devs)); 177 178 ath79_register_m25p80(&om5pacv2_flash_data); 179 ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio), 180 om5pacv2_leds_gpio); 181 ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL, 182 ARRAY_SIZE(om5pacv2_gpio_keys), 183 om5pacv2_gpio_keys); 184 185 ath79_init_mac(mac, art, 0x02); 186 ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac); 187 188 om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0); 189 ath79_register_mdio(0, 0x0); 190 ath79_register_mdio(1, 0x0); 191 192 mdiobus_register_board_info(om5pacv2_an_mdio0_info, 193 ARRAY_SIZE(om5pacv2_an_mdio0_info)); 194 195 ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); 196 ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); 197 198 /* GMAC0 is connected to the PHY4 */ 199 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; 200 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; 201 ath79_eth0_data.phy_mask = BIT(4); 202 ath79_eth0_pll_data.pll_1000 = 0x82000101; 203 ath79_eth0_pll_data.pll_100 = 0x80000101; 204 ath79_eth0_pll_data.pll_10 = 0x80001313; 205 ath79_register_eth(0); 206 207 /* GMAC1 is connected to MDIO1 in SGMII mode */ 208 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; 209 ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; 210 ath79_eth1_data.phy_mask = BIT(1); 211 ath79_eth1_pll_data.pll_1000 = 0x03000101; 212 ath79_eth1_pll_data.pll_100 = 0x80000101; 213 ath79_eth1_pll_data.pll_10 = 0x80001313; 214 ath79_eth1_data.speed = SPEED_1000; 215 ath79_eth1_data.duplex = DUPLEX_FULL; 216 ath79_register_eth(1); 217 218 ath79_register_pci(); 219} 220 221MIPS_MACHINE(ATH79_MACH_OM5P_ACv2, "OM5P-ACv2", "OpenMesh OM5P ACv2", om5p_acv2_setup); 222