1/*
2 *  EnGenius ESR900 board support
3 *
4 *  Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
5 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 *  This program is free software; you can redistribute it and/or modify it
8 *  under the terms of the GNU General Public License version 2 as published
9 *  by the Free Software Foundation.
10 */
11
12#define pr_fmt(fmt) "esr900: " fmt
13
14#include <linux/platform_device.h>
15#include <linux/ar8216_platform.h>
16
17#include <asm/mach-ath79/ar71xx_regs.h>
18
19#include "common.h"
20#include "pci.h"
21#include "dev-ap9x-pci.h"
22#include "dev-gpio-buttons.h"
23#include "dev-eth.h"
24#include "dev-leds-gpio.h"
25#include "dev-m25p80.h"
26#include "dev-usb.h"
27#include "dev-wmac.h"
28#include "machtypes.h"
29#include "nvram.h"
30
31#define ESR900_GPIO_LED_POWER           2
32#define ESR900_GPIO_LED_WLAN_2G         13
33#define ESR900_GPIO_LED_WPS_BLUE        19
34#define ESR900_GPIO_LED_WPS_AMBER       22
35#define ESR900_GPIO_LED_WLAN_5G         23
36
37#define ESR900_GPIO_BTN_WPS             16
38#define ESR900_GPIO_BTN_RESET           17
39
40#define ESR900_KEYS_POLL_INTERVAL       20 /* msecs */
41#define ESR900_KEYS_DEBOUNCE_INTERVAL   (3 * ESR900_KEYS_POLL_INTERVAL)
42
43#define ESR900_CALDATA_ADDR             0x1fff0000
44#define ESR900_WMAC_CALDATA_OFFSET      0x1000
45#define ESR900_PCIE_CALDATA_OFFSET      0x5000
46
47#define ESR900_CONFIG_ADDR              0x1f030000
48#define ESR900_CONFIG_SIZE              0x10000
49
50#define ESR900_LAN_PHYMASK              BIT(0)
51#define ESR900_WAN_PHYMASK              BIT(5)
52#define ESR900_MDIO_MASK                (~(ESR900_LAN_PHYMASK | ESR900_WAN_PHYMASK))
53
54static struct gpio_led esr900_leds_gpio[] __initdata = {
55	{
56		.name		= "engenius:amber:power",
57		.gpio		= ESR900_GPIO_LED_POWER,
58		.active_low	= 1,
59	},
60	{
61		.name		= "engenius:blue:wlan-2g",
62		.gpio		= ESR900_GPIO_LED_WLAN_2G,
63		.active_low	= 1,
64	},
65	{
66		.name		= "engenius:blue:wps",
67		.gpio		= ESR900_GPIO_LED_WPS_BLUE,
68		.active_low	= 1,
69	},
70	{
71		.name		= "engenius:amber:wps",
72		.gpio		= ESR900_GPIO_LED_WPS_AMBER,
73		.active_low	= 1,
74	},
75	{
76		.name		= "engenius:blue:wlan-5g",
77		.gpio		= ESR900_GPIO_LED_WLAN_5G,
78		.active_low	= 1,
79	}
80};
81
82static struct gpio_keys_button esr900_gpio_keys[] __initdata = {
83	{
84		.desc		= "WPS button",
85		.type		= EV_KEY,
86		.code		= KEY_WPS_BUTTON,
87		.debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL,
88		.gpio		= ESR900_GPIO_BTN_WPS,
89		.active_low	= 1,
90	},
91	{
92		.desc		= "Reset button",
93		.type		= EV_KEY,
94		.code		= KEY_RESTART,
95		.debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL,
96		.gpio		= ESR900_GPIO_BTN_RESET,
97		.active_low	= 1,
98	},
99};
100
101static struct ar8327_pad_cfg esr900_ar8327_pad0_cfg = {
102	/* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */
103	.mode = AR8327_PAD_MAC_RGMII,
104	.txclk_delay_en = true,
105	.rxclk_delay_en = true,
106	.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
107	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
108};
109
110static struct ar8327_pad_cfg esr900_ar8327_pad6_cfg = {
111	/* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
112	.mode = AR8327_PAD_MAC_SGMII,
113	.rxclk_delay_en = true,
114	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
115};
116
117static struct ar8327_platform_data esr900_ar8327_data = {
118	.pad0_cfg = &esr900_ar8327_pad0_cfg,
119	.pad6_cfg = &esr900_ar8327_pad6_cfg,
120	.port0_cfg = {
121		.force_link = 1,
122		.speed = AR8327_PORT_SPEED_1000,
123		.duplex = 1,
124		.txpause = 1,
125		.rxpause = 1,
126	},
127	.port6_cfg = {
128		.force_link = 1,
129		.speed = AR8327_PORT_SPEED_1000,
130		.duplex = 1,
131		.txpause = 1,
132		.rxpause = 1,
133	},
134};
135
136static struct mdio_board_info esr900_mdio0_info[] = {
137	{
138		.bus_id = "ag71xx-mdio.0",
139		.phy_addr = 0,
140		.platform_data = &esr900_ar8327_data,
141	},
142};
143
144static void __init esr900_setup(void)
145{
146	const char *config = (char *) KSEG1ADDR(ESR900_CONFIG_ADDR);
147	u8 *art = (u8 *) KSEG1ADDR(ESR900_CALDATA_ADDR);
148	u8 lan_mac[ETH_ALEN];
149	u8 wlan0_mac[ETH_ALEN];
150	u8 wlan1_mac[ETH_ALEN];
151
152	if (ath79_nvram_parse_mac_addr(config, ESR900_CONFIG_SIZE,
153				       "ethaddr=", lan_mac) == 0) {
154		ath79_init_local_mac(ath79_eth0_data.mac_addr, lan_mac);
155		ath79_init_mac(wlan0_mac, lan_mac, 0);
156		ath79_init_mac(wlan1_mac, lan_mac, 1);
157	} else {
158		pr_err("could not find ethaddr in u-boot environment\n");
159	}
160
161	ath79_register_m25p80(NULL);
162
163	ath79_register_leds_gpio(-1, ARRAY_SIZE(esr900_leds_gpio),
164					esr900_leds_gpio);
165	ath79_register_gpio_keys_polled(-1, ESR900_KEYS_POLL_INTERVAL,
166					ARRAY_SIZE(esr900_gpio_keys),
167					esr900_gpio_keys);
168
169	ath79_register_usb();
170
171	ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac);
172
173	ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
174
175	ath79_register_mdio(0, 0x0);
176
177	mdiobus_register_board_info(esr900_mdio0_info,
178				    ARRAY_SIZE(esr900_mdio0_info));
179
180	/* GMAC0 is connected to the RMGII interface */
181	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
182	ath79_eth0_data.phy_mask = ESR900_LAN_PHYMASK;
183	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
184
185	ath79_eth0_pll_data.pll_1000 = 0xa6000000;
186	ath79_register_eth(0);
187
188	/* GMAC1 is connected to the SGMII interface */
189	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
190	ath79_eth1_data.speed = SPEED_1000;
191	ath79_eth1_data.duplex = DUPLEX_FULL;
192
193	ath79_eth1_pll_data.pll_1000 = 0x03000101;
194	ath79_register_eth(1);
195
196	ap91_pci_init(art + ESR900_PCIE_CALDATA_OFFSET, wlan1_mac);
197}
198
199MIPS_MACHINE(ATH79_MACH_ESR900, "ESR900", "EnGenius ESR900", esr900_setup);
200
201