1/* 2 * ADM5120 NAND interface definitions 3 * 4 * This header file defines the hardware registers of the ADM5120 SoC 5 * built-in NAND interface. 6 * 7 * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org> 8 * 9 * NAND interface routines was based on a driver for Linux 2.6.19+ which 10 * was derived from the driver for Linux 2.4.xx published by Mikrotik for 11 * their RouterBoard 1xx and 5xx series boards. 12 * Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk> 13 * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License version 2 as published 17 * by the Free Software Foundation. 18 * 19 */ 20 21#ifndef _MACH_ADM5120_NAND_H 22#define _MACH_ADM5120_NAND_H 23 24#include <linux/types.h> 25#include <linux/io.h> 26 27#include <asm/mach-adm5120/adm5120_defs.h> 28#include <asm/mach-adm5120/adm5120_switch.h> 29 30/* NAND control registers */ 31#define NAND_REG_DATA 0x0 /* data register */ 32#define NAND_REG_SET_CEn 0x1 /* CE# low */ 33#define NAND_REG_CLR_CEn 0x2 /* CE# high */ 34#define NAND_REG_CLR_CLE 0x3 /* CLE low */ 35#define NAND_REG_SET_CLE 0x4 /* CLE high */ 36#define NAND_REG_CLR_ALE 0x5 /* ALE low */ 37#define NAND_REG_SET_ALE 0x6 /* ALE high */ 38#define NAND_REG_SET_SPn 0x7 /* SP# low (use spare area) */ 39#define NAND_REG_CLR_SPn 0x8 /* SP# high (do not use spare area) */ 40#define NAND_REG_SET_WPn 0x9 /* WP# low */ 41#define NAND_REG_CLR_WPn 0xA /* WP# high */ 42#define NAND_REG_STATUS 0xB /* Status register */ 43 44#define ADM5120_NAND_STATUS_READY 0x80 45 46#define NAND_READ_REG(r) \ 47 readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r)) 48#define NAND_WRITE_REG(r, v) \ 49 writeb((v), (void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r)) 50 51/*-------------------------------------------------------------------------*/ 52 53static inline void adm5120_nand_enable(void) 54{ 55 SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE); 56 SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1); 57} 58 59static inline void adm5120_nand_set_wpn(unsigned int set) 60{ 61 NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1); 62} 63 64static inline void adm5120_nand_set_spn(unsigned int set) 65{ 66 NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1); 67} 68 69static inline void adm5120_nand_set_cle(unsigned int set) 70{ 71 NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1); 72} 73 74static inline void adm5120_nand_set_ale(unsigned int set) 75{ 76 NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1); 77} 78 79static inline void adm5120_nand_set_cen(unsigned int set) 80{ 81 NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1); 82} 83 84static inline u8 adm5120_nand_get_status(void) 85{ 86 return NAND_READ_REG(NAND_REG_STATUS); 87} 88 89#endif /* _MACH_ADM5120_NAND_H */ 90