1/****************************************************************************** 2** 3** FILE NAME : ifxmips_ptm_ppe_common.h 4** PROJECT : UEIP 5** MODULES : PTM 6** 7** DATE : 7 Jul 2009 8** AUTHOR : Xu Liang 9** DESCRIPTION : PTM driver header file (PPE register for all platform) 10** COPYRIGHT : Copyright (c) 2006 11** Infineon Technologies AG 12** Am Campeon 1-12, 85579 Neubiberg, Germany 13** 14** This program is free software; you can redistribute it and/or modify 15** it under the terms of the GNU General Public License as published by 16** the Free Software Foundation; either version 2 of the License, or 17** (at your option) any later version. 18** 19** HISTORY 20** $Date $Author $Comment 21** 07 JUL 2009 Xu Liang Init Version 22*******************************************************************************/ 23 24 25 26#ifndef IFXMIPS_PTM_PPE_COMMON_H 27#define IFXMIPS_PTM_PPE_COMMON_H 28 29 30 31#if defined(CONFIG_DANUBE) 32 #include "ifxmips_ptm_ppe_danube.h" 33#elif defined(CONFIG_AMAZON_SE) 34 #include "ifxmips_ptm_ppe_amazon_se.h" 35#elif defined(CONFIG_AR9) 36 #include "ifxmips_ptm_ppe_ar9.h" 37#elif defined(CONFIG_VR9) 38 #include "ifxmips_ptm_ppe_vr9.h" 39#else 40 #error Platform is not specified! 41#endif 42 43 44 45/* 46 * Code/Data Memory (CDM) Interface Configuration Register 47 */ 48#define CDM_CFG PPE_REG_ADDR(0x0100) 49 50#define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2) 51#define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1)) 52 53#define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value) 54#define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0) 55 56/* 57 * QSB Internal Cell Delay Variation Register 58 */ 59#define QSB_ICDV QSB_CONF_REG_ADDR(0x0007) 60 61#define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0) 62 63#define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value) 64 65/* 66 * QSB Scheduler Burst Limit Register 67 */ 68#define QSB_SBL QSB_CONF_REG_ADDR(0x0009) 69 70#define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0) 71 72#define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value) 73 74/* 75 * QSB Configuration Register 76 */ 77#define QSB_CFG QSB_CONF_REG_ADDR(0x000A) 78 79#define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0) 80 81#define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value) 82 83/* 84 * QSB RAM Transfer Table Register 85 */ 86#define QSB_RTM QSB_CONF_REG_ADDR(0x000B) 87 88#define QSB_RTM_DM (*QSB_RTM) 89 90#define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF) 91 92/* 93 * QSB RAM Transfer Data Register 94 */ 95#define QSB_RTD QSB_CONF_REG_ADDR(0x000C) 96 97#define QSB_RTD_TTV (*QSB_RTD) 98 99#define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF) 100 101/* 102 * QSB RAM Access Register 103 */ 104#define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D) 105 106#define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31)) 107#define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24) 108#define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16)) 109#define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0) 110 111#define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0) 112#define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value) 113#define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0) 114#define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value) 115 116/* 117 * QSB Queue Scheduling and Shaping Definitions 118 */ 119#define QSB_WFQ_NONUBR_MAX 0x3f00 120#define QSB_WFQ_UBR_BYPASS 0x3fff 121#define QSB_TP_TS_MAX 65472 122#define QSB_TAUS_MAX 64512 123#define QSB_GCR_MIN 18 124 125/* 126 * QSB Constant 127 */ 128#define QSB_RAMAC_RW_READ 0 129#define QSB_RAMAC_RW_WRITE 1 130 131#define QSB_RAMAC_TSEL_QPT 0x01 132#define QSB_RAMAC_TSEL_SCT 0x02 133#define QSB_RAMAC_TSEL_SPT 0x03 134#define QSB_RAMAC_TSEL_VBR 0x08 135 136#define QSB_RAMAC_LH_LOW 0 137#define QSB_RAMAC_LH_HIGH 1 138 139#define QSB_QPT_SET_MASK 0x0 140#define QSB_QVPT_SET_MASK 0x0 141#define QSB_SET_SCT_MASK 0x0 142#define QSB_SET_SPT_MASK 0x0 143#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF 144 145#define QSB_SPT_SBV_VALID (1 << 31) 146#define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0) 147#define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value) 148 149/* 150 * QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry 151 */ 152#if defined(__BIG_ENDIAN) 153 union qsb_queue_parameter_table { 154 struct { 155 unsigned int res1 :1; 156 unsigned int vbr :1; 157 unsigned int wfqf :14; 158 unsigned int tp :16; 159 } bit; 160 u32 dword; 161 }; 162 163 union qsb_queue_vbr_parameter_table { 164 struct { 165 unsigned int taus :16; 166 unsigned int ts :16; 167 } bit; 168 u32 dword; 169 }; 170#else 171 union qsb_queue_parameter_table { 172 struct { 173 unsigned int tp :16; 174 unsigned int wfqf :14; 175 unsigned int vbr :1; 176 unsigned int res1 :1; 177 } bit; 178 u32 dword; 179 }; 180 181 union qsb_queue_vbr_parameter_table { 182 struct { 183 unsigned int ts :16; 184 unsigned int taus :16; 185 } bit; 186 u32 dword; 187 }; 188#endif // defined(__BIG_ENDIAN) 189 190/* 191 * Mailbox IGU0 Registers 192 */ 193#define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200) 194#define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201) 195#define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202) 196#define MBOX_IGU0_IER PPE_REG_ADDR(0x0203) 197 198#define MBOX_IGU0_ISRS_SET(n) (1 << (n)) 199#define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n)) 200#define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n))) 201#define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n))) 202#define MBOX_IGU0_IER_EN_SET(n) (1 << (n)) 203 204/* 205 * Mailbox IGU1 Registers 206 */ 207#define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204) 208#define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205) 209#define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206) 210#define MBOX_IGU1_IER PPE_REG_ADDR(0x0207) 211 212#define MBOX_IGU1_ISRS_SET(n) (1 << (n)) 213#define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n)) 214#define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n))) 215#define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n))) 216#define MBOX_IGU1_IER_EN_SET(n) (1 << (n)) 217 218/* 219 * Mailbox IGU3 Registers 220 */ 221#define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214) 222#define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215) 223#define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216) 224#define MBOX_IGU3_IER PPE_REG_ADDR(0x0217) 225 226#define MBOX_IGU3_ISRS_SET(n) (1 << (n)) 227#define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n)) 228#define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n))) 229#define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n))) 230#define MBOX_IGU3_IER_EN_SET(n) (1 << (n)) 231 232/* 233 * RTHA/TTHA Registers 234 */ 235#define RFBI_CFG PPE_REG_ADDR(0x0400) 236#define RBA_CFG0 PPE_REG_ADDR(0x0404) 237#define RBA_CFG1 PPE_REG_ADDR(0x0405) 238#define RCA_CFG0 PPE_REG_ADDR(0x0408) 239#define RCA_CFG1 PPE_REG_ADDR(0x0409) 240#define RDES_CFG0 PPE_REG_ADDR(0x040C) 241#define RDES_CFG1 PPE_REG_ADDR(0x040D) 242#define SFSM_STATE0 PPE_REG_ADDR(0x0410) 243#define SFSM_STATE1 PPE_REG_ADDR(0x0411) 244#define SFSM_DBA0 PPE_REG_ADDR(0x0412) 245#define SFSM_DBA1 PPE_REG_ADDR(0x0413) 246#define SFSM_CBA0 PPE_REG_ADDR(0x0414) 247#define SFSM_CBA1 PPE_REG_ADDR(0x0415) 248#define SFSM_CFG0 PPE_REG_ADDR(0x0416) 249#define SFSM_CFG1 PPE_REG_ADDR(0x0417) 250#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C) 251#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D) 252#define FFSM_DBA0 PPE_REG_ADDR(0x0508) 253#define FFSM_DBA1 PPE_REG_ADDR(0x0509) 254#define FFSM_CFG0 PPE_REG_ADDR(0x050A) 255#define FFSM_CFG1 PPE_REG_ADDR(0x050B) 256#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E) 257#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F) 258#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514) 259#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515) 260 261/* 262 * PPE TC Logic Registers (partial) 263 */ 264#define DREG_A_VERSION PPE_REG_ADDR(0x0D00) 265#define DREG_A_CFG PPE_REG_ADDR(0x0D01) 266#define DREG_AT_CTRL PPE_REG_ADDR(0x0D02) 267#define DREG_AT_CB_CFG0 PPE_REG_ADDR(0x0D03) 268#define DREG_AT_CB_CFG1 PPE_REG_ADDR(0x0D04) 269#define DREG_AR_CTRL PPE_REG_ADDR(0x0D08) 270#define DREG_AR_CB_CFG0 PPE_REG_ADDR(0x0D09) 271#define DREG_AR_CB_CFG1 PPE_REG_ADDR(0x0D0A) 272#define DREG_A_UTPCFG PPE_REG_ADDR(0x0D0E) 273#define DREG_A_STATUS PPE_REG_ADDR(0x0D0F) 274#define DREG_AT_CFG0 PPE_REG_ADDR(0x0D20) 275#define DREG_AT_CFG1 PPE_REG_ADDR(0x0D21) 276#define DREG_AT_FB_SIZE0 PPE_REG_ADDR(0x0D22) 277#define DREG_AT_FB_SIZE1 PPE_REG_ADDR(0x0D23) 278#define DREG_AT_CELL0 PPE_REG_ADDR(0x0D24) 279#define DREG_AT_CELL1 PPE_REG_ADDR(0x0D25) 280#define DREG_AT_IDLE_CNT0 PPE_REG_ADDR(0x0D26) 281#define DREG_AT_IDLE_CNT1 PPE_REG_ADDR(0x0D27) 282#define DREG_AT_IDLE0 PPE_REG_ADDR(0x0D28) 283#define DREG_AT_IDLE1 PPE_REG_ADDR(0x0D29) 284#define DREG_AR_CFG0 PPE_REG_ADDR(0x0D60) 285#define DREG_AR_CFG1 PPE_REG_ADDR(0x0D61) 286#define DREG_AR_CELL0 PPE_REG_ADDR(0x0D68) 287#define DREG_AR_CELL1 PPE_REG_ADDR(0x0D69) 288#define DREG_AR_IDLE_CNT0 PPE_REG_ADDR(0x0D6A) 289#define DREG_AR_IDLE_CNT1 PPE_REG_ADDR(0x0D6B) 290#define DREG_AR_AIIDLE_CNT0 PPE_REG_ADDR(0x0D6C) 291#define DREG_AR_AIIDLE_CNT1 PPE_REG_ADDR(0x0D6D) 292#define DREG_AR_BE_CNT0 PPE_REG_ADDR(0x0D6E) 293#define DREG_AR_BE_CNT1 PPE_REG_ADDR(0x0D6F) 294#define DREG_AR_HEC_CNT0 PPE_REG_ADDR(0x0D70) 295#define DREG_AR_HEC_CNT1 PPE_REG_ADDR(0x0D71) 296#define DREG_AR_IDLE0 PPE_REG_ADDR(0x0D74) 297#define DREG_AR_IDLE1 PPE_REG_ADDR(0x0D75) 298#define DREG_AR_CERRN_CNT0 PPE_REG_ADDR(0x0DA0) 299#define DREG_AR_CERRN_CNT1 PPE_REG_ADDR(0x0DA1) 300#define DREG_AR_CERRNP_CNT0 PPE_REG_ADDR(0x0DA2) 301#define DREG_AR_CERRNP_CNT1 PPE_REG_ADDR(0x0DA3) 302#define DREG_AR_CVN_CNT0 PPE_REG_ADDR(0x0DA4) 303#define DREG_AR_CVN_CNT1 PPE_REG_ADDR(0x0DA5) 304#define DREG_AR_CVNP_CNT0 PPE_REG_ADDR(0x0DA6) 305#define DREG_AR_CVNP_CNT1 PPE_REG_ADDR(0x0DA7) 306#define DREG_B0_LADR PPE_REG_ADDR(0x0DA8) 307#define DREG_B1_LADR PPE_REG_ADDR(0x0DA9) 308 309 310 311#endif // IFXMIPS_PTM_PPE_COMMON_H 312