1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, Version 1.0 only
6 * (the "License").  You may not use this file except in compliance
7 * with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22
23/*
24 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#pragma ident	"%Z%%M%	%I%	%E% SMI"
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/sysmacros.h>
33#include <sys/sunddi.h>
34#include <sys/esunddi.h>
35#include <sys/sunndi.h>
36
37#include <sys/platform_module.h>
38#include <sys/errno.h>
39#include <sys/utsname.h>
40#include <sys/modctl.h>
41#include <sys/systeminfo.h>
42#include <sys/promif.h>
43#include <sys/bootconf.h>
44
45/*
46 * Definitions for accessing the pci config space of the isa node
47 * of Southbridge.
48 */
49#define	ONTARIO_ISA_PATHNAME	"/pci@7c0/pci@0/pci@1/pci@0/isa@2"
50#define	ONTARIO_IDE_PATHNAME	"/pci@7c0/pci@0/pci@1/pci@0/ide@8"
51
52/*
53 * Handle for isa pci space
54 */
55static ddi_acc_handle_t isa_handle;
56
57/*
58 * Platform power management drivers list - empty by default
59 */
60char *platform_module_list[] = {
61	(char *)0
62};
63
64
65/*ARGSUSED*/
66void
67plat_tod_fault(enum tod_fault_type tod_bad)
68{
69}
70
71void
72load_platform_drivers(void)
73{
74	dev_info_t 		*dip;		/* dip of the isa driver */
75	pnode_t 		nodeid;
76
77	/*
78	 * Install ISA driver. This is required for the southbridge IDE
79	 * workaround - to reset the IDE channel during IDE bus reset.
80	 * Panic the system in case ISA driver could not be loaded or
81	 * any problem in accessing its pci config space. Since the register
82	 * to reset the channel for IDE is in ISA config space!.
83	 */
84
85	nodeid = prom_finddevice(ONTARIO_IDE_PATHNAME);
86	if (nodeid == OBP_BADNODE) {
87		return;
88	}
89	dip = e_ddi_hold_devi_by_path(ONTARIO_ISA_PATHNAME, 0);
90	if (dip == NULL) {
91		cmn_err(CE_PANIC, "Could not install the isa driver\n");
92		return;
93	}
94
95	if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) {
96		cmn_err(CE_PANIC, "Could not get the config space of isa\n");
97		return;
98	}
99}
100
101/*
102 * This routine provides a workaround for a bug in the SB chip which
103 * can cause data corruption. Will be invoked from the IDE HBA driver for
104 * Acer SouthBridge at the time of IDE bus reset.
105 */
106/*ARGSUSED*/
107int
108plat_ide_chipreset(dev_info_t *dip, int chno)
109{
110	uint8_t	val;
111	int	ret = DDI_SUCCESS;
112
113	if (isa_handle == NULL) {
114		return (DDI_FAILURE);
115	}
116
117	val = pci_config_get8(isa_handle, 0x58);
118	/*
119	 * The dip passed as the argument is not used here.
120	 * This will be needed for platforms which have multiple on-board SB,
121	 * The dip passed will be used to match the corresponding ISA node.
122	 */
123	switch (chno) {
124	case 0:
125		/*
126		 * First disable the primary channel then re-enable it.
127		 * As per ALI no wait should be required in between have
128		 * given 1ms delay in between to be on safer side.
129		 * bit 2 of register 0x58 when 0 disable the channel 0.
130		 * bit 2 of register 0x58 when 1 enables the channel 0.
131		 */
132		pci_config_put8(isa_handle, 0x58, val & 0xFB);
133		drv_usecwait(1000);
134		pci_config_put8(isa_handle, 0x58, val);
135		break;
136	case 1:
137		/*
138		 * bit 3 of register 0x58 when 0 disable the channel 1.
139		 * bit 3 of register 0x58 when 1 enables the channel 1.
140		 */
141		pci_config_put8(isa_handle, 0x58, val & 0xF7);
142		drv_usecwait(1000);
143		pci_config_put8(isa_handle, 0x58, val);
144		break;
145	default:
146		/*
147		 * Unknown channel number passed. Return failure.
148		 */
149		ret = DDI_FAILURE;
150	}
151
152	return (ret);
153}
154