1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_PX_ERR_H 27#define _SYS_PX_ERR_H 28 29#ifdef __cplusplus 30extern "C" { 31#endif 32 33/* error packet definitions */ 34 35/* Block Definitions */ 36#define BLOCK_RSVD 0x0 37#define BLOCK_HOSTBUS 0x1 38#define BLOCK_MMU 0x2 39#define BLOCK_INTR 0x3 40#define BLOCK_PCIE 0x4 41#define BLOCK_PORT 0x5 42#define BLOCK_UNKNOWN 0xe 43 44/* Op definitions for HOSTBUS */ 45#define OP_RESERVED 0x0 46#define OP_PIO 0x1 47#define OP_DMA 0x2 48#define OP_UNKNOWN 0xe 49 50/* Op definitions for MMU */ 51#define OP_RESERVED 0x0 52#define OP_XLAT 0x1 53#define OP_BYPASS 0x2 54#define OP_TBW 0x3 55#define OP_UNKNOWN 0xe 56 57/* Op definitions for INTR */ 58#define OP_RESERVED 0x0 59#define OP_MSI32 0x1 60#define OP_MSI64 0x2 61#define OP_MSIQ 0x3 62#define OP_PCIEMSG 0x4 63#define OP_FIXED 0x5 64#define OP_UNKNOWN 0xe 65 66/* Op definitions for PORT */ 67#define OP_RESERVED 0x0 68#define OP_PIO 0x1 69#define OP_DMA 0x2 70#define OP_LINK 0x3 71#define OP_UNKNOWN 0xe 72 73/* Phase definitons */ 74#define PH_RESERVED 0x0 75#define PH_ADDR 0x1 76#define PH_DATA 0x2 77#define PH_UNKNOWN 0xe 78#define PH_IRR 0xf 79 80/* Phase definitions for PORT/Link */ 81#define PH_FC 0x1 82 83 84/* Condition definitions for any major Block/Op/Phase */ 85#define CND_RESERVED 0x0 86#define CND_ILL 0x1 87#define CND_UNMAP 0x2 88#define CND_INT 0x3 89#define CND_UE 0x4 90#define CND_INV 0x6 91#define CND_UNKNOWN 0xe 92#define CND_IRR 0xf 93 94/* Additional condition definitions for INTR Block MSIQ phase */ 95#define CND_OV 0x5 96 97/* Additional condition definitions for MMU|INTR Block ADDR phase */ 98#define CND_PROT 0x5 99 100/* Additional condition definitions for DATA phase */ 101#define CND_TO 0x5 102 103/* Additional condition definitions for Port Link phase */ 104#define CND_RCA 0x7 105#define CND_RUR 0x8 106#define CND_UC 0x9 107 108/* Dir definitions for HOSTBUS & MMU */ 109#define DIR_RESERVED 0x0 110#define DIR_READ 0x1 111#define DIR_WRITE 0x2 112#define DIR_RDWR 0x3 113#define DIR_INGRESS 0x4 114#define DIR_EGRESS 0x5 115#define DIR_LINK 0x6 116#define DIR_UNKNOWN 0xe 117#define DIR_IRR 0xf 118 119#define PX_FM_RC_UNRECOG "fire.epkt" 120#define EPKT_SYSINO "sysino" 121#define EPKT_EHDL "ehdl" 122#define EPKT_STICK "stick" 123#define EPKT_DW0 "dw0" 124#define EPKT_DW1 "dw1" 125#define EPKT_DW2 "dw2" 126#define EPKT_DW3 "dw3" 127#define EPKT_DW4 "dw4" 128#define EPKT_RC_DESCR "rc_descr" 129#define EPKT_PEC_DESCR "pec_descr" 130 131#ifndef _ESC 132typedef struct root_complex { 133 uint64_t sysino; 134 uint64_t ehdl; 135 uint64_t stick; 136 struct { 137#if defined(_BIT_FIELDS_LTOH) 138 uint32_t S : 1, /* Also the "Q" flag */ 139 M : 1, 140 D : 1, 141 R : 1, 142 H : 1, 143 C : 1, 144 I : 1, 145 B : 1, 146 : 3, 147 STOP : 1, 148 dir : 4, 149 cond : 4, 150 phase : 4, 151 op : 4, 152 block : 4; 153#elif defined(_BIT_FIELDS_HTOL) 154 uint32_t block : 4, 155 op : 4, 156 phase : 4, 157 cond : 4, 158 dir : 4, 159 STOP : 1, 160 : 3, 161 B : 1, 162 I : 1, 163 C : 1, 164 H : 1, 165 R : 1, 166 D : 1, 167 M : 1, 168 S : 1; /* Also the "Q" flag */ 169#else 170#error "bit field not defined" 171#endif 172 } rc_descr; 173 uint32_t size; /* Also the EQ Num */ 174 uint64_t addr; 175 uint64_t hdr[2]; 176 uint64_t reserved; /* Contains Port */ 177} px_rc_err_t; 178 179typedef struct pec_block_err { 180 uint64_t sysino; 181 uint64_t ehdl; 182 uint64_t stick; 183 struct { 184 uint32_t block : 4, 185 rsvd1 : 12, 186 dir : 4, 187 : 3, 188 Z : 1, 189 S : 1, 190 R : 1, 191 I : 1, 192 H : 1, 193 C : 1, 194 U : 1, 195 E : 1, 196 P : 1; 197 } pec_descr; 198 uint16_t pci_err_status; 199 uint16_t pcie_err_status; 200 uint32_t ce_reg_status; 201 uint32_t ue_reg_status; 202 uint64_t hdr[2]; 203 uint32_t err_src_reg; 204 uint32_t root_err_status; 205} px_pec_err_t; 206#endif /* _ESC */ 207 208#ifdef __cplusplus 209} 210#endif 211 212#endif /* _SYS_PX_ERR_H */ 213