1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _SYS_SPITREGS_H 28#define _SYS_SPITREGS_H 29 30#pragma ident "%Z%%M% %I% %E% SMI" 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36/* 37 * This file is cpu dependent. 38 */ 39 40#ifdef _STARFIRE 41/* 42 * Starfire's cpu upaids are not the same 43 * as cpuids. 44 * XXX - our obp took the liberty of 45 * converting cpu upaids into cpuids when 46 * presenting it as upa-portid property. 47 */ 48#define CPUID_TO_UPAID(upaid) (((upaid & 0x3C) << 1) | \ 49 ((upaid & 0x40) >> 4) | \ 50 (upaid &0x3)) 51#else 52/* 53 * The mid is the same as the cpu id. 54 * We might want to change this later 55 */ 56#define CPUID_TO_UPAID(cpuid) (cpuid) 57#endif /* _STARFIRE */ 58 59/* 60 * LSU Control Register 61 * 62 * +------+----+----+----+----+----+----+-----+------+----+----+----+---+ 63 * | Resv | PM | VM | PR | PW | VR | VW | Rsv | FM | DM | IM | DC | IC| 64 * +------+----+----+----+----+----+----+-----+------+----+----+----+---+ 65 * 63 41 33 25 24 23 22 21 20 19 4 3 2 1 0 66 * 67 */ 68 69#define LSU_IC 0x00000000001 /* icache enable */ 70#define LSU_DC 0x00000000002 /* dcache enable */ 71#define LSU_IM 0x00000000004 /* immu enable */ 72#define LSU_DM 0x00000000008 /* dmmu enable */ 73#define LSU_FM 0x000000FFFF0 /* parity mask */ 74#define LSU_VW 0x00000200000 /* virtual watchpoint write enable */ 75#define LSU_VR 0x00000400000 /* virtual watchpoint read enable */ 76#define LSU_PW 0x00000800000 /* physical watchpoint write enable */ 77#define LSU_PR 0x00001000000 /* physical watchpoint read enable */ 78#define LSU_VM 0x001fe000000 /* virtual watchpoint byte mask */ 79#define LSU_PM 0x1fe00000000 /* physical watch point byte mask */ 80 81#define LSU_VM_SHIFT 25 82#define LSU_PM_SHIFT 33 83 84/* 85 * Defines for the different types of dcache_flush 86 * it is stored in dflush_type 87 */ 88#define FLUSHALL_TYPE 0x0 /* blasts all cache lines */ 89#define FLUSHMATCH_TYPE 0x1 /* flush entire cache but check each */ 90 /* each line for a match */ 91#define FLUSHPAGE_TYPE 0x2 /* flush only one page and check */ 92 /* each line for a match */ 93 94/* 95 * D-Cache Tag Data Register 96 * 97 * +----------+--------+----------+ 98 * | Reserved | DC_Tag | DC_Valid | 99 * +----------+--------+----------+ 100 * 63 30 29 2 1 0 101 * 102 */ 103#define ICACHE_FLUSHSZ 0x20 /* one line in i$ */ 104#define DC_PTAG_SHIFT 34 105#define DC_LINE_SHIFT 30 106#define SF_DC_VBIT_SHIFT 2 107#define SF_DC_VBIT_MASK 0x3 108#define IC_LINE_SHIFT 3 109#define IC_LINE 512 110#define INDEX_BIT_SHIFT 13 111 112/* 113 * Definitions of sun4u cpu implementations as specified in version register 114 */ 115#define SPITFIRE_IMPL 0x10 116#define IS_SPITFIRE(impl) ((impl) == SPITFIRE_IMPL) 117#define SPITFIRE_MAJOR_VERSION(rev) (((rev) >> 4) & 0xf) 118#define SPITFIRE_MINOR_VERSION(rev) ((rev) & 0xf) 119 120#define BLACKBIRD_IMPL 0x11 121#define IS_BLACKBIRD(impl) ((impl) == BLACKBIRD_IMPL) 122#define BLACKBIRD_MAJOR_VERSION(rev) (((rev) >> 4) & 0xf) 123#define BLACKBIRD_MINOR_VERSION(rev) ((rev) & 0xf) 124 125#define SABRE_IMPL 0x12 126#define HUMMBRD_IMPL 0x13 127 128/* 129 * Bits of Spitfire Asynchronous Fault Status Register 130 */ 131#define P_AFSR_STICKY 0x00000001FFF00000ULL /* mask for all sticky bits */ 132#define P_AFSR_ERRS 0x000000001EE00000ULL /* mask for remaining errors */ 133#define P_AFSR_ME 0x0000000100000000ULL /* errors > 1, same type!=CE */ 134#define P_AFSR_PRIV 0x0000000080000000ULL /* priv/supervisor access */ 135#define P_AFSR_ISAP 0x0000000040000000ULL /* incoming system addr. parity */ 136#define P_AFSR_ETP 0x0000000020000000ULL /* ecache tag parity */ 137#define P_AFSR_IVUE 0x0000000010000000ULL /* interrupt vector with UE */ 138#define P_AFSR_TO 0x0000000008000000ULL /* bus timeout */ 139#define P_AFSR_BERR 0x0000000004000000ULL /* bus error */ 140#define P_AFSR_LDP 0x0000000002000000ULL /* data parity error from SDB */ 141#define P_AFSR_CP 0x0000000001000000ULL /* copyout parity error */ 142#define P_AFSR_WP 0x0000000000800000ULL /* writeback ecache data parity */ 143#define P_AFSR_EDP 0x0000000000400000ULL /* ecache data parity */ 144#define P_AFSR_UE 0x0000000000200000ULL /* uncorrectable ECC error */ 145#define P_AFSR_CE 0x0000000000100000ULL /* correctable ECC error */ 146#define P_AFSR_ETS 0x00000000000F0000ULL /* cache tag parity syndrome */ 147#define P_AFSR_P_SYND 0x000000000000FFFFULL /* data parity syndrome */ 148 149/* 150 * All error types 151 */ 152#define S_AFSR_ALL_ERRS (P_AFSR_STICKY & ~P_AFSR_PRIV) 153 154/* 155 * Shifts for Spitfire Asynchronous Fault Status Register 156 */ 157#define P_AFSR_D_SIZE_SHIFT (57) 158#define P_AFSR_CP_SHIFT (24) 159#define P_AFSR_ETS_SHIFT (16) 160 161/* 162 * AFSR error bits for AFT Level 1 messages (uncorrected + parity + BERR + TO) 163 */ 164#define P_AFSR_LEVEL1 (P_AFSR_UE | P_AFSR_EDP | P_AFSR_WP | P_AFSR_CP |\ 165 P_AFSR_LDP | P_AFSR_BERR | P_AFSR_TO) 166 167/* 168 * Bits of Spitfire Asynchronous Fault Status Register 169 */ 170#define S_AFSR_MASK 0x00000001FFFFFFFFULL /* <33:0>: valid AFSR bits */ 171 172/* 173 * Bits of Spitfire Asynchronous Fault Address Register 174 * The Sabre AFAR includes more bits since it only has a UDBH, no UDBL 175 */ 176#define S_AFAR_PA 0x000001FFFFFFFFF0ULL /* PA<40:4>: physical address */ 177#define SABRE_AFAR_PA 0x000001FFFFFFFFF8ULL /* PA<40:3>: physical address */ 178 179/* 180 * Bits of Spitfire/Sabre/Hummingbird Error Enable Registers 181 */ 182#define EER_EPEN 0x00000000000000010ULL /* enable ETP, EDP, WP, CP */ 183#define EER_UEEN 0x00000000000000008ULL /* enable UE */ 184#define EER_ISAPEN 0x00000000000000004ULL /* enable ISAP */ 185#define EER_NCEEN 0x00000000000000002ULL /* enable the other errors */ 186#define EER_CEEN 0x00000000000000001ULL /* enable CE */ 187#define EER_DISABLE 0x00000000000000000ULL /* no errors enabled */ 188#define EER_ECC_DISABLE (EER_EPEN|EER_UEEN|EER_ISAPEN) 189#define EER_CE_DISABLE (EER_EPEN|EER_UEEN|EER_ISAPEN|EER_NCEEN) 190#define EER_ENABLE (EER_EPEN|EER_UEEN|EER_ISAPEN|EER_NCEEN|EER_CEEN) 191 192/* 193 * Bits and vaddrs of Spitfire Datapath Error Registers 194 */ 195#define P_DER_UE 0x00000000000000200ULL /* UE has occurred */ 196#define P_DER_CE 0x00000000000000100ULL /* CE has occurred */ 197#define P_DER_E_SYND 0x000000000000000FFULL /* SYND<7:0>: ECC syndrome */ 198#define P_DER_H 0x0 /* datapath error reg upper */ 199#define P_DER_L 0x18 /* datapath error reg upper */ 200 201/* 202 * Bits of Spitfire Datapath Control Register 203 */ 204#define P_DCR_VER 0x000001E00 /* datapath version */ 205#define P_DCR_F_MODE 0x000000100 /* send FCB<7:0> */ 206#define P_DCR_FCB 0x0000000FF /* ECC check bits to force */ 207#define P_DCR_H 0x20 /* datapath control reg upper */ 208#define P_DCR_L 0x38 /* datapath control reg lower */ 209 210/* 211 * Bits and shifts for the Spitfire (S), Sabre (SB) and Hummingbird (HB) 212 * Ecache tag data 213 */ 214#define S_ECTAG_MASK 0x000000000003FFFFFULL /* spitfire ecache tag mask */ 215#define SB_ECTAG_MASK 0x00000000000000FFFULL /* sabre ecache tag mask */ 216#define HB_ECTAG_MASK 0x0000000000000FFFFULL /* hbird ecache tag mask */ 217#define S_ECSTATE_MASK 0x00000000001C00000ULL /* spitfire tag state mask */ 218#define SB_ECSTATE_MASK 0x0000000000000C000ULL /* sabre tag state mask */ 219#define HB_ECSTATE_MASK 0x00000000000030000ULL /* hbird tag state mask */ 220#define S_ECPAR_MASK 0x0000000001E000000ULL /* spitfire tag parity mask */ 221#define SB_ECPAR_MASK 0x00000000000030000ULL /* sabre tag parity mask */ 222#define HB_ECPAR_MASK 0x00000000000300000ULL /* hbird tag parity mask */ 223#define S_ECTAG_SHIFT 19 /* spitfire ecache tag shift */ 224#define SB_ECTAG_SHIFT 18 /* sabre ecache tag shift */ 225#define HB_ECTAG_SHIFT 16 /* hbird ecache tag shift */ 226#define S_ECSTATE_SHIFT 22 /* spitfire tag state shift */ 227#define SB_ECSTATE_SHIFT 14 /* sabre tag state shift */ 228#define HB_ECSTATE_SHIFT 16 /* hbird tag state shift */ 229#define S_ECPAR_SHIFT 25 /* spitfire tag parity shift */ 230#define SB_ECPAR_SHIFT 16 /* sabre tag parity shift */ 231#define HB_ECPAR_SHIFT 20 /* hbird tag parity shift */ 232#define S_ECACHE_MAX_LSIZE 64 /* E$ line size */ 233 234/* 235 * Constants representing the complete Spitfire (S), Sabre (SB) and Hummingbird 236 * (HB) tag state: 237 */ 238#define S_ECSTATE_SHR 0x1 /* shared */ 239#define S_ECSTATE_EXL 0x3 /* exclusive */ 240#define S_ECSTATE_OWN 0x5 /* owner */ 241#define S_ECSTATE_MOD 0x7 /* modified */ 242#define SB_ECSTATE_EXL 0x2 /* exclusive */ 243#define SB_ECSTATE_MOD 0x3 /* modified */ 244#define HB_ECSTATE_EXL 0x2 /* exclusive */ 245#define HB_ECSTATE_MOD 0x3 /* modified */ 246 247/* 248 * Constants representing the individual Spitfire (S), Sabre (SB) and 249 * Hummingbird (HB) state bits: 250 */ 251#define S_ECSTATE_VALID 0x1 /* line is valid */ 252#define S_ECSTATE_DIRTY 0x4 /* line is dirty */ 253#define SB_ECSTATE_VALID 0x2 /* line is valid */ 254#define SB_ECSTATE_DIRTY 0x1 /* line is dirty */ 255#define HB_ECSTATE_VALID 0x2 /* line is valid */ 256#define HB_ECSTATE_DIRTY 0x1 /* line is dirty */ 257 258/* 259 * Constants representing the individual Spitfire (S), Sabre (SB) and 260 * Hummingbird (HB) state parity and address parity bits: 261 */ 262#define S_ECSTATE_PARITY 0x8 /* tag state parity bit */ 263#define S_EC_PARITY 0xF /* all parity bits */ 264#define SB_ECSTATE_PARITY 0x2 /* tag state parity bit */ 265#define SB_EC_PARITY 0x3 /* all parity bits */ 266#define HB_ECSTATE_PARITY 0x2 /* tag state parity bit */ 267#define HB_EC_PARITY 0x3 /* all parity bits */ 268 269#ifdef HUMMINGBIRD 270 271#define HB_ESTAR_MODE INT64_C(0x1FE0000F080) /* estar mode reg */ 272#define HB_MEM_CNTRL0 INT64_C(0x1FE0000F010) /* mem control0 reg */ 273#define HB_REFRESH_COUNT_MASK 0x7F00 /* mc0<14:8>: ref cnt */ 274#define HB_REFRESH_COUNT_SHIFT 8 /* bits to shift */ 275#define HB_REFRESH_INTERVAL INT64_C(7800) /* 7800 nsecs memory */ 276 /* refresh interval */ 277 /* works for all DIMM */ 278 /* same value as OBP */ 279#define HB_REFRESH_CLOCKS_PER_COUNT INT64_C(64) /* cpu clks per count */ 280#define HB_SELF_REFRESH_MASK 0x10000 /* mc0<16>: self ref */ 281#define HB_SELF_REFRESH_SHIFT 16 /* bits to shift */ 282#define HB_SELF_REFRESH_DISABLE 0 /* disable self ref */ 283#define HB_SELF_REFRESH_ENABLE 1 /* enable self ref */ 284 285#define HB_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */ 286#define HB_ECLK_2 INT64_C(0x0000000000000001) /* 1/2 clock */ 287#define HB_ECLK_4 INT64_C(0x0000000000000003) /* 1/4 clock */ 288#define HB_ECLK_6 INT64_C(0x0000000000000002) /* 1/6 clock */ 289#define HB_ECLK_8 INT64_C(0x0000000000000004) /* 1/8 clock */ 290#define HB_ECLK_MASK (HB_ECLK_1|HB_ECLK_2|HB_ECLK_4|HB_ECLK_6|HB_ECLK_8) 291 292 293/* 294 * UPA Configuration Register 295 * 296 * +--------------+----+------+------+----------+------+-------------+ 297 * | Resv | RR | DM | ELIM | PCON | MID | PCAP | 298 * +--------------+----+------+------+----------+------+-------------+ 299 * 63 39 38 37..36 35..33 32......22 21..17 16..........0 300 * 301 */ 302 303#define HB_UPA_DMAP_DATA_BIT 36 /* loads and stores direct mapped */ 304#define HB_UPA_DMAP_INSTR_BIT 37 /* instruction misses direct mapped */ 305#define HB_UPA_RR_BIT 38 /* reset rand generator */ 306 307#endif /* HUMMINGBIRD */ 308 309/* 310 * The minimum size needed to ensure consistency on a virtually address 311 * cache. Computed by taking the largest virtually indexed cache and dividing 312 * by its associativity. 313 */ 314#define S_VAC_SIZE 0x4000 315 316#ifdef _KERNEL 317 318#ifndef _ASM 319#include <sys/kstat.h> 320 321void get_udb_errors(uint64_t *udbh, uint64_t *udbl); 322 323/* 324 * The scrub_misc structure contains miscellaneous bookeepping items for 325 * scrubbing the E$. 326 * 327 * Counter of outstanding E$ scrub requests. The counter for a given CPU id 328 * is atomically incremented and decremented _only_ on that CPU, 329 * to avoid cacheline ownership bouncing. 330 */ 331 332typedef struct spitfire_scrub_misc { 333 uint32_t ec_scrub_outstanding; /* outstanding reqs */ 334 int ecache_flush_index; /* offset into E$ for flush */ 335 int ecache_busy; /* keeps track if cpu busy */ 336 int ecache_nlines; /* no. of E$ lines */ 337 int ecache_mirror; /* E$ is mirrored */ 338 kstat_t *ecache_ksp; /* ptr to the kstat */ 339} spitfire_scrub_misc_t; 340 341/* 342 * Spitfire module private data structure. One of these is allocated for each 343 * valid cpu at setup time and is pointed to by the machcpu "cpu_private" 344 * pointer. 345 */ 346typedef struct spitfire_private { 347 spitfire_scrub_misc_t sfpr_scrub_misc; 348 uint64_t sfpr_scrub_afsr; 349} spitfire_private_t; 350 351#endif /* !_ASM */ 352 353#endif /* _KERNEL */ 354 355#ifdef __cplusplus 356} 357#endif 358 359#endif /* _SYS_SPITREGS_H */ 360