1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_PCI_IOMMU_H 27#define _SYS_PCI_IOMMU_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#include <sys/vmem.h> 36 37typedef uint64_t dvma_addr_t; 38typedef uint64_t dma_bypass_addr_t; 39typedef uint64_t dma_peer_addr_t; 40typedef uint16_t dvma_context_t; 41typedef uint64_t window_t; 42 43/* 44 * The following typedef's represents the types for DMA transactions 45 * and corresponding DMA addresses supported by psycho/schizo. 46 */ 47typedef enum { IOMMU_XLATE, IOMMU_BYPASS, PCI_PEER_TO_PEER } iommu_dma_t; 48 49/* 50 * The following macros define the iommu page size and related operations. 51 */ 52#define IOMMU_PAGE_SHIFT 13 53#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) 54#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) 55#define IOMMU_PAGE_OFFSET (IOMMU_PAGE_SIZE - 1) 56#define IOMMU_PTOB(x) (((uint64_t)(x)) << IOMMU_PAGE_SHIFT) 57#define IOMMU_BTOP(x) ((x) >> IOMMU_PAGE_SHIFT) 58#define IOMMU_BTOPR(x) IOMMU_BTOP((x) + IOMMU_PAGE_OFFSET) 59 60/* 61 * control register decoding 62 */ 63/* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 64#define IOMMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 65#define IOMMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 66#define IOMMU_DARWIN_BOGUS_TSBSIZE 7 67 68/* 69 * boiler plate for tte (everything except the pfn) 70 */ 71#define MAKE_TTE_TEMPLATE(pfn, mp) (COMMON_IOMMU_TTE_V | \ 72 (pf_is_memory(pfn) ? COMMON_IOMMU_TTE_C : 0) | \ 73 ((mp->dmai_rflags & DDI_DMA_READ) ? COMMON_IOMMU_TTE_W : 0) | \ 74 ((mp->dmai_rflags & DDI_DMA_CONSISTENT) ? 0 : COMMON_IOMMU_TTE_S)) 75#define TTE_IS_INVALID(tte) (((tte) & COMMON_IOMMU_TTE_V) == 0x0ull) 76 77/* 78 * The following macros define the address ranges supported for DVMA 79 * and iommu bypass transfers. 80 */ 81#define COMMON_IOMMU_BYPASS_BASE 0xFFFC000000000000ull 82 83/* 84 * The IOMMU_BYPASS_END is ASIC dependent and so defined in the appropriate 85 * header file. 86 */ 87 88/* 89 * For iommu bypass addresses, bit 43 specifies cacheability. 90 */ 91#define COMMON_IOMMU_BYPASS_NONCACHE 0x0000080000000000ull 92 93/* 94 * Generic iommu definitions and types: 95 */ 96#define IOMMU_TLB_ENTRIES 16 97 98/* 99 * The following macros are for loading and unloading iotte 100 * entries. 101 */ 102#define COMMON_IOMMU_TTE_SIZE 8 103#define COMMON_IOMMU_TTE_V 0x8000000000000000ull 104#define COMMON_IOMMU_TTE_S 0x1000000000000000ull 105#define COMMON_IOMMU_TTE_C 0x0000000000000010ull 106#define COMMON_IOMMU_TTE_W 0x0000000000000002ull 107#define COMMON_IOMMU_INVALID_TTE 0x0000000000000000ull 108 109/* 110 * Tomatillo's micro TLB bug. errata #82 111 */ 112typedef struct dvma_unbind_req { 113 uint32_t dur_base; 114 uint_t dur_npg; 115 uint_t dur_flags; /* = dmai_flags & DMAI_FLAGS_VMEMCACHE */ 116} dvma_unbind_req_t; 117 118/* 119 * iommu block soft state structure: 120 * 121 * Each pci node may share an iommu block structure with its peer 122 * node of have its own private iommu block structure. 123 */ 124typedef struct iommu iommu_t; 125struct iommu { 126 127 pci_t *iommu_pci_p; /* link back to pci soft state */ 128 int iommu_inst; /* ddi_get_instance(iommu_pci_p->pci_dip) */ 129 130 volatile uint64_t *iommu_ctrl_reg; 131 volatile uint64_t *iommu_tsb_base_addr_reg; 132 volatile uint64_t *iommu_flush_page_reg; 133 volatile uint64_t *iommu_flush_ctx_reg; /* schizo only */ 134 volatile uint64_t *iommu_tfar_reg; /* tomatillo only */ 135 136 /* 137 * virtual and physical addresses and size of the iommu tsb: 138 */ 139 uint64_t *iommu_tsb_vaddr; 140 uint64_t iommu_tsb_paddr; 141 uint_t iommu_tsb_entries; 142 uint_t iommu_tsb_size; 143 144 /* 145 * address ranges of dvma space: 146 */ 147 dvma_addr_t iommu_dvma_base; 148 dvma_addr_t iommu_dvma_end; 149 dvma_addr_t iommu_dvma_fast_end; 150 dvma_addr_t dvma_base_pg; /* = IOMMU_BTOP(iommu_dvma_base) */ 151 dvma_addr_t dvma_end_pg; /* = IOMMU_BTOP(iommu_dvma_end) */ 152 153 /* 154 * address ranges of dma bypass space: 155 */ 156 dma_bypass_addr_t iommu_dma_bypass_base; 157 dma_bypass_addr_t iommu_dma_bypass_end; 158 159 /* 160 * virtual memory map and callback id for dvma space: 161 */ 162 vmem_t *iommu_dvma_map; 163 uintptr_t iommu_dvma_clid; 164 165 /* 166 * fields for fast dvma interfaces: 167 */ 168 ulong_t iommu_dvma_reserve; 169 170 /* 171 * dvma fast track page cache byte map 172 */ 173 uint8_t *iommu_dvma_cache_locks; 174 uint_t iommu_dvma_addr_scan_start; 175 176 /* 177 * dvma context bitmap 178 */ 179 uint64_t *iommu_ctx_bitmap; 180 181 /* 182 * dvma debug 183 */ 184 kmutex_t dvma_debug_lock; 185 uint32_t dvma_alloc_rec_index; 186 uint32_t dvma_free_rec_index; 187 uint32_t dvma_active_count; 188 189 struct dvma_rec *dvma_alloc_rec; 190 struct dvma_rec *dvma_free_rec; 191 struct dvma_rec *dvma_active_list; 192 193 /* 194 * tomatillo's micro TLB bug. errata #82 195 */ 196 dvma_unbind_req_t *iommu_mtlb_req_p; /* unbind requests */ 197 uint32_t iommu_mtlb_maxpgs; /* GC threshold */ 198 uint32_t iommu_mtlb_npgs; /* total page count */ 199 uint32_t iommu_mtlb_nreq; /* total request count */ 200 kmutex_t iommu_mtlb_lock; 201}; 202 203typedef struct pci_dvma_range_prop { 204 uint32_t dvma_base; 205 uint32_t dvma_len; 206} pci_dvma_range_prop_t; 207 208#define IOMMU_PAGE_INDEX(iommu_p, dvma_pg) ((dvma_pg) - (iommu_p)->dvma_base_pg) 209#define IOMMU_PAGE_FLUSH(iommu_p, dvma_pg) \ 210 *(iommu_p)->iommu_flush_page_reg = IOMMU_PTOB(dvma_pg) 211#define IOMMU_UNLOAD_TTE(iommu_p, pg_index) \ 212 (iommu_p)->iommu_tsb_vaddr[pg_index] = COMMON_IOMMU_INVALID_TTE 213#define IOMMU_PAGE_TTEPA(iommu_p, dvma_pg) \ 214 ((iommu_p)->iommu_tsb_paddr + (IOMMU_PAGE_INDEX(iommu_p, dvma_pg) << 3)) 215 216#define IOMMU_CONTEXT_BITS 12 217#define IOMMU_CTX_MASK ((1 << IOMMU_CONTEXT_BITS) - 1) 218#define IOMMU_TTE_CTX_SHIFT 47 219#define IOMMU_CTX2TTE(ctx) (((uint64_t)(ctx)) << IOMMU_TTE_CTX_SHIFT) 220#define IOMMU_TTE2CTX(tte) \ 221 (((tte) >> (IOMMU_TTE_CTX_SHIFT - 32)) & IOMMU_CTX_MASK) 222#define MP2CTX(mp) IOMMU_TTE2CTX((uint32_t)(uintptr_t)(mp)->dmai_tte) 223 224/* dvma debug */ 225#define DVMA_DBG_ON(iommu_p) \ 226 ((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_on) 227#define DVMA_DBG_OFF(iommu_p) \ 228 ((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_off) 229 230extern void pci_dvma_debug_fini(iommu_t *iommu_p); 231extern void pci_dvma_alloc_debug(iommu_t *iommu_p, char *address, uint_t len, 232 ddi_dma_impl_t *mp); 233extern void pci_dvma_free_debug(iommu_t *iommu_p, char *address, uint_t len, 234 ddi_dma_impl_t *mp); 235 236/* dvma routines */ 237extern void iommu_map_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp, 238 dvma_addr_t dvma_pg, size_t npages, size_t pfn_index); 239extern void iommu_unmap_pages(iommu_t *iommu_p, dvma_addr_t dvma_pg, 240 uint_t npages); 241extern void iommu_remap_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp, 242 dvma_addr_t dvma_pg, size_t npages, size_t pfn_index); 243extern void iommu_map_window(iommu_t *iommu_p, 244 ddi_dma_impl_t *mp, window_t window); 245extern void iommu_unmap_window(iommu_t *iommu_p, ddi_dma_impl_t *mp); 246 247/* iommu initialization routines */ 248extern void iommu_configure(iommu_t *iommu_p); 249extern void iommu_create(pci_t *pci_p); 250extern void iommu_destroy(pci_t *pci_p); 251extern uint_t iommu_tsb_size_encode(uint_t tsb_bytes); 252 253/* TSB allocate/free */ 254extern int pci_alloc_tsb(pci_t *pci_p); 255extern void pci_free_tsb(pci_t *pci_p); 256 257#ifdef __cplusplus 258} 259#endif 260 261#endif /* _SYS_PCI_IOMMU_H */ 262