1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright (c) 1999 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27#ifndef _SYS_DB21554_CONFIG_H 28#define _SYS_DB21554_CONFIG_H 29 30#pragma ident "%Z%%M% %I% %E% SMI" 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36#include <sys/types.h> 37#include <sys/pci.h> 38 39#define DB_PCONF_PRI_HDR_OFF 0x00 /* primary offset on primary */ 40#define DB_PCONF_SEC_HDR_OFF 0x40 /* secondary offset on sec */ 41#define DB_SCONF_PRI_HDR_OFF 0x40 /* primary offset on sec */ 42#define DB_SCONF_SEC_HDR_OFF 0x00 /* secondary offset on sec */ 43#define DB_CONF_REGS 0x80 /* configuration regs after hdrs */ 44#define DB_SCONF_HDR_OFF 0x40 /* second config hdr offset */ 45 46/* 47 * Some register definitions for configuration header. 48 */ 49#define DB_PCONF_MEM_CSR PCI_CONF_BASE0 50#define DB_PCONF_IO_CSR PCI_CONF_BASE1 51#define DB_PCONF_DS_IO_MEM1 PCI_CONF_BASE2 52#define DB_PCONF_DS_MEM2 PCI_CONF_BASE3 53#define DB_PCONF_DS_MEM3 PCI_CONF_BASE4 54#define DB_PCONF_DS_UMEM3 PCI_CONF_BASE5 55#define DB_PCONF_EXP_ROM PCI_CONF_ROM 56#define DB_PCONF_US_IO_MEM0 DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE2 57#define DB_PCONF_US_MEM1 DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE3 58#define DB_PCONF_US_MEM2 DB_PCONF_SEC_HDR_OFF+PCI_CONF_BASE4 59 60#define DB_SCONF_MEM_CSR PCI_CONF_BASE0 61#define DB_SCONF_IO_CSR PCI_CONF_BASE1 62#define DB_SCONF_US_IO_MEM0 PCI_CONF_BASE2 63#define DB_SCONF_US_MEM1 PCI_CONF_BASE3 64#define DB_SCONF_US_MEM2 PCI_CONF_BASE4 65#define DB_SCONF_DS_IO_MEM1 DB_SCONF_PRI_HDR_OFF+PCI_CONF_BASE2 66#define DB_SCONF_DS_MEM2 DB_SCONF_PRI_HDR_OFF+PCI_CONF_BASE3 67#define DB_SCONF_DS_MEM3 DB_PCONF_PRI_HDR_OFF+PCI_CONF_BASE4 68#define DB_SCONF_DS_UMEM3 DB_PCONF_PRI_HDR_OFF+PCI_CONF_BASE5 69 70#define DB_IO_BIT 0x00000001 71 72/* register definitions in configuration space after primary/sec. header */ 73 74#define DB_CONF_DS_CONF_ADDR 0x80 /* downstream config address */ 75#define DB_CONF_DS_CONF_DATA 0x84 /* downstream config data */ 76#define DB_CONF_US_CONF_ADDR 0x88 /* upstream config address */ 77#define DB_CONF_US_CONF_DATA 0x8C /* upstream config data */ 78#define DB_CONF_CONF_OWN 0x90 /* config own bits - word reg */ 79#define DB_CONF8_DS_CONF_OWN 0x90 /* config own bits - byte reg */ 80#define DB_CONF8_US_CONF_OWN 0x91 /* config own bits - byte reg */ 81#define DB_CONF_CONF_CSR 0x92 /* config control status - word */ 82#define DB_CONF8_DS_CONF_CSR 0x92 /* config DS CSR - byte reg */ 83#define DB_CONF8_US_CONF_CSR 0x93 /* config US CSR - byte reg */ 84#define DB_CONF_DS_MEM0_TR_BASE 0x94 /* DS memory 0 translated base */ 85#define DB_CONF_DS_IO_MEM1_TR_BASE 0x98 /* DS IO or mem 1 trans base */ 86#define DB_CONF_DS_MEM2_TR_BASE 0x9C /* DS memory 2 translated base */ 87#define DB_CONF_DS_MEM3_TR_BASE 0xA0 /* DS memory 3 translated base */ 88#define DB_CONF_US_IO_MEM0_TR_BASE 0xA4 /* DS IO or mem0 trans base */ 89#define DB_CONF_US_MEM1_TR_BASE 0xA8 /* US memory 1 translated base */ 90#define DB_CONF_DS_MEM0_SETUP 0xAC /* DS memory 0 setup */ 91#define DB_CONF_DS_IO_MEM1_SETUP 0xB0 /* DS IO or memory 1 setup */ 92#define DB_CONF_DS_MEM2_SETUP 0xB4 /* DS memory 2 setup */ 93#define DB_CONF_DS_MEM3_SETUP 0xB8 /* DS memory 3 setup */ 94#define DB_CONF_DS_UP32_MEM3_SETUP 0xBC /* Upper 32bits DS mem3 setup */ 95#define DB_CONF_PRIM_EXP_ROM_SETUP 0xC0 /* Primary Expansion ROM setup */ 96#define DB_CONF_US_IO_MEM0_SETUP 0xC4 /* Upstream IO or memory 0 setup */ 97#define DB_CONF_US_MEM1_SETUP 0xC8 /* upstream memory 1 setup */ 98#define DB_CONF_CHIP_CTRL0 0xCC /* chip control 0 */ 99#define DB_CONF_CHIP_CTRL1 0xCE /* chip control 1 */ 100#define DB_CONF_STATUS 0xD0 /* chip status */ 101#define DB_CONF_ARBITER_CTRL 0xD2 /* Arbiter control */ 102#define DB_CONF_PRIM_SERR_DISABLES 0xD4 /* primary SERR# disables */ 103#define DB_CONF_SEC_SERR_DISABLES 0xD5 /* Secondary SERR# disables */ 104#define DB_CONF_RESET_CTRL 0xD8 /* Reset Control */ 105#define DB_CONF_CAP_ID_1 0xDC /* Capabilities ID */ 106#define DB_CONF_NEXT_ITEM_PTR_1 0xDD /* Next Item Pointer */ 107#define DB_CONF_PM_CAP 0xDE /* Power Management Capabilities */ 108#define DB_CONF_PM_CSR 0xE0 /* Power Management CSR */ 109#define DB_CONF_PM_CSR_BSE 0xE2 /* PMCSR Bridge Support Exts */ 110#define DB_CONF_PM_DATA 0xE3 /* Power Management data */ 111#define DB_CONF_CAP_ID_2 0xE4 /* Capabilities ID */ 112#define DB_CONF_NEXT_ITEM_PTR_2 0xE5 /* Next Item Pointer */ 113#define DB_CONF_VPD_ADDRESS 0xE6 /* VPD Address */ 114#define DB_CONF_VPD_DATA 0xE8 /* VPD Data */ 115#define DB_CONF_CAP_ID_3 0xEC /* Capabilities ID */ 116#define DB_CONF_NEXT_ITEM_PTR_3 0xED /* Next Item Pointer */ 117#define DB_CONF_HS_CSR 0xEE /* Hotswap control status */ 118 119#define DB_VENDOR_ID 0x1011 120#define DB_DEVICE_ID 0x46 121#define DB_INVAL_VEND 0xffff 122 123/* configuration own register bits : Register offset 0x90-91 */ 124#define DS_CONF_OWN 0x0001 /* master owns DSconfig address/data */ 125#define US_CONF_OWN 0x0100 /* master owns USconfig address/data */ 126/* the following is a 8-bit register version definition. */ 127#define DS8_CONF_OWN 0x01 128#define US8_CONF_OWN 0x01 129 130/* configuration control status register bits: Register offset 0x92-93 */ 131#define DS_OWN_STAT 0x0001 /* downstream config own status */ 132#define DS_ENABLE 0x0002 /* enable downstream config cycles */ 133#define US_OWN_STAT 0x0100 /* upstream config own status */ 134#define US_ENABLE 0x0200 /* enable upstream config cycles */ 135 136/* chip control 0 register bits: Register Offset 0xcc-cd */ 137#define DELAYED_TRANS_ORDER 0x0040 /* delayed transaction order control */ 138#define SERR_FWD 0x0080 /* forward SERR# from sec to prim */ 139#define PLOCKOUT 0x0400 /* primary lockout set */ 140#define SEC_CLK_DIS 0x0800 /* disable secondary clock */ 141 142/* chip control 1 register bits: Register Offset 0xce-cf */ 143#define P_PW_THRESHOLD 0x0001 144#define S_PW_THRESHOLD 0x0002 145#define P_DREAD_THRESHOLD_MASK 0x000C 146#define S_DREAD_THRESHOLD_MASK 0x0030 147#define DREAD_THRESHOLD_VALBITS 0x3 148 149#define US_MEM2_DISABLE 0x0000 /* disable USmem2 BAR */ 150#define PAGESIZE_256 0x0100 151#define PAGESIZE_512 0x0200 152#define PAGESIZE_1K 0x0300 153#define PAGESIZE_2K 0x0400 154#define PAGESIZE_4K 0x0500 155#define PAGESIZE_8K 0x0600 156#define PAGESIZE_16K 0x0700 157#define PAGESIZE_32K 0x0800 158#define PAGESIZE_64K 0x0900 159#define PAGESIZE_128K 0x0A00 160#define PAGESIZE_256K 0x0B00 161#define PAGESIZE_512K 0x0C00 162#define PAGESIZE_1M 0x0D00 163#define PAGESIZE_2M 0x0E00 164#define PAGESIZE_4M 0x0F00 165 166#define GET_PAGESIZE(chip_ctrl1) (((chip_ctrl1) & 0x0F00) >> 8) 167 168/* chip reset control register bits : Register Offset 0xd8-db */ 169#define RESET_CTRL_RST_SEC 0x01 /* reset secondary */ 170#define RESET_CTRL_RST 0x02 /* reset chip */ 171#define RESET_CTRL_LSTAT 0x08 /* when set, l_stat is high */ 172 173/* chip status register bits : Register Offset 0xd0-d1 */ 174#define DS_DEL_MTO 0x0001 /* DS delayed master TO */ 175#define DS_DEL_RD_DISCARD 0x0002 /* DS delayed read discard */ 176#define DS_DEL_WR_DISCARD 0x0004 /* DS delayed write discard */ 177#define DS_POST_WRDATA_DISCA 0x0008 178#define US_DEL_MTO 0x0100 /* US delayed trans master TO */ 179#define US_DEL_RD_DISCARD 0x0200 /* US delayed trans.read disc */ 180#define US_DEL_WR_DISCARD 0x0400 /* US delayed trans.writ disc */ 181#define US_POST_WRDATA_DISCA 0x0800 182 183#define DB_PCI_REG_ADDR(bus, device, function, reg) \ 184 (((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \ 185 | (((function) & 0x7) << 8) | ((reg) & 0xff) 186 187/* form a type 0 configuration address */ 188#define DB_PCI_REG_ADDR_TYPE0(bus, device, function, reg) \ 189 (((1 << (device & 0x1f)) << 11) \ 190 | (((function) & 0x7) << 8) | \ 191 ((reg) & 0xfc)) 192 193/* form a type 1 configuration address */ 194#define DB_PCI_REG_ADDR_TYPE1(bus, device, function, reg) \ 195 ((((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \ 196 | (((function) & 0x7) << 8) | ((reg) & 0xfc)) 197 198 199#define DB_ENABLE_PCI_CONF_CYCLE_TYPE0 0 200#define DB_ENABLE_PCI_CONF_CYCLE_TYPE1 1 201 202/* 203 * add local address offsets and get the right config address double 204 * word aligned type 0 format addresses. 205 */ 206#define DB_PCI_CONF_CYCLE_TYPE0_ADDR(conf_addr) \ 207 (((conf_addr) & 0xfffffffc) | DB_ENABLE_PCI_CONF_CYCLE_TYPE0) 208 209/* 210 * add local address offsets and get the right config address double 211 * word aligned type 1 format addresses. 212 */ 213#define DB_PCI_CONF_CYCLE_TYPE1_ADDR(conf_addr) \ 214 (((conf_addr) & 0xfffffffc) | DB_ENABLE_PCI_CONF_CYCLE_TYPE1) 215 216#define PCI_HDR_SIZE 64 217 218typedef struct db_pci_header { 219 uint16_t venid; 220 uint16_t devid; 221 uint16_t command; 222 uint16_t status; 223 uint8_t revid; 224 uint8_t pif; 225 uint8_t subclass; 226 uint8_t class; 227 uint8_t cacheline; 228 uint8_t lat; 229 uint8_t hdr_type; 230 uint8_t bist; 231 uint32_t bar0; 232 uint32_t bar1; 233 uint32_t bar2; 234 uint32_t bar3; 235 uint32_t bar4; 236 uint32_t bar5; 237 uint32_t cardbus_cisp; 238 uint16_t sub_venid; 239 uint16_t sub_devid; 240 uint32_t exprom_bar; 241 uint32_t res1; 242 uint32_t res2; 243 uint8_t int_line; 244 uint8_t int_pin; 245 uint8_t min_gnt; 246 uint8_t max_lat; 247} db_pci_header_t; 248 249typedef struct db_conf_regs { 250 uint32_t ds_mem0_tr_base; /* DS memory 0 translated base */ 251 uint32_t ds_io_mem1_tr_base; /* DS IO or memory1 trans base */ 252 uint32_t ds_mem2_tr_base; /* DS memory 2 trans base */ 253 uint32_t ds_mem3_tr_base; /* DS memory 3 trans base */ 254 uint32_t us_io_mem0_tr_base; /* US IO or memory0 trans base */ 255 uint32_t us_mem1_tr_base; /* US memory 1 translated base */ 256 uint32_t ds_mem0_setup_reg; /* DS memory 0 setup reg */ 257 uint32_t ds_io_mem1_setup_reg; /* DS IO or memory1 setup reg */ 258 uint32_t ds_mem2_setup_reg; /* DS memory 2 setup reg */ 259 uint64_t ds_mem3_setup_reg; /* DS memory 3 setup reg */ 260 uint32_t p_exp_rom_setup; /* primary expansion ROM setup reg */ 261 uint32_t us_io_mem0_setup_reg; /* US IO or memory 0 setup reg */ 262 uint32_t us_mem1_setup_reg; /* US memory 1 setup reg */ 263 ushort_t chip_control0; /* chip control 0 */ 264 ushort_t chip_control1; /* chip control 1 */ 265 ushort_t chip_status; /* chip status */ 266 ushort_t arb_control; /* arbiter control */ 267 uchar_t p_serr_disables; /* primary SERR# disables */ 268 uchar_t s_serr_disables; /* secondary SERR# disables */ 269 ushort_t config_csr; /* configuration control and status */ 270 uint32_t reset_control; /* reset control */ 271 ushort_t pm_cap; /* power management capabilities reg */ 272 ushort_t pm_csr; /* power management control status */ 273 uint8_t hs_csr; /* hotswap control status */ 274} db_conf_regs_t; 275 276#ifdef __cplusplus 277} 278#endif 279 280#endif /* _SYS_DB21554_CONFIG_H */ 281