1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _SMBUS_H 28#define _SMBUS_H 29 30#pragma ident "%Z%%M% %I% %E% SMI" 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36#include <sys/promif.h> 37 38/* 39 * Attach flags 40 */ 41#define SETUP_REGS 0x01 42#define NEXUS_REGISTER 0x02 43#define IMUTEX 0x04 44#define ADD_INTR 0x08 45#define INTERRUPT_PRI 0x10 46 47/* 48 * Register offsets 49 */ 50#define SMB_STS 0x00 51#define SMB_TYP 0x01 52#define STR_PORT 0x02 53#define DEV_ADDR 0x03 54#define DEV_DATA0 0x04 55#define DEV_DATA1 0x05 56#define BLK_DATA 0x06 57#define SMB_CMD 0x07 58 59/* 60 * Bit values for SMB_STS (status) register 61 */ 62#define FAILED 0x80 63#define BUS_ERR 0x40 64#define DRV_ERR 0x20 65#define CMD_CMPL 0x10 66#define HOST_BSY 0x08 67#define IDLE 0x04 68#define INDEX 0x04 69#define TENBITS 0x02 70#define ALERT 0x01 71 72/* 73 * Bit values for the SMB_TYP (command type) register 74 */ 75#define DEV10B_EN 0x80 76#define QUICK_CMD 0x00 77#define SEND_BYTE 0x10 78#define RCV_BYTE 0x10 79#define WR_BYTE 0x20 80#define RD_BYTE 0x20 81#define WR_WORD 0x30 82#define RD_WORD 0x30 83#define WR_BLK 0x40 84#define RD_BLK 0x40 85#define PRC_CALL 0x50 86#define T_OUT 0x08 87#define KILL 0x04 88 89#define SMBUS_PIL 4 90 91#define MAX_BLK_SEND 32 92 93/* 94 * Used to or in bit 0 to be 1 for I2C read address. 95 */ 96#define I2C_READ 0x01 97 98/* 99 * The maximum number of times to retry in event of 100 * a failure. 101 */ 102#define SMBUS_MAX_RETRIES 10 103 104/* 105 * If smbus_put() should make sure the buffer is flushed. 106 */ 107#define SMBUS_FLUSH 0x01 108 109/* 110 * The time in microseconds to wait before the timeout fires 111 * to protect against an interrupt never arriving. 112 */ 113#define INTR_TIMEOUT 100000 114 115/* 116 * Time to wait in microseconds for any transaction before giving up 117 * ie 10 seconds. 118 */ 119#define SMBUS_TRANS_TIMEOUT 10000000 120 121/* 122 * smbus event mode selection. select poll or interrupt mode 123 */ 124 125#define SMBUS_POLL_MODE 1 /* polling mode */ 126#define SMBUS_POLL_TIMEOUT 50000 127 /* 128 * how long to wait(us) for 129 * command completion. 130 */ 131#define SMBUS_POLL_INTERVAL 1 132 /* 133 * time (us) to wait between 134 * polls: must be small in comparison 135 * to the time an an i2c transaction 136 * takes. 137 */ 138/* 139 * Scale polling retries so that the total timeout is "SMBUS_POLL_TIMEOUT" 140 */ 141#define SMBUS_POLL_MAX_RETRIES (SMBUS_POLL_TIMEOUT/SMBUS_POLL_INTERVAL) 142 143 144/* 145 * smbus_ppvt_t contains info that is chip specific 146 * and is stored on the child's devinfo parent private data. 147 */ 148typedef struct smbus_ppvt { 149 int smbus_ppvt_addr; /* address of I2C device */ 150} smbus_ppvt_t; 151 152typedef struct smbus { 153 dev_info_t *smbus_dip; 154 int smbus_attachflags; 155 kmutex_t smbus_mutex; 156 kmutex_t smbus_imutex; 157 kcondvar_t smbus_icv; 158 kcondvar_t smbus_cv; 159 kcondvar_t smbus_intr_cv; 160 ddi_iblock_cookie_t smbus_icookie; 161 int smbus_busy; 162 int smbus_wait; 163 int smbus_bus; 164 i2c_transfer_t *smbus_cur_tran; 165 dev_info_t *smbus_cur_dip; 166 char smbus_name[12]; 167 uint8_t *smbus_regaddr; 168 ddi_acc_handle_t smbus_rhandle; 169 uint8_t *smbus_configregaddr; 170 ddi_acc_handle_t smbus_confighandle; 171 timeout_id_t smbus_timeout; 172 int smbus_saved_w_resid; 173 int smbus_retries; 174 int smbus_bytes_to_read; 175 int smbus_poll_complete; 176 /* 177 * Boolean:true if 178 * polling is complete 179 */ 180 int smbus_polling; 181 /* 182 * Boolean: true if 183 * driver is polling 184 */ 185 int smbus_poll_retries; 186 /* 187 * How many 188 * times we 189 * have polled 190 * the status 191 * register. Not 192 * to be 193 * confused with 194 * "retries", 195 * which is how 196 * many times we 197 * tried after 198 * an error 199 */ 200} smbus_t; 201 202#define PRT_INIT 0x01 203#define PRT_WR 0x02 204#define PRT_RD 0x04 205#define PRT_PUT 0x08 206#define PRT_GET 0x10 207#define PRT_ATTACH 0x20 208#define PRT_INTR 0x40 209#define PRT_INTR_ERR 0x80 210#define PRT_TRANS 0x100 211#define PRT_SPEC 0x200 212#define PRT_BUFFONLY 0x1000 213#define PRT_PROM 0x2000 214 215/* 216 * smbus_switch return status 217 */ 218#define SMBUS_PENDING 0x01 219#define SMBUS_COMPLETE 0x02 220#define SMBUS_FAILURE 0x03 221 222#define SMBUS_SUCCESS 0x04 223 224#define SMBUS_SRC_STATUS 0x48 225#define SMBUS_SRC_ENA 0x44 226#define SMBUS_SMI 0x80000 227#define SMBUS_SMB_INTR_STATUS 0x80000 228 229#define SMBUS_INTR "smbus_intr" 230#define SMBUS_TIMEOUT "smbus_timeout" 231#define SMBUS_POLL "smbus_poll" 232 233#ifdef DEBUG 234#define SMBUS_PRINT(a) smbus_print a 235#else 236#define SMBUS_PRINT(a) 237#endif 238 239 240/* 241 * Other function delcarations 242 */ 243int smbus_transfer(dev_info_t *, i2c_transfer_t *); 244void smbus_print(int flags, const char *fmt, ...); 245 246#ifdef __cplusplus 247} 248#endif 249 250#endif /* _SMBUS_H */ 251