1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 1998 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _SYS_ENVCTRL_H 28#define _SYS_ENVCTRL_H 29 30#pragma ident "%Z%%M% %I% %E% SMI" 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36 37 38 39#define OVERTEMP_TIMEOUT_USEC 60 * MICROSEC 40#define BLINK_TIMEOUT_USEC 500 * (MICROSEC / MILLISEC) 41 42#define ENVCTRL_NORMAL_MODE 0x01 43#define ENVCTRL_DIAG_MODE 0x02 44#define MAX_TAZ_CONTROLLERS 0x02 45#define ENVCTRL_CHAR_ZERO 0x00 46#define ENVCTRL_PS_550 550 47#define ENVCTRL_PS_650 650 48#define ENVCTRL_INIT_TEMPR 20 49#define ENVCTRL_TAZCPU_STRING "SUNW,UltraSPARC" 50#define ENVCTRL_TAZBLKBRDCPU_STRING "SUNW,UltraSPARC-II" 51#define ENVCTRL_MAX_CPUS 8 52 53/* 54 * MACROS 55 */ 56 57#define S1 &unitp->bus_ctl_regs->s1 58#define S0 &unitp->bus_ctl_regs->s0 59 60/* 61 * I2c Sensor Types 62 */ 63 64#define PCD8584 0x00 /* Bus Controller Master */ 65#define PCF8591 0x01 /* Temp Sensor 8bit A/D, D/A */ 66#define PCF8574 0x02 /* PS, FAN, LED, Fail and Control */ 67#define TDA8444T 0x03 /* Fan Speed Control, 8 bit D/A */ 68#define PCF8574A 0x04 /* 8574A chip */ 69#define PCF8583 0x05 /* PCF8583 clock chip */ 70 71/* 72 * Max number of a particular 73 * device on 1 bus. 74 */ 75#define MAX_DEVS 0x10 76#define I2C_NODEV 0xFF 77#define MIN_FAN_BANKS 0x02 78#define INSTANCE_0 0x00 79 80/* 81 * Defines for the PCF8583 Clock Calendar Chip 82 * We use this chip as a watchdog timer for the fans 83 * should the kernel thread controling the fans get 84 * wedged. If it does, the alarm wil go off and 85 * set the fans to max speed. 86 * Valid addresses for this chip are A0, A2. 87 * We use the address at A0. 88 * To address this chip the format is as folows (write mode) 89 * | SLaveaddress |MEMORY LOCATION| DATA| 90 * Wgere memory location is the internal location from 91 * 0x00 - 0x0F. 0x00 is the CSR and MUST be addressed 92 * directly. 93 */ 94 95#define PCF8583_BASE_ADDR 0xA0 96#define PCF8583_READ_BIT 0x01 97 98#define CLOCK_CSR_REG 0x00 99 100#define ALARM_CTRL_REG 0x07 101#define EGG_TIMER_VAL 0x96 102#define DIAG_MAX_TIMER_VAL 0x00 103#define MAX_CL_VAL 59 104#define MIN_DIAG_TEMPR 0x00 105#define MAX_DIAG_TEMPR 70 106#define MAX_AMB_TEMP 50 107#define MAX_CPU_TEMP 80 108#define MAX_PS_TEMP 100 109#define MAX_PS_ADVAL 0xfd 110#define PS_DEFAULT_VAL 17 /* corresponds to 90 C in lookup table */ 111#define PS_TEMP_WARN 95 112#define CPU_AMB_RISE 20 /* cpu runs avg of 20 above amb */ 113#define PS_AMB_RISE 30 /* cpu runs avg of 30 above amb */ 114 115#define CLOCK_ALARM_REG_A 0x08 116#define CLOCK_ENABLE_TIMER 0xCB 117#define CLOCK_ENABLE_TIMER_S 0xCA 118 119#define CLOCK_DISABLE 0xA0 120#define CLOCK_ENABLE 0x04 121 122/* Keyswitch Definitions */ 123#define ENVCTRL_FSP_KEYMASK 0xC0 124#define ENVCTRL_FSP_POMASK 0x20 125#define ENVCTRL_FSP_KEYLOCKED 0x00 126#define ENVCTRL_FSP_KEYOFF 0x40 127#define ENVCTRL_FSP_KEYDIAG 0x80 128#define ENVCTRL_FSP_KEYON 0xC0 129 130/* Disk Fault bit fields */ 131#define ENVCTRL_DISK_0 0x01 132#define ENVCTRL_DISK_1 0x02 133#define ENVCTRL_DISK_2 0x04 134#define ENVCTRL_DISK_3 0x08 135#define ENVCTRL_DISK_4 0x10 136#define ENVCTRL_DISK_5 0x20 137#define ENVCTRL_DISK_6 0x40 138#define ENVCTRL_DISK_7 0x80 139 140#define ENVCTRL_4SLOT_BACKPLANE 0x0F 141#define ENVCTRL_8SLOT_BACKPLANE 0xFF 142 143 144/* Front Status Panel Definitions */ 145#define ENVCTRL_FSP_DISK_ERR 0x01 146#define ENVCTRL_FSP_PS_ERR 0x02 147#define ENVCTRL_FSP_TEMP_ERR 0x04 148#define ENVCTRL_FSP_GEN_ERR 0x08 149#define ENVCTRL_FSP_ACTIVE 0x10 150#define ENVCTRL_FSP_POWER 0x20 151#define ENVCTRL_FSP_USRMASK (ENVCTRL_FSP_DISK_ERR | ENVCTRL_FSP_GEN_ERR) 152 153#define ENVCTRL_ENCL_FSP 0x00 154#define ENVCTRL_ENCL_AMBTEMPR 0x01 155#define ENVCTRL_ENCL_CPUTEMPR 0x02 156#define ENVCTRL_ENCL_BACKPLANE4 0x03 157#define ENVCTRL_ENCL_BACKPLANE8 0x04 158 159#define ENVCTRL_FSP_OFF 0x4F 160#define ENVCTRL_DISK4LED_ALLOFF 0xF0 161#define ENVCTRL_DISK8LED_ALLOFF 0xFF 162 163/* Kstat Structures and defines */ 164#define ENVCTRL_FAN_TYPE_CPU 0x00 165#define ENVCTRL_FAN_TYPE_PS 0x01 166#define ENVCTRL_FAN_TYPE_AFB 0x02 167 168#define ENVCTRL_MODULE_NAME "envctrl" 169#define ENVCTRL_KSTAT_NUMPS "envctrl_numps" 170#define ENVCTRL_KSTAT_PSNAME "envctrl_pwrsupply" 171#define ENVCTRL_KSTAT_NUMFANS "envctrl_numfans" 172#define ENVCTRL_KSTAT_FANSTAT "envctrl_fanstat" 173#define ENVCTRL_KSTAT_NUMENCLS "envctrl_numencls" 174#define ENVCTRL_KSTAT_ENCL "envctrl_enclosure" 175 176typedef struct envctrl_ps { 177 int instance; /* instance of this type */ 178 ushort_t ps_tempr; /* temperature */ 179 int ps_rating; /* type in watts */ 180 boolean_t ps_ok; /* normal state or not. */ 181 boolean_t curr_share_ok; /* current share imbalance */ 182 boolean_t limit_ok; /* overlimit warning */ 183} envctrl_ps_t; 184 185typedef struct envctrl_fan { 186 int instance; /* instance of this type */ 187 int type; /* CPU, PS or AMBIENT fan */ 188 boolean_t fans_ok; /* are the fans okay */ 189 int fanflt_num; /* if not okay, which fan faulted */ 190 uint_t fanspeed; /* chip to set speed of fans */ 191} envctrl_fan_t; 192 193typedef struct envctrl_encl { 194 int instance; 195 int type; 196 uint_t value; 197} envctrl_encl_t; 198 199/* 200 * configuration registers 201 * Register S1 Looks like the following: 202 * WRITE MODE ONLY 203 * 204 * MSB -------------------------------------> LSB 205 * ---------------------------------------------- 206 * | X | ESO | ES1 | ES2 | ENI | STA | STO | ACK | 207 * ---------------------------------------------- 208 * Low order bits 209 */ 210 211#define CSRS1_ENI 0x08 /* Enable interrupts */ 212#define CSRS1_STA 0x04 /* Packet Start */ 213#define CSRS1_STO 0x02 /* Packet Stop */ 214#define CSRS1_ACK 0x01 /* Packet ACK */ 215 216/* Hight order bits */ 217#define CSRS1_PIN 0x80 /* READ and WRITE mode Enable Serial Output */ 218#define CSRS1_ESO 0x40 /* Enable Serial Output */ 219#define CSRS1_ES1 0x20 220#define CSRS1_ES2 0x10 221 222/* 223 * configuration registers 224 * Register S1 Looks like the following: 225 * READ MODE ONLY 226 * 227 * MSB -------------------------------------> LSB 228 * ---------------------------------------------- 229 * | PIN | 0 | STS | BER | AD0/LRB | AAS | LAB | BB| 230 * ---------------------------------------------- 231 */ 232 233#define CSRS1_STS 0x20 /* For Slave receiv mode stop */ 234#define CSRS1_BER 0x10 /* Bus Error */ 235 236#define CSRS1_LRB 0x08 /* Last Received Bit */ 237#define CSRS1_AAS 0x04 /* Addressed as Slave */ 238#define CSRS1_LAB 0x02 /* Lost Arbitration Bit */ 239#define CSRS1_BB 0x01 /* Bus Busy */ 240 241#define START CSRS1_PIN | CSRS1_ESO | CSRS1_STA | CSRS1_ACK 242#define STOP CSRS1_PIN | CSRS1_ESO | CSRS1_STO | CSRS1_ACK 243/* 244 * A read wants to have an NACK on the bus to stop 245 * transmitting data from the slave. If you don't 246 * NACK the SDA line will get stuck low. After this you 247 * can send the stop with the ack. 248 */ 249#define NACK CSRS1_PIN | CSRS1_ESO 250 251/* 252 * ESO = Enable Serial output 253 * ES1 and ES2 have different meanings based upon ES0. 254 * The following table explains this association. 255 * 256 * ES0 = 0 = serial interface off. 257 * --------------------------------------------------------- 258 * | A0 | ES1 | ES1 | iACK | OPERATION 259 * --------------------------------------------------------- 260 * | H | X | X | X | Read/write CSR1 (S1) Status n/a 261 * | | | | | 262 * | L | 0 | 0 | X | R/W Own Address S0' 263 * | | | | | 264 * | L | 0 | 1 | X | R/W Intr Vector S3 265 * | | | | | 266 * | L | 1 | 0 | X | R/W Clock Register S2 267 * --------------------------------------------------------- 268 * 269 * ES0 = 1 = serial interface ON. 270 * --------------------------------------------------------- 271 * | A0 | ES1 | ES1 | iACK | OPERATION 272 * --------------------------------------------------------- 273 * | H | X | X | H | Write Control Register (S1) 274 * | | | | | 275 * | H | X | X | H | Read Status Register (S1) 276 * | | | | | 277 * | L | X | 0 | H | R/W Data Register (S0) 278 * | | | | | 279 * | L | X | 1 | H | R/W Interrupt Vector (S3) 280 * | | | | | 281 * | X | 0 | X | L | R Interrupt Vector (S3) ack cycle 282 * | | | | | 283 * | X | 1 | X | L | long distance mode 284 * --------------------------------------------------------- 285 * 286 */ 287 288#ifdef TESTBED 289struct envctrl_pcd8584_regs { 290 uchar_t s0; /* Own Address S0' */ 291 uchar_t pad[3]; /* Padding XXX Will go away in FCS */ 292 uchar_t s1; /* Control Status register */ 293 uchar_t pad1[3]; 294 uchar_t clock_s2; /* Clock programming register */ 295}; 296#else 297struct envctrl_pcd8584_regs { 298 uchar_t s0; /* Own Address S0' */ 299 uchar_t s1; /* Control Status register */ 300 uchar_t clock_s2; /* Clock programming register */ 301}; 302#endif 303#define ENVCTRL_BUS_INIT0 0x80 304#define ENVCTRL_BUS_INIT1 0x55 305#define ENVCTRL_BUS_CLOCK0 0xA0 306#define ENVCTRL_BUS_CLOCK1 0x1C 307#define ENVCTRL_BUS_ESI 0xC1 308 309 310/* 311 * PCF8591 Chip Used for temperature sensors 312 * 313 * Check with bob to see if singled ended inputs are true 314 * for the pcf8591 temp sensors.. 315 * 316 * Addressing Register definition. 317 * A0-A2 valid range is 0-7 318 * 319 * 7 6 5 4 3 2 1 0 320 * ------------------------------------------------ 321 * | 1 | 0 | 0 | 1 | A2 | A1 | A0 | R/W | 322 * ------------------------------------------------ 323 */ 324 325 326#define PCF8591_BASE_ADDR 0x90 327#define PCF8501_MAX_DEVS 0x08 328 329#define MAXPS 0x02 /* 0 based array */ 330 331#define PSTEMP0 0x00 /* DUMMY PS */ 332#define PSTEMP1 0x94 333#define PSTEMP2 0x92 334#define PSTEMP3 0x90 335#define ENVCTRL_CPU_PCF8591_ADDR (PCF8591_BASE_ADDR | PCF8591_DEV7) 336 337#define PCF8591_DEV0 0x00 338#define PCF8591_DEV1 0x02 339#define PCF8591_DEV2 0x04 340#define PCF8591_DEV3 0x06 341#define PCF8591_DEV4 0x08 342#define PCF8591_DEV5 0x0A 343#define PCF8591_DEV6 0x0C 344#define PCF8591_DEV7 0x0E 345 346 347/* 348 * For the LM75 thermal watchdog chip by TI 349 */ 350 351#define LM75_BASE_ADDR 0x9A 352#define LM75_READ_BIT 0x01 353#define LM75_CONFIG_ADDR2 0x02 354#define LM75_CONFIG_ADDR4 0x04 355#define LM75_CONFIG_ADDR6 0x06 356#define LM75_CONFIG_ADDR8 0x08 357#define LM75_CONFIG_ADDRA 0x0A 358#define LM75_CONFIG_ADDRC 0x0C 359#define LM75_CONFIG_ADDRE 0x0E 360#define LM75_COMP_MASK 0x100 361#define LM75_COMP_MASK_UPPER 0xFF 362 363/* 364 * CONTROL OF CHIP 365 * PCF8591 Temp sensing control register definitions 366 * 367 * 7 6 5 4 3 2 1 0 368 * --------------------------------------------- 369 * | 0 | AOE | X | X | 0 | AIF | X | X | 370 * --------------------------------------------- 371 * AOE = Analog out enable.. not used on out implementation 372 * 5 & 4 = Analog Input Programming.. see data sheet for bits.. 373 * 374 * AIF = Auto increment flag 375 * bits 1 & 0 are for the Chennel number. 376 */ 377 378#define PCF8591_ANALOG_OUTPUT_EN 0x40 379#define PCF8591_ANALOG_INPUT_EN 0x00 380#define PCF8591_READ_BIT 0x01 381 382 383#define PCF8591_AUTO_INCR 0x04 384#define PCF8591_OSCILATOR 0x40 385 386#define PCF8591_MAX_PORTS 0x04 387 388#define PCF8591_CH_0 0x00 389#define PCF8591_CH_1 0x01 390#define PCF8591_CH_2 0x02 391#define PCF8591_CH_3 0x03 392 393struct envctrl_pcf8591_chip { 394 uchar_t chip_num; /* valid values are 0-7 */ 395 int type; /* type is PCF8591 */ 396 uchar_t sensor_num; /* AIN0, AIN1, AIN2 AIN3 */ 397 uchar_t temp_val; /* value of temp probe */ 398}; 399 400 401/* 402 * PCF8574 Fan Fail, Power Supply Fail Detector 403 * This device is driven by interrupts. Each time it interrupts 404 * you must look at the CSR to see which ports caused the interrupt 405 * they are indicated by a 1. 406 * 407 * Address map of this chip 408 * 409 * ------------------------------------------- 410 * | 0 | 1 | 1 | 1 | A2 | A1 | A0 | 0 | 411 * ------------------------------------------- 412 * 413 */ 414 415#define PCF8574A_BASE_ADDR 0x70 416#define PCF8574_BASE_ADDR 0x40 417 418#define PCF8574_READ_BIT 0x01 419 420#define ENVCTRL_PCF8574_DEV0 0x00 421#define ENVCTRL_PCF8574_DEV1 0x02 422#define ENVCTRL_PCF8574_DEV2 0x04 423#define ENVCTRL_PCF8574_DEV3 0x06 424#define ENVCTRL_PCF8574_DEV4 0x08 425#define ENVCTRL_PCF8574_DEV5 0x0A 426#define ENVCTRL_PCF8574_DEV6 0x0C 427#define ENVCTRL_PCF8574_DEV7 0x0E 428#define ENVCTRL_INTR_CHIP PCF8574_DEV7 429 430#define PS1 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV3 431#define PS2 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV2 432#define PS3 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV1 433 434#define ENVCTRL_PCF8574_PORT0 0x01 435#define ENVCTRL_PCF8574_PORT1 0x02 436#define ENVCTRL_PCF8574_PORT2 0x04 437#define ENVCTRL_PCF8574_PORT3 0x08 438#define ENVCTRL_PCF8574_PORT4 0x10 439#define ENVCTRL_PCF8574_PORT5 0x20 440#define ENVCTRL_PCF8574_PORT6 0x40 441#define ENVCTRL_PCF8574_PORT7 0x80 442 443#define ENVCTRL_DFLOP_INIT0 0x77 444#define ENVCTRL_DFLOP_INIT1 0x7F 445 446#define ENVCTRL_DEVINTR_INTI0 0xF7 447#define ENVCTRL_DEVINTR_INTI1 0xFF 448 449#define CPU_FAN_1 0x01 450#define CPU_FAN_2 0x02 451#define CPU_FAN_3 0x03 452 453#define PS_FAN_1 CPU_FAN_1 454#define PS_FAN_2 CPU_FAN_2 455#define PS_FAN_3 CPU_FAN_3 456 457#define AFB_FAN_1 0x00 458 459struct envctrl_pcf8574_chip { 460 uchar_t chip_num; /* valid values are 0-7 */ 461 int type; /* type is PCF8574 */ 462 uint_t val; 463}; 464 465 466/* 467 * TDA8444T chip structure 468 * FAN Speed Control 469 */ 470 471/* ADDRESSING */ 472 473#define TDA8444T_BASE_ADDR 0x40 474 475 476#define ENVCTRL_TDA8444T_DEV0 0x00 477#define ENVCTRL_TDA8444T_DEV1 0x02 478#define ENVCTRL_TDA8444T_DEV2 0x04 479#define ENVCTRL_TDA8444T_DEV3 0x06 480#define ENVCTRL_TDA8444T_DEV4 0x08 481#define ENVCTRL_TDA8444T_DEV5 0x0A 482#define ENVCTRL_TDA8444T_DEV6 0x0C 483#define ENVCTRL_TDA8444T_DEV7 0x0E 484 485#define ENVCTRL_FAN_ADDR_MIN ENVCTRL_TDA8444T_DEV0 486#define ENVCTRL_FAN_ADDR_MAX ENVCTRL_TDA8444T_DEV7 487 488/* Control information and port addressing */ 489 490#define NO_AUTO_PORT_INCR 0xF0 491#define AUTO_PORT_INCR 0x00 492#define TDA8444T_READ_BIT 0x01 493 494#define ENVCTRL_CPU_FANS 0x00 495#define ENVCTRL_PS_FANS 0x01 496#define ENVCTRL_AFB_FANS 0x02 497#define ENVCTRL_PORT3 0x03 498#define ENVCTRL_PORT4 0x04 499#define ENVCTRL_PORT5 0x05 500#define ENVCTRL_PORT6 0x06 501#define ENVCTRL_PORT7 0x07 502 503#define MAX_FAN_SPEED 0x3f 504#define MIN_FAN_VAL 0x00 505#define MAX_FAN_VAL 0x3f 506#define AFB_MAX 0x3f 507#define AFB_MIN 0x1d 508 509struct envctrl_tda8444t_chip { 510 uchar_t chip_num; /* valid values are 0-7 */ 511 int type; /* type is TDA8444T */ 512 uchar_t fan_num; /* Ao0-Ao7 */ 513 uchar_t val; /* for fan speed */ 514}; 515 516/* 517 * This table converts an A/D value from the cpu thermistor to a 518 * temperature in degrees C. Usable range is typically 35-135. 519 */ 520 521static short cpu_temps[] = { 522150, 150, 150, 150, 150, 150, 150, 150, /* 0-7 */ 523150, 150, 150, 150, 150, 150, 150, 150, /* 8-15 */ 524150, 150, 150, 150, 150, 150, 150, 150, /* 16-23 */ 525150, 150, 150, 148, 146, 144, 143, 142, /* 24-31 */ 526141, 140, 138, 136, 135, 134, 133, 132, /* 32-39 */ 527131, 130, 129, 128, 127, 126, 125, 124, /* 40-47 */ 528123, 122, 121, 121, 120, 120, 119, 118, /* 48-55 */ 529117, 116, 115, 114, 113, 112, 112, 111, /* 56-63 */ 530111, 110, 110, 110, 109, 109, 108, 107, /* 64-71 */ 531106, 106, 105, 105, 104, 103, 102, 101, /* 72-79 */ 532101, 100, 100, 100, 99, 99, 98, 98, /* 80-87 */ 53397, 97, 96, 96, 95, 95, 94, 94, /* 88-95 */ 53493, 93, 92, 92, 91, 91, 91, 90, /* 96-103 */ 53590, 90, 89, 89, 88, 88, 87, 87, /* 104-111 */ 53686, 86, 85, 85, 84, 84, 83, 83, /* 112-119 */ 53782, 82, 82, 81, 81, 80, 80, 80, /* 120-127 */ 53880, 79, 79, 79, 78, 78, 78, 77, /* 128-135 */ 53977, 77, 76, 76, 76, 75, 75, 75, /* 136-143 */ 54074, 74, 74, 73, 73, 73, 72, 72, /* 144-151 */ 54172, 71, 71, 71, 70, 70, 70, 70, /* 142-159 */ 54269, 69, 69, 68, 68, 68, 68, 67, /* 160-167 */ 54367, 67, 67, 66, 66, 66, 66, 65, /* 168-175 */ 54465, 65, 64, 64, 64, 63, 63, 63, /* 176-183 */ 54562, 62, 62, 61, 61, 61, 61, 60, /* 184-191 */ 54660, 60, 60, 59, 59, 59, 58, 58, /* 192-199 */ 54758, 57, 57, 57, 56, 56, 56, 56, /* 200-207 */ 54855, 55, 55, 55, 54, 54, 54, 53, /* 208-215 */ 54953, 53, 52, 52, 52, 51, 51, 51, /* 216-223 */ 55051, 50, 50, 50, 49, 49, 49, 48, /* 224-231 */ 55148, 48, 47, 47, 47, 46, 46, 46, /* 232-239 */ 55245, 45, 45, 44, 44, 44, 43, 43, /* 240-247 */ 55343, 42, 42, 42, 41, 41, 41, 40, /* 248-255 */ 55440, /* 256 */ 555}; 556 557static short ps_temps[] = { 558160, 155, 154, 150, 130, 125, 120, 115, /* 0-7 */ 559110, 110, 106, 103, 101, 100, 97, 94, /* 8-15 */ 56092, 90, 88, 86, 84, 83, 82, 81, /* 16-23 */ 56180, 79, 78, 77, 76, 74, 72, 71, /* 24-31 */ 56270, 69, 68, 67, 66, 65, 64, 63, /* 32-39 */ 56362, 62, 61, 61, 60, 60, 60, 59, /* 40-47 */ 56459, 58, 58, 57, 56, 56, 55, 55, /* 48-55 */ 56554, 54, 53, 53, 52, 52, 51, 51, /* 56-63 */ 56650, 50, 50, 49, 49, 49, 49, 48, /* 64-71 */ 56748, 48, 48, 47, 47, 47, 47, 46, /* 72-79 */ 56846, 46, 45, 44, 43, 42, 41, 41, /* 80-87 */ 56940, 40, 40, 40, 39, 39, 39, 38, /* 88-95 */ 57038, 38, 37, 37, 36, 36, 36, 35, /* 96-103 */ 57135, 35, 35, 34, 34, 34, 33, 33, /* 104-111 */ 57232, 32, 32, 32, 32, 32, 31, 31, /* 112-119 */ 57331, 31, 31, 30, 30, 30, 29, 29, /* 120-127 */ 57429, 29, 29, 29, 28, 28, 28, 28, /* 128-135 */ 57528, 28, 27, 27, 27, 27, 27, 26, /* 136-143 */ 57626, 26, 26, 26, 26, 26, 26, 26, /* 144-151 */ 57725, 25, 25, 25, 24, 24, 23, 23, /* 142-159 */ 57822, 22, 21, 21, 21, 21, 21, 21, /* 160-167 */ 57920, 20, 20, 20, 19, 19, 19, 19, /* 168-175 */ 58019, 18, 18, 18, 18, 18, 17, 17, /* 176-183 */ 58117, 17, 17, 16, 16, 16, 16, 15, /* 184-191 */ 58215, 15, 15, 15, 15, 14, 14, 14, /* 192-199 */ 58314, 14, 13, 13, 13, 13, 12, 12, /* 200-207 */ 58412, 12, 12, 11, 11, 11, 11, 11, /* 208-215 */ 58510, 10, 10, 10, 10, 10, 10, 10, /* 216-223 */ 5869, 9, 9, 9, 9, 9, 8, 8, /* 224-231 */ 5878, 8, 8, 7, 7, 7, 7, 7, /* 232-239 */ 5887, 6, 6, 6, 6, 6, 6, 6, /* 240-247 */ 5895, 5, 5, 5, 5, 5, 5, 4, /* 248-255 */ 5904, /* 256 */ 591}; 592 593/* 594 * This is the lookup table used for P1 and FCS systems to convert a temperature 595 * to a fanspeed for the CPU side of the machine. 596 */ 597 598static short acme_cpu_fanspd[] = { 59931, 31, 31, 31, 31, 31, 31, 31, /* 0-7 */ 60031, 31, 31, 31, 31, 31, 31, 31, /* 8-15 */ 60131, 31, 31, 31, 31, 31, 31, 31, /* 16-23 */ 60231, 31, 31, 31, 32, 33, 34, 35, /* 24-31 */ 60336, 37, 38, 39, 40, 42, 43, 45, /* 32-39 */ 60448, 49, 50, 51, 52, 53, 54, 55, /* 40-47 */ 60556, 57, 58, 59, 60, 61, 62, 63, /* 48-55 */ 60663, 63, 63, 63, 63, 63, 63, 63, /* 56-63 */ 60763, 63, 63, 63, 63, 63, 63, 63, /* 64-71 */ 60863, 63, 63, 63, 63, 63, 63, 63, /* 72-79 */ 60963, 63, 63, 63, 63, 63, 63, 63, /* 80-87 */ 61063, 63, 63, 63, 63, 63, 63, 63, /* 88-95 */ 61163, 63, 63, 63, 63, 63, 63, 63, /* 96-103 */ 61263, 63, 63, 63, 63, 63, 63, 63, /* 104-111 */ 613}; 614 615/* 616 * This is the lookup table used for P1 and FCS systems to convert a temperature 617 * to a fanspeed for the CPU side of the machine. 618 */ 619 620static short acme_ps_fanspd[] = { 62131, 31, 31, 31, 31, 31, 31, 31, /* 0-7 */ 62231, 31, 31, 31, 31, 31, 31, 31, /* 8-15 */ 62331, 31, 31, 31, 31, 31, 31, 31, /* 16-23 */ 62431, 31, 31, 31, 31, 33, 34, 35, /* 24-31 */ 62536, 37, 38, 38, 39, 40, 41, 42, /* 32-39 */ 62643, 45, 46, 47, 48, 48, 48, 48, /* 40-47 */ 62748, 48, 49, 50, 51, 52, 53, 54, /* 48-55 */ 62855, 56, 57, 58, 59, 60, 61, 62, /* 56-63 */ 62963, 63, 63, 63, 63, 63, 63, 63, /* 64-71 */ 63063, 63, 63, 63, 63, 63, 63, 63, /* 72-79 */ 63163, 63, 63, 63, 63, 63, 63, 63, /* 80-87 */ 63263, 63, 63, 63, 63, 63, 63, 63, /* 88-95 */ 63363, 63, 63, 63, 63, 63, 63, 63, /* 96-103 */ 63463, 63, 63, 63, 63, 63, 63, 63, /* 104-111 */ 635}; 636 637static short ps_fans[] = { 63810, 10, 10, 10, 10, 10, 10, 10, /* 0-7 */ 63910, 10, 10, 10, 10, 10, 10, 10, /* 8-15 */ 64010, 10, 10, 10, 10, 10, 10, 10, /* 16-23 */ 64110, 10, 10, 10, 10, 10, 10, 10, /* 24-31 */ 64210, 10, 10, 10, 10, 10, 10, 10, /* 32-39 */ 64311, 12, 13, 14, 15, 16, 17, 18, /* 24-31 */ 64419, 20, 21, 22, 23, 24, 25, 26, /* 32-39 */ 64527, 28, 29, 30, 31, 32, 33, 34, /* 40-47 */ 64635, 36, 37, 38, 39, 40, 41, 42, /* 48-55 */ 64743, 44, 45, 46, 47, 48, 49, 50, /* 56-63 */ 64850, 50, 50, 50, 50, 50, 50, 50, /* 56-63 */ 64913, 12, 11, 10, 10, 10, 10, 10, /* 64-71 */ 65010, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65110, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65210, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65310, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65410, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65510, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65610, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65710, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65810, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 65910, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66010, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66110, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66210, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66310, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66410, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66510, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66610, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66710, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66810, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 66910, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 67010, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 67110, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */ 67210, 673}; 674 675/* 676 * Get a fan speed setting based upon a temperature value 677 * from the above lookup tables. 678 * Less than zero ia a special case and greater than 70 is a 679 * the operating range of the powersupply. The system operating 680 * range is 5 - 40 Degrees C. 681 * This may need some tuning. 682 * The MAX_CPU_TEMP is set to 80 now, this table is used to set their 683 * fans. 684 */ 685static short fan_speed[] = { 68630, 29, 28, 27, 26, 25, 24, 23, /* 0-7 */ 68723, 23, 23, 23, 22, 21, 20, 20, /* 8-15 */ 68820, 20, 20, 20, 20, 20, 20, 20, /* 16-23 */ 68919, 18, 17, 16, 15, 14, 13, 12, /* 24-31 */ 69011, 11, 11, 11, 11, 11, 11, 11, /* 32-39 */ 69111, 11, 11, 10, 10, 10, 9, 8, /* 40-47 */ 6927, 6, 5, 4, 3, 2, 1, 1, /* 48-55 */ 6931, 1, 1, 1, 1, 1, 1, 1, /* 56-63 */ 6941, 1, 1, 1, 1, 1, 1, 1, /* 64-71 */ 6951, 1, 1, 1, 1, 1, 1, 1, /* 72-79 */ 6961, 1, 1, 1, 1, 1, 1, 1, /* 80-87 */ 697}; 698 699 700#define ENVCTRL_PANEL_LEDS_PR "panel-leds-present" 701#define ENVCTRL_PANEL_LEDS_STA "panel-leds-state" 702#define ENVCTRL_DISK_LEDS_PR "disk-leds-present" 703#define ENVCTRL_DISK_LEDS_STA "disk-leds-state" 704#define ENVCTRL_LED_BLINK "activity-led-blink?" 705 706#define ENVCTRL_IOC_RESETTMPR (int)(_IOW('p', 76, uchar_t)) 707#define ENVCTRL_IOC_SETMODE (int)(_IOW('p', 77, uchar_t)) 708#define ENVCTRL_IOC_SETTEMP (int)(_IOW('p', 79, uchar_t)) 709#define ENVCTRL_IOC_SETFAN (int)(_IOW('p', 80, struct envctrl_tda8444t_chip)) 710#define ENVCTRL_IOC_SETWDT (int)(_IOW('p', 81, uchar_t)) 711#define ENVCTRL_IOC_GETFAN (int)(_IOR('p', 81, struct envctrl_tda8444t_chip)) 712#define ENVCTRL_IOC_GETTEMP (int)(_IOR('p', 82, struct envctrl_pcf8591_chip)) 713#define ENVCTRL_IOC_GETFANFAIL (int)(_IOR('p', 83, struct envctrl_pcf8574_chip)) 714#define ENVCTRL_IOC_SETFSP (int)(_IOW('p', 84, uchar_t)) 715#define ENVCTRL_IOC_SETDSKLED (int)(_IOW('p', 85, struct envctrl_pcf8574_chip)) 716#define ENVCTRL_IOC_GETDSKLED (int)(_IOR('p', 86, struct envctrl_pcf8574_chip)) 717#define ENVCTRL_IOC_GETMODE (int)(_IOR('p', 87, uchar_t)) 718 719#if defined(_KERNEL) 720 721struct envctrlunit { 722 struct envctrl_pcd8584_regs *bus_ctl_regs; 723 ddi_acc_handle_t ctlr_handle; 724 kmutex_t umutex; /* lock for this structure */ 725 int instance; 726 dev_info_t *dip; /* device information */ 727 struct envctrl_ps ps_kstats[MAX_DEVS]; /* kstats for powersupplies */ 728 struct envctrl_fan fan_kstats[MAX_DEVS]; /* kstats for fans */ 729 struct envctrl_encl encl_kstats[MAX_DEVS]; /* kstats for enclosure */ 730 int cpu_pr_location[ENVCTRL_MAX_CPUS]; /* slot true if cpu present */ 731 uint_t num_fans_present; 732 uint_t num_ps_present; 733 uint_t num_encl_present; 734 uint_t num_cpus_present; 735 kstat_t *psksp; 736 kstat_t *fanksp; 737 kstat_t *enclksp; 738 ddi_iblock_cookie_t ic_trap_cookie; /* interrupt cookie */ 739 queue_t *readq; /* pointer to readq */ 740 queue_t *writeq; /* pointer to writeq */ 741 mblk_t *msg; /* current message block */ 742 /* CPR support */ 743 boolean_t suspended; /* TRUE if driver suspended */ 744 boolean_t oflag; /* already open */ 745 int current_mode; /* NORMAL or DIAG_MODE */ 746 int AFB_present; /* is the AFB present */ 747 timeout_id_t timeout_id; /* timeout id */ 748 timeout_id_t pshotplug_id; /* ps poll id */ 749 int ps_present[MAXPS+1]; /* PS present t/f 0 not used */ 750 int num_fans_failed; /* don't change fan speed if > 0 */ 751 int activity_led_blink; 752 int present_led_state; /* is it on or off?? */ 753 timeout_id_t blink_timeout_id; 754 int initting; /* 1 is TRUE , 0 is FALSE , used to mask intrs */ 755 boolean_t shutdown; /* TRUE = power off in error event */ 756 757}; 758 759#endif /* _KERNEL */ 760 761#ifdef __cplusplus 762} 763#endif 764 765#endif /* _SYS_ENVCTRL_H */ 766