1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2000-2002 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _SYS_DR_MBX_H 28#define _SYS_DR_MBX_H 29 30#pragma ident "%Z%%M% %I% %E% SMI" 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36#ifdef _KERNEL 37#include <sys/mboxsc.h> 38#endif /* _KERNEL */ 39#include <post/scat_const.h> 40 41/* this version of the DR - SC mailbox interface */ 42#define DRMBX_VERSION 0x0016 43 44#define DR_KEY(a, b, c, d) \ 45 (((uint_t)(a) << 24) | ((uint_t)(b) << 16) \ 46 | ((uint_t)(c) << 8) | ((uint_t)(d))) 47#define KEY_DRSC DR_KEY('D', 'R', 'S', 'C') 48#define KEY_SCDR DR_KEY('S', 'C', 'D', 'R') 49 50#define DRSC_TIMEOUT 30 51#define BD_TYPELEN 16 52#define DR_HPOPTLEN 512 /* maximum length of hpost options */ 53 54/* Commands */ 55#define DRMSG_BOARDEVENT 0x1 /* must be 0x1 in every vesion */ 56#define DRMSG_MBOX_INIT 0x2 /* must be 0x2 in every version */ 57#define DRMSG_ASSIGN 0x3 58#define DRMSG_UNASSIGN 0x4 59#define DRMSG_CLAIM 0x5 60#define DRMSG_UNCLAIM 0x6 61#define DRMSG_POWERON 0x7 62#define DRMSG_POWEROFF 0x8 63#define DRMSG_TESTBOARD 0x9 64#define DRMSG_ABORT_TEST 0xa 65#define DRMSG_SHOWBOARD 0xb 66#define DRMSG_UNCONFIG 0xc 67 68 69/* Test status definitions */ 70#define DR_TEST_STATUS_UNKNOWN 0x1 71#define DR_TEST_STATUS_IPOST 0x2 72#define DR_TEST_STATUS_PASSED 0x3 73#define DR_TEST_STATUS_FAILED 0x4 74#define DR_TEST_STATUS_ABORTED 0x5 75 76/* Message reply status definitions */ 77#define DRMSG_REPLY_OK 0x0 78#define DRMSG_REPLY_FAIL 0x1 79 80/* Error Code definitions */ 81#define DRERR_NOACL 0x1 /* Board is not in domain's ACL */ 82#define DRERR_NOT_ASSIGNED 0x2 /* Board isn't assigned to domain */ 83#define DRERR_NOT_ACTIVE 0x3 /* Board is not active */ 84#define DRERR_EMPTY_SLOT 0x4 /* The board (slot) is empty */ 85#define DRERR_POWER_OFF 0x5 /* The specified board is powered off */ 86#define DRERR_TEST_IN_PROGRESS 0x6 /* The board is being tested */ 87#define DRERR_TESTING_BUSY 0x7 /* All SC test resources are in use */ 88#define DRERR_TEST_REQUIRED 0x8 /* Board requires test prior to use */ 89#define DRERR_UNAVAILABLE 0x9 /* Slot is not available to domain */ 90#define DRERR_RECOVERABLE 0xa /* Failed, may safely retry */ 91#define DRERR_UNRECOVERABLE 0xb /* Failed, resource unusable */ 92 93/* 94 * Protocol Header and message structure definitions 95 */ 96 97/* DR-SC Protocol Header */ 98typedef struct { 99 uint32_t message_id; 100 uint16_t drproto_version; 101 uint8_t command; 102 uint8_t expbrd; 103 uint8_t slot; 104 uint8_t reply_status; 105 uint8_t error_code; 106 uint8_t pad[1]; /* explicit pad to 4 byte alignment */ 107} dr_proto_hdr_t; 108 109/* Showboard reply structure (from SC) */ 110typedef struct { 111 uint8_t slot_empty :1, 112 power_on :1, 113 bd_assigned :1, 114 bd_active :1, 115 test_status :4; 116 uint8_t test_level; 117 char board_type[BD_TYPELEN]; 118} dr_showboard_t; 119 120/* CPU Memory Controller constants and macros */ 121#define DRMACH_MC_VALID_MASK (0x1ull << 63) 122#define DRMACH_MC_UK_MASK (0xFFFull << 41) 123#define DRMACH_MC_UM_MASK (0x1FFFFFull << 20) 124#define DRMACH_MC_LK_MASK (0xFull << 14) 125#define DRMACH_MC_LM_MASK (0xFull << 8) 126 127#define DRMACH_MC_UK(madr) (((madr) & DRMACH_MC_UK_MASK) >> 41) 128#define DRMACH_MC_UM_TO_PA(madr) (((madr) & DRMACH_MC_UM_MASK) << 6) 129#define DRMACH_MC_LM_TO_PA(madr) (((madr) & DRMACH_MC_LM_MASK) >> 2) 130#define DRMACH_MC_PA_TO_UM(pa) (((pa) >> 6) & DRMACH_MC_UM_MASK) 131#define DRMACH_MC_PA_TO_LM(pa) (((pa) << 2) & DRMACH_MC_LM_MASK) 132 133/* Claim/Unclaim/Unconfig request structures */ 134typedef struct { 135 uint8_t valid :1, 136 unused :2, 137 slice :5; 138} dr_memslice_t; 139 140/* 141 * Since uint64_t can't be used in DR mailbox messages due to alignment and 142 * backwards compatibility issues, the 64 bit MADR and MACR register values must 143 * be broken into high and low uint32_t values. 144 */ 145#define DRMACH_MCREG_TO_U64(mcreg) (((uint64_t)mcreg.hi) << 32 | \ 146 ((uint64_t)mcreg.lo)) 147#define DRMACH_U64_TO_MCREGHI(u64) ((uint32_t)((u64) >> 32)) 148#define DRMACH_U64_TO_MCREGLO(u64) ((uint32_t)(u64)) 149typedef struct { 150 uint32_t hi; 151 uint32_t lo; 152} dr_mcreg_t; 153 154/* 155 * Each expander can contain S0_LPORT_COUNT memory controllers (each CPU has one 156 * memory controller, and slot 1 doesn't support memory), and each controller 157 * contains PMBANKS_PER_PORT * LMBANKS_PER_PMBANK (the total number of memory 158 * banks supported by each controller) MADR registers 159 */ 160typedef struct { 161 dr_mcreg_t madr[S0_LPORT_COUNT][PMBANKS_PER_PORT * 162 LMBANKS_PER_PMBANK]; 163} dr_memregs_t; 164 165typedef struct { 166 dr_memslice_t mem_slice[18]; 167 uint8_t mem_clear; 168 uint8_t pad[1]; /* explicit pad to 4 byte alignment */ 169 dr_memregs_t mem_regs[18]; 170} dr_unclaim_t; 171 172typedef struct { 173 dr_memslice_t mem_slice[18]; 174 uint8_t pad[2]; /* explicit pad to 4 byte alignment */ 175 dr_memregs_t mem_regs[18]; 176} dr_claim_t; 177 178typedef struct { 179 dr_memslice_t mem_slice[18]; 180 uint8_t pad[2]; /* explicit pad to 4 byte alignment */ 181 dr_memregs_t mem_regs[18]; 182} dr_unconfig_t; 183 184/* CPU Portid macros */ 185#define DRMBX_PORTID2EXP(cpu_portid) \ 186 (((cpu_portid) >> 5) & 0x1F) 187#define DRMBX_PORTID2SLOT(cpu_portid) \ 188 (((((cpu_portid) >> 4) & 0x7E) | (((cpu_portid) >> 3) & 0x01)) & 1) 189#define DRMBX_PORTID2AGID(cpu_portid) ((cpu_portid) & 0x1F) 190 191/* Test board request structure */ 192typedef struct { 193 uint32_t memaddrhi; 194 uint32_t memaddrlo; 195 uint32_t memlen; 196 uint16_t cpu_portid; 197 uint8_t force :1, 198 immediate :1, 199 reserved :6; 200 char hpost_opts[DR_HPOPTLEN]; 201} dr_testboard_req_t; 202 203/* Test board reply structure (from SC) */ 204typedef struct { 205 uint32_t memaddrhi; 206 uint32_t memaddrlo; 207 uint32_t memlen; 208 uint16_t cpu_portid; 209 uint8_t cpu_recovered :1, 210 test_status :4, 211 reserved :3; 212} dr_testboard_reply_t; 213 214/* Test Abort structure (bi-directional) */ 215typedef struct { 216 uint32_t memaddrhi; 217 uint32_t memaddrlo; 218 uint32_t memlen; 219 uint16_t cpu_portid; 220} dr_abort_test_t; 221 222 223/* Board event structure (from SC) */ 224typedef struct { 225 uint16_t initialized :1, 226 board_insertion :1, 227 board_removal :1, 228 slot_assign :1, 229 slot_unassign :1, 230 slot_avail :1, 231 slot_unavail :1, 232 power_on :1, 233 power_off :1, 234 reserved :7; 235} dr_boardevent_t; 236 237/* 238 * NOTE: The structures in this union all require 4 byte alignment or less. It 239 * is forbidden to add any structure that requires 8 byte alignment, as doing so 240 * will alter the dr_mbox_msg_t structure, thereby breaking compatibility with 241 * older software. (Since the dr_proto_hdr_t structure is 12 bytes long, it 242 * can't be followed immediately by an 8 byte aligned structure, and the 243 * compiler will implicitly insert 4 padding bytes.) 244 */ 245typedef union { 246 dr_showboard_t dm_sb; 247 dr_unclaim_t dm_ur; 248 dr_claim_t dm_cr; 249 dr_unconfig_t dm_uc; 250 dr_testboard_req_t dm_tb; 251 dr_testboard_reply_t dm_tr; 252 dr_abort_test_t dm_ta; 253 dr_boardevent_t dm_be; 254} dr_msg_t; 255 256typedef struct { 257 dr_proto_hdr_t p_hdr; 258 dr_msg_t msgdata; 259} dr_mbox_msg_t; 260 261#ifdef __cplusplus 262} 263#endif 264 265#endif /* _SYS_DR_MBX_H */ 266