1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#ifndef	_SYS_SGSBBC_PRIV_H
28#define	_SYS_SGSBBC_PRIV_H
29
30#pragma ident	"%Z%%M%	%I%	%E% SMI"
31
32#ifdef	__cplusplus
33extern "C" {
34#endif
35
36/*
37 * Private structures used by the Serengeti SBBC Driver
38 *
39 * The Serengeti SBBC driver handles communication between the
40 * System Controller Software (ScApp) and Solaris via SBBC
41 * registers and IOSRAM.
42 *
43 * This header file contains necessary definitions to enable
44 * such communication.
45 *
46 * Register offsets and definitions can be found in
47 * Serengeti Architecture Programmer's Reference
48 * Revision 1.3 11/16/1999
49 * Section 2.5 to 2.8
50 */
51
52#include <sys/types.h>
53#include <sys/dditypes.h>
54#include <sys/sgsbbc.h>
55
56/*
57 * SBBC Interrupt registers
58 */
59#define	SBBC_MAX_INTRS		32
60
61/*
62 * Different interrupts
63 */
64#define	INTERRUPT_ON	0x1	/* bit 0 */
65/*
66 * EPLD Interrupt Register Offset for communication with the SC
67 */
68#define	EPLD_INTERRUPT	0x13
69
70/*
71 * register numbers for mapping in OBP reg properties
72 */
73#define	RNUM_SBBC_REGS		1
74
75/*
76 * SBBC registers and devices on CPU/memory board
77 */
78#define	SBBC_REGS_OFFSET	0x800000
79#define	SBBC_REGS_SIZE		0x6230
80#define	SBBC_EPLD_OFFSET	0x8e0000
81#define	SBBC_EPLD_SIZE		0x20
82#define	SBBC_SRAM_OFFSET	0x900000
83#define	SBBC_SRAM_SIZE		0x20000		/* max. 128KB of SRAM */
84/*
85 * Register Offsets
86 */
87#define	SBBC_PCI_INT_STATUS	0x2320
88#define	SBBC_PCI_INT_ENABLE	0x2330
89
90/*
91 * Port Interrupt Enable Register
92 *
93 * Field	Bits	Reset	Type	Description
94 *			State
95 * Resvd	<31:8>	0	R	Reserved
96 * PINT1_EN	<7:4>	0	RW	Enables for each of the 4 PCI
97 *					interrupt lines for Port Interrupt
98 *					Generation register 1.  Bit 7
99 *					corresponds to PCI Interrupt D,
100 *					bit 4 corresponds to PCI Interrupt A.
101 * PINT0_EN	<3:0>	0	RW	Same as above, but for register 0.
102 */
103#define	SBBC_PCI_ENABLE_INT_A	0x11	/* Enable both PCI Interrupt A */
104#define	SBBC_PCI_ENABLE_MASK	0xff	/* Mask for the two enable registers */
105
106#ifdef	DEBUG
107#define	SGSBBC_DBG_MASK_MBOX		0x00000001
108#define	SGSBBC_DBG_MASK_INTR		0x00000002
109#define	SGSBBC_DBG_MASK_EVENT		0x00000004
110
111extern uint_t sgsbbc_debug;
112#define	SGSBBC_DBG_ALL	if (sgsbbc_debug)	prom_printf
113#define	SGSBBC_DBG_MBOX \
114	if (sgsbbc_debug & SGSBBC_DBG_MASK_MBOX) printf
115#define	SGSBBC_DBG_INTR \
116	if (sgsbbc_debug & SGSBBC_DBG_MASK_INTR) cmn_err
117#define	SGSBBC_DBG_EVENT \
118	if (sgsbbc_debug & SGSBBC_DBG_MASK_EVENT) cmn_err
119
120#else	/* DEBUG */
121#define	SGSBBC_DBG_ALL
122#define	SGSBBC_DBG_MBOX
123#define	SGSBBC_DBG_INTR
124#define	SGSBBC_DBG_EVENT
125
126#endif	/* DEBUG */
127
128
129typedef struct sbbc_intrs {
130	sbbc_intrfunc_t		sbbc_handler;	/* interrupt handler */
131	caddr_t			sbbc_arg;	/* interrupt argument */
132	ddi_softintr_t		sbbc_intr_id;
133	kmutex_t		*sbbc_intr_lock;	/* for state flag */
134	uint_t			*sbbc_intr_state;	/* handler state */
135	struct sbbc_intrs	*sbbc_intr_next;
136	int			registered;
137} sbbc_intrs_t;
138
139struct sbbc_epld_regs {
140	uchar_t		epld_reg[32];
141};
142
143/*
144 * device soft state
145 */
146typedef struct sbbc_softstate {
147	struct sbbc_softstate	*prev;
148	struct sbbc_softstate	*next;
149
150	struct chosen_iosram    *iosram; /* back reference */
151	dev_info_t 		*dip;
152
153	/*
154	 * Tunnel Info.
155	 */
156	void			*sram;
157
158	/*
159	 * SBBC Register Info.
160	 */
161	caddr_t				sbbc_regs;	/* common device regs */
162	uint32_t			*port_int_regs; /* interrupt regs */
163	struct sbbc_epld_regs		*epld_regs;	/* EPLD regs */
164	uint32_t			sram_toc;	/* SRAM TOC */
165
166	/*
167	 * device map handles for register mapping
168	 */
169	ddi_acc_handle_t		sbbc_reg_handle1;
170	ddi_acc_handle_t		sbbc_reg_handle2;
171	/*
172	 * SBBC Interrupts
173	 */
174	uint_t			inumber;
175	ddi_iblock_cookie_t 	iblock;
176	ddi_idevice_cookie_t 	idevice;
177
178	sbbc_intrs_t		*intr_hdlrs;
179
180	/*
181	 * misc.
182	 */
183	kmutex_t		sbbc_lock;	/* mutex for this struct */
184	uchar_t			suspended;	/* TRUE if instance suspended */
185	uchar_t			chosen;		/* TRUE if instance 'chosen' */
186	int			sbbc_instance;
187	int			sbbc_state;	/* see below */
188} sbbc_softstate_t;
189/* sbbc iosram state */
190#define	SBBC_STATE_INIT 0x0001		/* initialization */
191#define	SBBC_STATE_DETACH 0x0002	/* IOSRAM instance being detached */
192
193/*
194 * Structure used for tunnel switch
195 */
196typedef struct {
197	dev_info_t	*cur_dip;	/* current dip that we compare to */
198	dev_info_t	*new_dip;	/* new dip that fits the condition */
199} sbbc_find_dip_t;
200
201/*
202 * Routines for mapping and unmapping SBBC internal registers
203 */
204extern int	sbbc_map_regs(sbbc_softstate_t *);
205
206/*
207 * Interrupt related routines
208 */
209extern int	sbbc_add_intr(sbbc_softstate_t *);
210extern void	sbbc_enable_intr(sbbc_softstate_t *);
211extern void	sbbc_disable_intr(sbbc_softstate_t *);
212extern int	sbbc_send_intr(sbbc_softstate_t *, int);
213extern uint_t	sbbc_intr_handler();
214
215extern sbbc_softstate_t	*sbbc_get_soft_state(int);
216
217/*
218 * To protect master_chosen
219 */
220extern kmutex_t chosen_lock;
221
222#ifdef	__cplusplus
223}
224#endif
225
226#endif	/* _SYS_SGSBBC_PRIV_H */
227