1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_OPL_HWDESC_H 27#define _SYS_OPL_HWDESC_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35/* 36 * Hardware Descriptor. 37 */ 38 39#define HWD_SBS_PER_DOMAIN 32 /* System boards per domain */ 40#define HWD_CPUS_PER_CORE 4 /* Strands per physical core */ 41#define HWD_CORES_PER_CPU_CHIP 4 /* Cores per processor chip */ 42#define HWD_CPU_CHIPS_PER_CMU 4 /* Processor chips per CMU */ 43#define HWD_SCS_PER_CMU 4 /* System controllers per CMU */ 44#define HWD_DIMMS_PER_CMU 32 /* Memory DIMMs per CMU */ 45#define HWD_IOCS_PER_IOU 2 /* Oberon chips per I/O unit */ 46#define HWD_PCI_CHANNELS_PER_IOC 2 /* PCI channels per Oberon chip */ 47#define HWD_LEAVES_PER_PCI_CHANNEL 2 /* Leaves per PCI channel */ 48#define HWD_PCI_CHANNELS_PER_SB 4 /* PCI channels per system board */ 49#define HWD_CMU_CHANNEL 4 /* CMU channel number */ 50#define HWD_IO_BOATS_PER_IOU 6 /* I/O boats per I/O unit */ 51#define HWD_BANKS_PER_CMU 8 /* Memory banks per CMU */ 52#define HWD_MAX_MEM_CHUNKS 8 /* Chunks per board */ 53 54typedef uint32_t hwd_stat_t; /* component status */ 55 56/* 57 * Values for hwd_stat_t. 58 */ 59#define HWD_STAT_UNKNOWN 0x0000 /* No status yet */ 60#define HWD_STAT_PRESENT 0x0001 /* Present */ 61#define HWD_STAT_MISS 0x0002 /* Missing */ 62#define HWD_STAT_MISCONFIG 0x0003 /* Misconfigured */ 63#define HWD_STAT_PASS 0x0004 /* Ok */ 64#define HWD_STAT_FAIL 0x0080 /* Failed by XSCF */ 65#define HWD_STAT_FAIL_OBP 0x0081 /* Failed by POST/OBP */ 66#define HWD_STAT_FAIL_OS 0x0082 /* Failed by OS */ 67 68#define HWD_STAT_FAILED 0x0080 69 70#define HWD_MASK_NOT_USED 0x8000 /* If this bit is set, the component */ 71 /* is not used (even if it presents) */ 72 73#define HWD_STATUS_FAILED(stat) ((stat) & HWD_STAT_FAILED) 74#define HWD_STATUS_OK(stat) ((stat) == HWD_STAT_PASS) 75#define HWD_STATUS_PRESENT(stat) \ 76 ((stat) & (HWD_STAT_PRESENT | HWD_STAT_PASS)) 77#define HWD_STATUS_NONE(stat) \ 78 (((stat) == HWD_STAT_UNKNOWN) || ((stat) == HWD_STAT_MISS)) 79 80#define HWD_VERSION_MAJOR 1 81#define HWD_VERSION_MINOR 1 82 83/* 84 * Hardware Descriptor Header. 85 * 86 * Some fields occur repeatedly in different structures: 87 * 88 * spare* This field is for future use. 89 * 90 * filler* This field is used to show alignment. This could also 91 * be used in the future for something. 92 * 93 * check_sum This contains the check sum of the structure it resides in. 94 */ 95typedef struct { 96 uint32_t hdr_magic; /* magic code ('HWDE') */ 97 struct hwdesc_version { 98 uint16_t major; 99 uint16_t minor; 100 } hdr_version; /* structure version */ 101 102 /* 103 * Domain Identifier. The OPL system can have 104 * upto 24 domains so domain id can be 0 - 23. 105 */ 106 uint8_t hdr_domain_id; 107 char hdr_filler[3]; 108 109 /* 110 * offsets from the beginning of the header to: 111 * - SB status information (hwd_sb_status_t) 112 * - domain information (hwd_domain_info_t) 113 * - SB information (hwd_sb_info_t). 114 */ 115 uint32_t hdr_sb_status_offset; 116 uint32_t hdr_domain_info_offset; 117 uint32_t hdr_sb_info_offset; 118 119 uint32_t hdr_spare[9]; 120 uint32_t hdr_check_sum; 121} hwd_header_t; 122 123/* 124 * SB Status 125 */ 126typedef struct { 127 hwd_stat_t sb_status[HWD_SBS_PER_DOMAIN]; /* status of all LSBs */ 128 /* PSB number of respective LSB */ 129 uint8_t sb_psb_number[HWD_SBS_PER_DOMAIN]; 130 uint32_t sb_spare[7]; 131 uint32_t sb_check_sum; 132} hwd_sb_status_t; 133 134/* 135 * SP -> Domain Information. 136 */ 137typedef struct { 138 uint32_t dinf_reset_factor; /* domain reset reason */ 139 uint32_t dinf_host_id; /* domain unique id */ 140 uint64_t dinf_system_frequency; /* Hz */ 141 uint64_t dinf_stick_frequency; /* Hz */ 142 uint32_t dinf_scf_command_timeout; /* SCF i/f timeout seconds */ 143 uint32_t dinf_model_info; /* FF1/2 DC1/2/3 */ 144 uint8_t dinf_mac_address[6]; /* system MAC address */ 145 uint8_t dinf_filler1[10]; 146 uint8_t dinf_dr_status; /* 0: DR capable, !0: no DR */ 147 uint8_t dinf_filler2[7]; 148 /* 149 * Specification of degeneracy operation of POST by XSCF 150 * 0x00: off 151 * 0x20: component 152 * 0x40: board 153 * 0x80: system 154 */ 155 uint8_t dinf_config_policy; 156 /* 157 * Specification of diagnosis operation of POST by XSCF 158 * 0x00: off 159 * 0x20: min 160 * 0x40: max 161 */ 162 uint8_t dinf_diag_level; 163 /* 164 * Specification of boot operation of OBP by XSCF 165 * 0x00: It follows other settings. 166 * 0x80: Auto boot is not done. 167 */ 168 uint8_t dinf_boot_mode; 169 uint8_t dinf_spare1[5]; 170 int64_t dinf_cpu_start_time; /* seconds since the Epoch */ 171 char dinf_banner_name[64]; /* system banner string */ 172 char dinf_platform_token[64]; /* platform name */ 173 uint32_t dinf_floating_board_bitmap; /* bit 0 = SB0 ... */ 174 char dinf_chassis_sn[16]; 175 uint32_t dinf_brand_control; 176 uint32_t dinf_spare2[7]; 177 uint32_t dinf_check_sum; 178} hwd_domain_info_t; 179 180/* 181 * CPU Strand 182 */ 183typedef struct { 184 hwd_stat_t cpu_status; 185 char cpu_component_name[32]; 186 uint16_t cpu_cpuid; /* 0x0000, 0x0001, ... 0x01ff */ 187 uint16_t cpu_filler; 188 uint32_t cpu_spare[6]; 189} hwd_cpu_t; 190 191/* 192 * CPU Core 193 */ 194typedef struct { 195 hwd_stat_t core_status; 196 char core_component_name[32]; 197 uint32_t core_filler1; 198 uint64_t core_frequency; /* Hz */ 199 uint64_t core_config; /* bus config reg */ 200 uint64_t core_version; /* processor VER */ 201 uint16_t core_manufacturer; /* VER.manuf */ 202 uint16_t core_implementation; /* VER.impl */ 203 uint8_t core_mask; /* VER.mask */ 204 uint8_t core_filler2[3]; 205 uint32_t core_l1_icache_size; 206 uint16_t core_l1_icache_line_size; 207 uint16_t core_l1_icache_associativity; 208 uint32_t core_num_itlb_entries; 209 uint32_t core_l1_dcache_size; 210 uint16_t core_l1_dcache_line_size; 211 uint16_t core_l1_dcache_associativity; 212 uint32_t core_num_dtlb_entries; 213 uint32_t core_spare1[4]; 214 uint32_t core_l2_cache_size; 215 uint16_t core_l2_cache_line_size; 216 uint16_t core_l2_cache_associativity; 217 uint32_t core_l2_cache_sharing; /* bit N:coreN */ 218 uint32_t core_spare2[5]; 219 hwd_cpu_t core_cpus[HWD_CPUS_PER_CORE]; 220 uint32_t core_spare3[4]; 221} hwd_core_t; 222 223/* 224 * CPU Chip 225 */ 226typedef struct { 227 hwd_stat_t chip_status; 228 char chip_component_name[32]; /* example: "CPU#x" */ 229 char chip_fru_name[32]; /* example: "CPU#x" */ 230 char chip_compatible[32]; /* example: "FJSV,SPARC64-VI" */ 231 /* 232 * Jupiter Bus Device ID 233 * 0x0400, 0x0408, ... , 0x05f8 234 */ 235 uint16_t chip_portid; 236 uint16_t chip_filler; 237 uint32_t chip_spare1[6]; 238 hwd_core_t chip_cores[HWD_CORES_PER_CPU_CHIP]; 239 uint32_t chip_spare2[4]; 240} hwd_cpu_chip_t; 241 242/* 243 * SC 244 */ 245typedef struct { 246 hwd_stat_t sc_status; 247 uint32_t sc_filler; 248 /* 249 * Top address of SC registers in this XSB 250 */ 251 uint64_t sc_register_address; 252} hwd_sc_t; 253 254/* 255 * Bank 256 */ 257typedef struct { 258 hwd_stat_t bank_status; 259 hwd_stat_t bank_cs_status[2]; /* DIMM pair status */ 260 uint32_t bank_filler1; 261 uint64_t bank_register_address; /* address of mem patrol regs */ 262 uint8_t bank_mac_ocd; /* calibrated MAC OCD value */ 263 uint8_t bank_filler2[3]; 264 uint8_t bank_dimm_ocd[4][2]; /* calibrated DIMM OCD value */ 265 uint32_t bank_tune; /* for POST use */ 266 uint32_t bank_spare[2]; 267} hwd_bank_t; 268 269/* 270 * Chunk 271 */ 272typedef struct { 273 uint64_t chnk_start_address; 274 uint64_t chnk_size; 275} hwd_chunk_t; 276 277/* 278 * Dimm 279 */ 280typedef struct { 281 hwd_stat_t dimm_status; 282 uint32_t dimm_filler1; 283 uint64_t dimm_capacity; /* bytes */ 284 uint64_t dimm_available_capacity; /* bytes */ 285 uint8_t dimm_rank; /* 1 or 2 */ 286 uint8_t dimm_filler2[7]; 287 char dimm_component_name[32]; /* "MEM#xyz" */ 288 char dimm_fru_name[32]; /* "MEM#xyz" */ 289} hwd_dimm_t; 290 291/* 292 * CS 293 */ 294typedef struct { 295 hwd_stat_t cs_status; 296 uint8_t cs_number_of_dimms; 297 uint8_t cs_filler[3]; 298 uint64_t cs_available_capacity; 299 uint64_t cs_dimm_capacity; 300 uint8_t cs_dimm_badd[8]; /* Value to initialize MAC by POST */ 301 uint16_t cs_dimm_add[8]; /* Value to initialize MAC by POST */ 302 uint8_t cs_pa_mac_table[64]; /* PA <-> MAC address conversion */ 303} hwd_cs_t; 304 305/* 306 * Memory 307 */ 308typedef struct { 309 uint64_t mem_start_address; /* Memory start for this LSB */ 310 uint64_t mem_size; /* Memory size for this LSB */ 311 hwd_bank_t mem_banks[HWD_BANKS_PER_CMU]; 312 /* 313 * Mirroring mode: 314 * 0x00 or 0x01 315 * 0x00 : not 'memory mirror mode' 316 * 0x01 : 'memory mirror mode' 317 */ 318 uint8_t mem_mirror_mode; /* mirroring mode */ 319 /* 320 * Memory configuration: 321 * 0x01 : 1 divided mode 322 * 0x02 : 2 divided mode 323 * 0x04 : 4 divided mode 324 * 325 * It is always set to 0x04 at the XSB mode. 326 */ 327 uint8_t mem_division_mode; 328 uint8_t mem_piece_number; /* 0-3 memory slot group used */ 329 uint8_t mem_cs_interleave; /* 1:cs interleave, 0:not */ 330 uint32_t mem_filler[3]; 331 uint8_t mem_available_bitmap[512]; /* for POST use */ 332 uint8_t mem_degrade_bitmap[16384]; /* for POST use */ 333 hwd_chunk_t mem_chunks[HWD_MAX_MEM_CHUNKS]; 334 hwd_dimm_t mem_dimms[HWD_DIMMS_PER_CMU]; 335 hwd_cs_t mem_cs[2]; 336} hwd_memory_t; 337 338typedef struct { 339 hwd_stat_t scf_status; 340 char scf_component_name[32]; /* "SCFI#z" */ 341} hwd_scf_interface_t; 342 343typedef struct { 344 hwd_stat_t tty_status; 345 char tty_component_name[32]; /* "TTY#z" */ 346} hwd_tty_t; 347 348typedef struct { 349 uint8_t fver_major; /* firmware major version */ 350 uint8_t fver_minor; /* firmware minor version */ 351 uint8_t fver_local; /* firmware local version */ 352 uint8_t fver_filler; 353} hwd_fmem_version_t; 354 355typedef struct { 356 hwd_stat_t fmem_status; /* status of flash */ 357 char fmem_component_name[32]; 358 uint8_t fmem_used; /* non-zero: fmem is used */ 359 uint8_t fmem_filler[3]; 360 hwd_fmem_version_t fmem_version; 361 uint32_t fmem_spare; 362} hwd_fmem_t; 363 364/* 365 * CMU CH 366 */ 367typedef struct { 368 hwd_stat_t chan_status; 369 /* 370 * CMU_CH port ID 371 * LSB0 is 0x0008, LSB1 is 0x0018, ... , LSB15 is 0x00f8 372 */ 373 uint16_t chan_portid; 374 uint16_t chan_filler; 375 char chan_component_name[32]; /* "U2P#z" */ 376 hwd_scf_interface_t chan_scf_interface; 377 hwd_tty_t chan_serial; 378 hwd_fmem_t chan_fmem[2]; 379} hwd_cmu_chan_t; 380 381/* 382 * CMU 383 */ 384typedef struct { 385 char cmu_component_name[32]; /* example: "CxS0y" */ 386 char cmu_fru_name[32]; /* example: "Cabinet#x-CMU#y" */ 387 388 hwd_cpu_chip_t cmu_cpu_chips[HWD_CPU_CHIPS_PER_CMU]; /* CPU */ 389 hwd_sc_t cmu_scs[HWD_SCS_PER_CMU]; /* SC */ 390 hwd_memory_t cmu_memory; /* Memory */ 391 hwd_cmu_chan_t cmu_ch; /* CMU CH */ 392 uint32_t cmu_spare[32]; 393} hwd_cmu_t; 394 395typedef struct { 396 hwd_stat_t slot_status; 397 char slot_name[16]; 398} hwd_slot_t; 399 400/* 401 * IO Boat 402 */ 403typedef struct { 404 hwd_stat_t iob_status; 405 char iob_component_name[32]; 406 char iob_fru_name[32]; 407 /* 408 * IO_Boat type 409 * 0x01 : PCI-X Slot Type 410 * 0x02 : PCI Express Slot Type 411 */ 412 uint32_t iob_type; /* PCI-X or PCI Express */ 413 uint64_t iob_io_box_info; /* location of I/O */ 414 /* 415 * Information of switch on IO_boat 416 * use only switch_status[0] when PCI-X type IO_boat 417 */ 418 hwd_stat_t iob_switch_status[3]; /* PCIE switch statuses */ 419 /* 420 * Information of bridge on IO_boat 421 * use only when PCI-X type IO_boat 422 */ 423 hwd_stat_t iob_bridge_status[3]; /* PCIX bridge statuses */ 424 hwd_slot_t iob_slot[6]; /* PCI slot names */ 425 uint32_t iob_spare[8]; 426} hwd_io_boat_t; 427 428/* IOU PCI Express Slot */ 429typedef struct { 430 uint32_t iou_type; /* 0: empty, 1: card, 2: IO boat */ 431 hwd_slot_t iou_slot; 432 hwd_io_boat_t iou_io_boat; 433} hwd_iou_slot_t; 434 435typedef struct { 436 hwd_stat_t ff_onb_switch_status; 437 uint8_t ff_onb_filler[64]; 438 hwd_stat_t ff_onb_bridge_status; 439 hwd_stat_t ff_onb_sas_status; 440 hwd_stat_t ff_onb_gbe_status; 441 hwd_iou_slot_t ff_onb_slot; 442 hwd_slot_t ff_onb_xslot; 443} hwd_ff_onboard_t; 444 445typedef struct { 446 hwd_stat_t ioua_status; /* IOUA status */ 447 char ioua_component_name[32]; 448 char ioua_fru_name[32]; 449 hwd_stat_t ioua_bridge_status; 450 hwd_stat_t ioua_sas_status; 451 hwd_stat_t ioua_gbe_status; 452} hwd_ioua_t; 453 454typedef struct { 455 uint8_t iou_desc_filler[80]; 456 hwd_iou_slot_t iou_desc_slot; 457} hwd_iou_slot_desc_t; 458 459typedef struct { 460 hwd_stat_t leaf_status; 461 uint16_t leaf_port_id; /* portid (logical leaf id) */ 462 uint8_t leaf_filler[6]; 463 uint32_t leaf_slot_type; /* card or boat */ 464 union { 465 hwd_ff_onboard_t leaf_ff_onboard; 466 hwd_ioua_t leaf_ioua; 467 hwd_iou_slot_desc_t leaf_iou_slot; 468 uint8_t leaf_spare[448]; 469 } leaf_u; 470 uint64_t leaf_cfgio_offset; /* config space offset */ 471 uint64_t leaf_cfgio_size; /* config space size */ 472 uint64_t leaf_mem32_offset; /* offset of mem32 area */ 473 uint64_t leaf_mem32_size; /* size of mem32 area */ 474 uint64_t leaf_mem64_offset; /* offset of mem64 area */ 475 uint64_t leaf_mem64_size; /* size of mem64 area */ 476} hwd_leaf_t; 477 478/* 479 * PCI CH 480 */ 481typedef struct { 482 hwd_stat_t pci_status; /* PCI CH status */ 483 char pci_component_name[32]; 484 char pci_fru_name[32]; 485 uint8_t pci_filler[12]; 486 hwd_leaf_t pci_leaf[HWD_LEAVES_PER_PCI_CHANNEL]; 487} hwd_pci_ch_t; 488 489/* 490 * System Board 491 */ 492typedef struct { 493 /* 494 * SB 495 */ 496 hwd_stat_t sb_status; 497 uint8_t sb_mode; /* 0:PSB 1:XSB */ 498 uint8_t sb_psb_number; /* PSB number for this LSB */ 499 uint8_t sb_filler1[10]; 500 501 hwd_cmu_t sb_cmu; /* CMU */ 502 503 hwd_pci_ch_t sb_pci_ch[HWD_PCI_CHANNELS_PER_SB]; /* PCI CH */ 504 505 uint32_t sb_spare[31]; 506 uint32_t sb_check_sum; 507} hwd_sb_t; 508 509#define HWD_DATA_SIZE (36 * 1024) /* Size of HWD data from SCF */ 510 511#ifdef __cplusplus 512} 513#endif 514 515#endif /* _SYS_OPL_HWDESC_H */ 516