1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25#ifndef _SYS_PX_LIB4U_H
26#define	_SYS_PX_LIB4U_H
27
28#ifdef	__cplusplus
29extern "C" {
30#endif
31
32/*
33 * Errors returned.
34 */
35#define	H_EOK			0	/* Successful return */
36#define	H_ENOINTR		1	/* Invalid interrupt id */
37#define	H_EINVAL		2	/* Invalid argument */
38#define	H_ENOACCESS		3	/* No access to resource */
39#define	H_EIO			4	/* I/O error */
40#define	H_ENOTSUPPORTED		5	/* Function not supported */
41#define	H_ENOMAP		6	/* Mapping is not valid, */
42					/* no translation exists */
43
44/*
45 * Register base definitions.
46 *
47 * The specific numeric values for CSR, XBUS, Configuration,
48 * Interrupt blocks and other register bases.
49 */
50typedef enum {
51	PX_REG_CSR = 0,
52	PX_REG_XBC,
53	PX_REG_CFG,
54	PX_REG_IC,
55	PX_REG_MAX
56} px_reg_bank_t;
57
58/*
59 * Registers/state/variables that need to be saved and restored during
60 * suspend/resume.
61 *
62 * SUN4U px specific data structure.
63 */
64
65/* Control block soft state structure */
66typedef struct px_cb_list {
67	px_t			*pxp;
68	struct px_cb_list	*next;
69} px_cb_list_t;
70
71/* IO chip type */
72typedef enum {
73	PX_CHIP_UNIDENTIFIED = 0,
74	PX_CHIP_FIRE = 1,
75	PX_CHIP_OBERON = 2
76} px_chip_type_t;
77
78#define	PX_CHIP_TYPE(pxu_p)	((pxu_p)->chip_type)
79
80typedef struct px_cb {
81	px_cb_list_t	*pxl;		/* linked list px */
82	kmutex_t	cb_mutex;	/* lock for CB */
83	sysino_t	sysino;		/* proxy sysino */
84	cpuid_t		cpuid;		/* proxy cpuid */
85	int		attachcnt;	/* number of attached px */
86	uint_t		(*px_cb_func)(caddr_t); /* CB intr dispatcher */
87} px_cb_t;
88
89typedef struct pxu {
90	px_chip_type_t	chip_type;
91	uint8_t		portid;
92	uint16_t	tsb_cookie;
93	uint32_t	tsb_size;
94	uint64_t	*tsb_vaddr;
95	uint64_t	tsb_paddr;	/* Only used for Oberon */
96	sysino_t	hp_sysino;	/* Oberon hotplug interrupt */
97
98	void		*msiq_mapped_p;
99	px_cb_t		*px_cb_p;
100
101	/* Soft state for suspend/resume */
102	uint64_t	*pec_config_state;
103	uint64_t	*mmu_config_state;
104	uint64_t	*ib_intr_map;
105	uint64_t	*ib_config_state;
106	uint64_t	*xcb_config_state;
107	uint64_t	*msiq_config_state;
108	uint_t		cpr_flag;
109
110	/* sun4u specific vars */
111	caddr_t			px_address[4];
112	ddi_acc_handle_t	px_ac[4];
113	uint64_t		obp_tsb_paddr;
114	uint_t			obp_tsb_entries;
115
116	/* PCItool */
117	caddr_t		pcitool_addr;
118} pxu_t;
119
120#define	PX2CB(px_p) (((pxu_t *)px_p->px_plat_p)->px_cb_p)
121
122/* cpr_flag */
123#define	PX_NOT_CPR	0
124#define	PX_ENTERED_CPR	1
125
126/*
127 * Event Queue data structure.
128 */
129typedef	struct eq_rec {
130	uint64_t	eq_rec_rsvd0 : 1,	/* DW 0 - 63 */
131			eq_rec_fmt_type : 7,	/* DW 0 - 62:56 */
132			eq_rec_len : 10,	/* DW 0 - 55:46 */
133			eq_rec_addr0 : 14,	/* DW 0 - 45:32 */
134			eq_rec_rid : 16,	/* DW 0 - 31:16 */
135			eq_rec_data0 : 16;	/* DW 0 - 15:00 */
136	uint64_t	eq_rec_addr1 : 48,	/* DW 1 - 63:16 */
137			eq_rec_data1 : 16;	/* DW 1 - 15:0 */
138	uint64_t	eq_rec_rsvd[6];		/* DW 2-7 */
139} eq_rec_t;
140
141/*
142 * EQ record type
143 *
144 * Upper 4 bits of eq_rec_fmt_type is used
145 * to identify the EQ record type.
146 */
147#define	EQ_REC_MSG	0x6			/* MSG   - 0x3X */
148#define	EQ_REC_MSI32	0xB			/* MSI32 - 0x58 */
149#define	EQ_REC_MSI64	0xF			/* MSI64 - 0x78 */
150
151/* EQ State */
152#define	EQ_IDLE_STATE	0x1			/* IDLE */
153#define	EQ_ACTIVE_STATE	0x2			/* ACTIVE */
154#define	EQ_ERROR_STATE	0x4			/* ERROR */
155
156/*
157 * Default EQ Configurations
158 */
159#define	EQ_CNT		36
160#define	EQ_REC_CNT	128
161#define	EQ_1ST_ID	0
162#define	EQ_1ST_DEVINO	24
163
164#define	MMU_INVALID_TTE		0ull
165#define	MMU_TTE_VALID(tte)	(((tte) & MMU_TTE_V) == MMU_TTE_V)
166#define	MMU_OBERON_PADDR_MASK	0x7fffffffffff
167#define	MMU_FIRE_PADDR_MASK	0x7ffffffffff
168
169/*
170 * control register decoding
171 */
172/* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */
173#define	MMU_CTL_TO_TSBSIZE(ctl)		((ctl) >> 16)
174#define	MMU_TSBSIZE_TO_TSBENTRIES(s)	((1 << (s)) << (13 - 3))
175
176/*
177 * For Fire mmu bypass addresses, bit 43 specifies cacheability.
178 */
179#define	MMU_FIRE_BYPASS_NONCACHE	 (1ull << 43)
180
181/*
182 * For Oberon mmu bypass addresses, bit 47 specifies cacheability.
183 */
184#define	MMU_OBERON_BYPASS_NONCACHE	 (1ull << 47)
185
186/*
187 * The following macros define the address ranges supported for DVMA
188 * and mmu bypass transfers. For Oberon, bit 63 is used for ordering.
189 */
190#define	MMU_FIRE_BYPASS_BASE		0xFFFC000000000000ull
191#define	MMU_FIRE_BYPASS_END		0xFFFC03FFFFFFFFFFull
192
193#define	MMU_OBERON_BYPASS_BASE		0x7FFC000000000000ull
194#define	MMU_OBERON_BYPASS_END		0x7FFC7FFFFFFFFFFFull
195
196#define	MMU_OBERON_BYPASS_RO		0x8000000000000000ull
197
198#define	MMU_TSB_PA_MASK		0x7FFFFFFFE000
199
200/*
201 * The following macros are for loading and unloading io tte
202 * entries.
203 */
204#define	MMU_TTE_SIZE		8
205#define	MMU_TTE_V		(1ull << 63)
206#define	MMU_TTE_W		(1ull << 1)
207#define	MMU_TTE_RO		(1ull << 62)	/* Oberon Relaxed Ordering */
208
209#define	INO_BITS		6	/* INO#s are 6 bits long */
210#define	INO_MASK		0x3F	/* INO#s mask */
211
212#define	SYSINO_TO_DEVINO(sysino)	(sysino & INO_MASK)
213
214#define	FIRE_IGN_MASK		0x1F	/* IGN#s mask, 5 bits long for Fire */
215#define	OBERON_IGN_MASK		0xFF	/* IGN#s mask, 8 bits long for Oberon */
216
217#define	ID_TO_IGN(chip, portid) ((portid) & ((chip) == PX_CHIP_OBERON ? \
218	OBERON_IGN_MASK : FIRE_IGN_MASK))
219
220#define	DEVINO_TO_SYSINO(portid, devino) \
221	(((portid) << INO_BITS) | ((devino) & INO_MASK))
222
223/* Interrupt states */
224#define	INTERRUPT_IDLE_STATE		0
225#define	INTERRUPT_RECEIVED_STATE	1
226#define	INTERRUPT_PENDING_STATE		3
227
228/*
229 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer
230 * and TxLink Replay Timer Latency Table array sizes
231 * Num		Link Width		Packet Size
232 * 0		1			128
233 * 1		4			256
234 * 2		8			512
235 * 3		16			1024
236 * 4		-			2048
237 * 5		-			4096
238 */
239#define	LINK_WIDTH_ARR_SIZE		4
240#define	LINK_MAX_PKT_ARR_SIZE		6
241
242/*
243 * Defines for registers which have multi-bit fields.
244 */
245#define	TLU_LINK_CONTROL_ASPM_DISABLED			0x0
246#define	TLU_LINK_CONTROL_ASPM_L0S_EN			0x1
247#define	TLU_LINK_CONTROL_ASPM_L1_EN			0x2
248#define	TLU_LINK_CONTROL_ASPM_L0S_L1_EN			0x3
249
250#define	TLU_CONTROL_CONFIG_DEFAULT			0x1
251#define	TLU_CONTROL_L0S_TIM_DEFAULT			0xdaull
252#define	TLU_CONTROL_MPS_MASK				0x1C
253#define	TLU_CONTROL_MPS_SHIFT				2
254
255#define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0	0x0
256#define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1	0x1
257#define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2	0x2
258#define	LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3	0x3
259
260#define	LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT	0xFFFFull
261#define	LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT	0x0ull
262
263#define	LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT	0xFFF
264#define	LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT	0x0
265#define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF	0x157
266
267#define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT	0xFFF
268#define	LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT	0x0
269
270#define	LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT		0x2
271#define	LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT		0x5
272#define	LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT		0x2DC6C0
273#define	LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT		0x7A120
274#define	LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT		0x2
275#define	LPU_LTSSM_CONFIG4_N_FTS_DEFAULT			0x8c
276
277/* LPU LTSSM states */
278#define	LPU_LTSSM_L0			0x0
279#define	LPU_LTSSM_L1_IDLE		0x15
280
281/* TLU Control register bits */
282#define	TLU_REMAIN_DETECT_QUIET		8
283
284/*
285 * Fire hardware specific version definitions.
286 * All Fire versions > 2.0 will be numerically greater than FIRE_MOD_REV_20
287 */
288#define	FIRE_MOD_REV_20	0x03
289
290/*
291 * Oberon specific definitions.
292 */
293#define	OBERON_RANGE_PROP_MASK	0x7fff
294
295/*
296 * HW specific paddr mask.
297 */
298extern uint64_t px_paddr_mask;
299
300extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p);
301extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p);
302extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p);
303extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p);
304
305extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p,
306    devino_t devino, sysino_t *sysino);
307extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino,
308    intr_valid_state_t *intr_valid_state);
309extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino,
310    intr_valid_state_t intr_valid_state);
311extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino,
312    intr_state_t *intr_state);
313extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino,
314    intr_state_t intr_state);
315extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p,
316    sysino_t sysino, cpuid_t *cpuid);
317extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p,
318    sysino_t sysino, cpuid_t cpuid);
319
320extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
321    pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index,
322    int flags);
323extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p,
324    tsbid_t tsbid, pages_t pages);
325extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p,
326    tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p);
327extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p,
328    r_addr_t ra, io_attributes_t attr, io_addr_t *io_addr_p);
329extern uint64_t hvio_get_bypass_base(pxu_t *pxu_p);
330extern uint64_t hvio_get_bypass_end(pxu_t *pxu_p);
331extern uint64_t px_get_range_prop(px_t *px_p, pci_ranges_t *rp, int bank);
332extern void hvio_obptsb_attach(pxu_t *pxu_p);
333extern void hvio_obptsb_detach(px_t *px_p);
334
335
336/*
337 * MSIQ Functions:
338 */
339extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p);
340extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
341    pci_msiq_valid_state_t *msiq_valid_state);
342extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
343    pci_msiq_valid_state_t msiq_valid_state);
344extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
345    pci_msiq_state_t *msiq_state);
346extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
347    pci_msiq_state_t msiq_state);
348extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
349    msiqhead_t *msiq_head);
350extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
351    msiqhead_t msiq_head);
352extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
353    msiqtail_t *msiq_tail);
354
355/*
356 * MSI Functions:
357 */
358extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32,
359    uint64_t addr64);
360extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
361    msiqid_t *msiq_id);
362extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
363    msiqid_t msiq_id);
364extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
365    pci_msi_valid_state_t *msi_valid_state);
366extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
367    pci_msi_valid_state_t msi_valid_state);
368extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
369    pci_msi_state_t *msi_state);
370extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
371    pci_msi_state_t msi_state);
372
373/*
374 * MSG Functions:
375 */
376extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
377    msiqid_t *msiq_id);
378extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
379    msiqid_t msiq_id);
380extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
381    pcie_msg_valid_state_t *msg_valid_state);
382extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
383    pcie_msg_valid_state_t msg_valid_state);
384
385/*
386 * Suspend/Resume Functions:
387 */
388extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
389extern void hvio_resume(devhandle_t dev_hdl,
390    devino_t devino, pxu_t *pxu_p);
391extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
392extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl,
393    devino_t devino, pxu_t *pxu_p);
394extern int px_send_pme_turnoff(caddr_t csr_base);
395extern int px_link_wait4l1idle(caddr_t csr_base);
396extern int px_link_retrain(caddr_t csr_base);
397extern void px_enable_detect_quiet(caddr_t csr_base);
398
399extern void px_lib_clr_errs(px_t *px_p, dev_info_t *rdip, uint64_t addr);
400
401/*
402 * Hotplug functions:
403 */
404extern int hvio_hotplug_init(dev_info_t *dip, void *arg);
405extern int hvio_hotplug_uninit(dev_info_t *dip);
406
407#ifdef	__cplusplus
408}
409#endif
410
411#endif	/* _SYS_PX_LIB4U_H */
412