1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, Version 1.0 only
6 * (the "License").  You may not use this file except in compliance
7 * with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22/*
23 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#pragma ident	"%Z%%M%	%I%	%E% SMI"
28
29/*
30 * PCI Streaming Cache operations: initialization and configuration
31 */
32
33#include <sys/types.h>
34#include <sys/kmem.h>
35#include <vm/seg_kmem.h>
36#include <sys/async.h>
37#include <sys/spl.h>
38#include <sys/sunddi.h>
39#include <sys/ddi_impldefs.h>
40#include <sys/pci/pci_obj.h>
41#include <sys/x_call.h>		/* XCALL_PIL */
42
43/*LINTLIBRARY*/
44
45void
46sc_create(pci_t *pci_p)
47{
48	dev_info_t *dip = pci_p->pci_dip;
49	sc_t *sc_p;
50	uint64_t paddr;
51
52#ifdef lint
53	dip = dip;
54#endif
55
56	if (!pci_stream_buf_exists)
57		return;
58
59	/*
60	 * Allocate streaming cache state structure and link it to
61	 * the pci state structure.
62	 */
63	sc_p = (sc_t *)kmem_zalloc(sizeof (sc_t), KM_SLEEP);
64	pci_p->pci_sc_p = sc_p;
65	sc_p->sc_pci_p = pci_p;
66
67	pci_sc_setup(sc_p);
68	sc_p->sc_sync_reg_pa = va_to_pa((char *)sc_p->sc_sync_reg);
69
70	DEBUG3(DBG_ATTACH, dip, "sc_create: ctrl=%x, invl=%x, sync=%x\n",
71		sc_p->sc_ctrl_reg, sc_p->sc_invl_reg,
72		sc_p->sc_sync_reg);
73	DEBUG2(DBG_ATTACH, dip, "sc_create: ctx_invl=%x ctx_match=%x\n",
74		sc_p->sc_ctx_invl_reg, sc_p->sc_ctx_match_reg);
75	DEBUG3(DBG_ATTACH, dip,
76		"sc_create: data_diag=%x, tag_diag=%x, ltag_diag=%x\n",
77		sc_p->sc_data_diag_acc, sc_p->sc_tag_diag_acc,
78		sc_p->sc_ltag_diag_acc);
79
80	/*
81	 * Allocate the flush/sync buffer.  Make sure it's properly
82	 * aligned.
83	 */
84	sc_p->sc_sync_flag_base =
85	    vmem_xalloc(static_alloc_arena, PCI_SYNC_FLAG_SIZE,
86		PCI_SYNC_FLAG_SIZE, 0, 0, NULL, NULL, VM_SLEEP);
87	sc_p->sc_sync_flag_vaddr = (uint64_t *)sc_p->sc_sync_flag_base;
88	paddr = (uint64_t)hat_getpfnum(kas.a_hat,
89	    (caddr_t)sc_p->sc_sync_flag_vaddr);
90	paddr <<= MMU_PAGESHIFT;
91	paddr += (uint64_t)
92	    ((uintptr_t)sc_p->sc_sync_flag_vaddr & ~MMU_PAGEMASK);
93	sc_p->sc_sync_flag_pa = paddr;
94	DEBUG2(DBG_ATTACH, dip, "sc_create: sync buffer - vaddr=%x paddr=%x\n",
95	    sc_p->sc_sync_flag_vaddr, sc_p->sc_sync_flag_pa);
96
97	/*
98	 * Create a mutex to go along with it.  While the mutex is held,
99	 * all interrupts should be blocked.  This will prevent driver
100	 * interrupt routines from attempting to acquire the mutex while
101	 * held by a lower priority interrupt routine.  Note also that
102	 * we now block cross calls as well, to prevent issues with
103	 * relocation.
104	 */
105	mutex_init(&sc_p->sc_sync_mutex, NULL, MUTEX_DRIVER,
106	    (void *)ipltospl(XCALL_PIL));
107
108	sc_configure(sc_p);
109}
110
111void
112sc_destroy(pci_t *pci_p)
113{
114	sc_t *sc_p;
115
116	if (!pci_stream_buf_exists)
117		return;
118
119	sc_p = pci_p->pci_sc_p;
120
121	DEBUG0(DBG_DETACH, pci_p->pci_dip, "sc_destroy:\n");
122
123	vmem_xfree(static_alloc_arena, sc_p->sc_sync_flag_base,
124	    PCI_SYNC_FLAG_SIZE);
125
126	/*
127	 * Free the streaming cache state structure.
128	 */
129	kmem_free(sc_p, sizeof (sc_t));
130	pci_p->pci_sc_p = NULL;
131}
132
133void
134sc_configure(sc_t *sc_p)
135{
136	int i, instance;
137	uint64_t l;
138	dev_info_t *dip;
139
140	if (!sc_p)
141		return;
142
143	dip = sc_p->sc_pci_p->pci_dip;
144
145	/*
146	 * Invalidate all streaming cache entries via the diagnostic
147	 * access registers.
148	 */
149	DEBUG0(DBG_ATTACH, dip, "sc_configure:\n");
150	*sc_p->sc_ctrl_reg |= COMMON_SC_CTRL_DIAG_ENABLE;
151	for (i = 0; i < PCI_SBUF_ENTRIES; i++) {
152		sc_p->sc_tag_diag_acc[i] = 0x0ull;
153		sc_p->sc_ltag_diag_acc[i] = 0x0ull;
154	}
155
156	/*
157	 * Configure the streaming cache:
158	 */
159	l = 0;
160	instance = ddi_get_instance(dip);
161	if (pci_stream_buf_enable & (1 << instance))
162		l |= COMMON_SC_CTRL_ENABLE;
163	if (pci_rerun_disable & (1 << instance))
164		l |= COMMON_SC_CTRL_RR__DISABLE;
165	if (pci_lock_sbuf & (1 << instance))
166		l |= COMMON_SC_CTRL_LRU_LE;
167
168	/*
169	 * Get any SC configuration changes specific to the chip.
170	 */
171	l |= pci_sc_configure(sc_p->sc_pci_p);
172
173	DEBUG1(DBG_ATTACH, dip,
174	    "sc_configure: writing %x to sc csr\n", l);
175	*sc_p->sc_ctrl_reg = l;
176}
177