1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#pragma ident	"%Z%%M%	%I%	%E% SMI"
27
28#include <sys/types.h>
29#include <sys/sunddi.h>
30#include <sys/sunndi.h>
31#include <sys/ddi_impldefs.h>
32#include <sys/async.h>
33#include <sys/membar.h>
34#include <sys/spl.h>
35#include <sys/iommu.h>
36#include <sys/pci/pci_obj.h>
37#include <sys/fm/util.h>
38#include <sys/fm/io/pci.h>
39#include <sys/fm/io/ddi.h>
40#include <sys/fm/io/sun4upci.h>
41#include <sys/fm/protocol.h>
42#include <sys/intr.h>
43
44/*LINTLIBRARY*/
45
46/*
47 * The routines below are generic sun4u PCI interfaces to support
48 * Fault Management.
49 *
50 * pci_dma_check, pci_acc_check, pci_handle_lookup are functions used
51 * to associate a captured PCI address to a particular dma/acc handle.
52 *
53 * pci_fm_acc_setup, pci_fm_init_child, pci_fm_create,
54 * pci_fm_destroy are constructors/destructors used to setup and teardown
55 * necessary resources.
56 *
57 * pci_bus_enter, pci_bus_exit are registered via busops and are used to
58 * provide exclusive access to the PCI bus.
59 *
60 * pci_err_callback is the registered callback for PCI which is called
61 * by the CPU code when it detects a UE/TO/BERR.
62 *
63 * pbm_ereport_post is used by the PBM code to generically report all
64 * PBM errors.
65 *
66 */
67
68/*
69 * Function used to setup access functions depending on level of desired
70 * protection.
71 */
72void
73pci_fm_acc_setup(ddi_map_req_t *mp, dev_info_t *rdip)
74{
75	uchar_t fflag;
76	ddi_acc_hdl_t *hp;
77	ddi_acc_impl_t *ap;
78
79	hp = mp->map_handlep;
80	ap = (ddi_acc_impl_t *)hp->ah_platform_private;
81	fflag = ap->ahi_common.ah_acc.devacc_attr_access;
82
83	if (mp->map_op == DDI_MO_MAP_LOCKED) {
84		ndi_fmc_insert(rdip, ACC_HANDLE, (void *)hp, NULL);
85		switch (fflag) {
86		case DDI_FLAGERR_ACC:
87			ap->ahi_get8 = i_ddi_prot_get8;
88			ap->ahi_get16 = i_ddi_prot_get16;
89			ap->ahi_get32 = i_ddi_prot_get32;
90			ap->ahi_get64 = i_ddi_prot_get64;
91			ap->ahi_put8 = i_ddi_prot_put8;
92			ap->ahi_put16 = i_ddi_prot_put16;
93			ap->ahi_put32 = i_ddi_prot_put32;
94			ap->ahi_put64 = i_ddi_prot_put64;
95			ap->ahi_rep_get8 = i_ddi_prot_rep_get8;
96			ap->ahi_rep_get16 = i_ddi_prot_rep_get16;
97			ap->ahi_rep_get32 = i_ddi_prot_rep_get32;
98			ap->ahi_rep_get64 = i_ddi_prot_rep_get64;
99			ap->ahi_rep_put8 = i_ddi_prot_rep_put8;
100			ap->ahi_rep_put16 = i_ddi_prot_rep_put16;
101			ap->ahi_rep_put32 = i_ddi_prot_rep_put32;
102			ap->ahi_rep_put64 = i_ddi_prot_rep_put64;
103			break;
104		case DDI_CAUTIOUS_ACC :
105			ap->ahi_get8 = i_ddi_caut_get8;
106			ap->ahi_get16 = i_ddi_caut_get16;
107			ap->ahi_get32 = i_ddi_caut_get32;
108			ap->ahi_get64 = i_ddi_caut_get64;
109			ap->ahi_put8 = i_ddi_caut_put8;
110			ap->ahi_put16 = i_ddi_caut_put16;
111			ap->ahi_put32 = i_ddi_caut_put32;
112			ap->ahi_put64 = i_ddi_caut_put64;
113			ap->ahi_rep_get8 = i_ddi_caut_rep_get8;
114			ap->ahi_rep_get16 = i_ddi_caut_rep_get16;
115			ap->ahi_rep_get32 = i_ddi_caut_rep_get32;
116			ap->ahi_rep_get64 = i_ddi_caut_rep_get64;
117			ap->ahi_rep_put8 = i_ddi_caut_rep_put8;
118			ap->ahi_rep_put16 = i_ddi_caut_rep_put16;
119			ap->ahi_rep_put32 = i_ddi_caut_rep_put32;
120			ap->ahi_rep_put64 = i_ddi_caut_rep_put64;
121			break;
122		default:
123			break;
124		}
125	} else if (mp->map_op == DDI_MO_UNMAP) {
126		ndi_fmc_remove(rdip, ACC_HANDLE, (void *)hp);
127	}
128}
129
130/*
131 * Function used to initialize FMA for our children nodes. Called
132 * through pci busops when child node calls ddi_fm_init.
133 */
134/* ARGSUSED */
135int
136pci_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
137    ddi_iblock_cookie_t *ibc)
138{
139	pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
140
141	ASSERT(ibc != NULL);
142	*ibc = pci_p->pci_fm_ibc;
143
144	return (pci_p->pci_fm_cap);
145}
146
147/*
148 * Lock accesses to the pci bus, to be able to protect against bus errors.
149 */
150void
151pci_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle)
152{
153	pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
154	pbm_t *pbm_p = pci_p->pci_pbm_p;
155
156	membar_sync();
157
158	mutex_enter(&pbm_p->pbm_pokefault_mutex);
159	pbm_p->pbm_excl_handle = handle;
160}
161
162/*
163 * Unlock access to bus and clear errors before exiting.
164 */
165/* ARGSUSED */
166void
167pci_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle)
168{
169	pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip));
170	pbm_t *pbm_p = pci_p->pci_pbm_p;
171	ddi_fm_error_t derr;
172
173	ASSERT(MUTEX_HELD(&pbm_p->pbm_pokefault_mutex));
174
175	membar_sync();
176
177	mutex_enter(&pci_p->pci_common_p->pci_fm_mutex);
178	ddi_fm_acc_err_get(pbm_p->pbm_excl_handle, &derr, DDI_FME_VERSION);
179
180	if (derr.fme_status == DDI_FM_OK) {
181		if (pci_check_error(pci_p) != 0) {
182			(void) pci_pbm_err_handler(pci_p->pci_dip, &derr,
183					(const void *)pci_p, PCI_BUS_EXIT_CALL);
184		}
185	}
186	mutex_exit(&pci_p->pci_common_p->pci_fm_mutex);
187
188	pbm_p->pbm_excl_handle = NULL;
189	mutex_exit(&pbm_p->pbm_pokefault_mutex);
190}
191
192/*
193 * PCI error callback which is registered with our parent to call
194 * for PCI logging when the CPU traps due to BERR/TO/UE.
195 */
196int
197pci_err_callback(dev_info_t *dip, ddi_fm_error_t *derr,
198    const void *impl_data)
199{
200	pci_t *pci_p = (pci_t *)impl_data;
201	pci_common_t *cmn_p = pci_p->pci_common_p;
202	ecc_t *ecc_p = cmn_p->pci_common_ecc_p;
203	ecc_errstate_t ecc_err;
204	int fatal = 0;
205	int nonfatal = 0;
206	int unknown = 0;
207	int ret = DDI_FM_OK;
208
209	bzero(&ecc_err, sizeof (ecc_err));
210	mutex_enter(&cmn_p->pci_fm_mutex);
211	/*
212	 * Check and log ecc and pbm errors
213	 */
214	ecc_err.ecc_ii_p = ecc_p->ecc_ue;
215	ecc_err.ecc_ena = derr->fme_ena;
216	ecc_err.ecc_caller = PCI_TRAP_CALL;
217
218	if ((ret = ecc_err_handler(&ecc_err)) == DDI_FM_FATAL)
219		fatal++;
220	else if (ret == DDI_FM_NONFATAL)
221		nonfatal++;
222	else if (ret == DDI_FM_UNKNOWN)
223		unknown++;
224
225	if (pci_check_error(pci_p) != 0) {
226		int err = pci_pbm_err_handler(pci_p->pci_dip, derr,
227				(const void *)pci_p, PCI_TRAP_CALL);
228		if (err == DDI_FM_FATAL)
229			fatal++;
230		else if (err == DDI_FM_NONFATAL)
231			nonfatal++;
232		else if (err == DDI_FM_UNKNOWN)
233			unknown++;
234	}
235
236	mutex_exit(&cmn_p->pci_fm_mutex);
237
238	if (fatal)
239		return (DDI_FM_FATAL);
240	else if (nonfatal)
241		return (DDI_FM_NONFATAL);
242	else if (unknown)
243		return (DDI_FM_UNKNOWN);
244	else
245		return (DDI_FM_OK);
246}
247
248void
249pci_fm_create(pci_t *pci_p)
250{
251	pci_common_t *cmn_p = pci_p->pci_common_p;
252
253	/*
254	 * PCI detected ECC errorq, to schedule async handling
255	 * of ECC errors and logging.
256	 * The errorq is created here but destroyed when _fini is called
257	 * for the pci module.
258	 */
259	if (pci_ecc_queue == NULL) {
260		pci_ecc_queue = errorq_create("pci_ecc_queue",
261				(errorq_func_t)ecc_err_drain,
262				(void *)pci_p->pci_ecc_p,
263				ECC_MAX_ERRS, sizeof (ecc_errstate_t),
264				PIL_2, ERRORQ_VITAL);
265		if (pci_ecc_queue == NULL)
266			panic("failed to create required system error queue");
267	}
268
269	/*
270	 * Initialize pci_target_queue for FMA handling of pci errors.
271	 */
272	pci_targetq_init();
273
274	/*
275	 * Initialize FMA support
276	 * The axq workaround prevents fault management of access errors
277	 */
278	if (pci_p->pci_pbm_p->pbm_pio_limit == 0)
279		pci_p->pci_fm_cap = DDI_FM_EREPORT_CAPABLE |
280			DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE |
281			DDI_FM_ERRCB_CAPABLE;
282	else
283		pci_p->pci_fm_cap = DDI_FM_EREPORT_CAPABLE |
284			DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE;
285	/*
286	 * Call parent to get it's capablity
287	 */
288	ddi_fm_init(pci_p->pci_dip, &pci_p->pci_fm_cap,
289			&pci_p->pci_fm_ibc);
290	/*
291	 * Need to be ereport and error handler cabable
292	 */
293	ASSERT((pci_p->pci_fm_cap & DDI_FM_ERRCB_CAPABLE) &&
294	    (pci_p->pci_fm_cap & DDI_FM_EREPORT_CAPABLE));
295	/*
296	 * Initialize error handling mutex.
297	 */
298	if (cmn_p->pci_common_refcnt == 0) {
299		mutex_init(&cmn_p->pci_fm_mutex, NULL, MUTEX_DRIVER,
300				(void *)pci_p->pci_fm_ibc);
301	}
302
303	/*
304	 * Register error callback with our parent.
305	 */
306	ddi_fm_handler_register(pci_p->pci_dip, pci_err_callback,
307			pci_p);
308
309}
310
311void
312pci_fm_destroy(pci_t *pci_p)
313{
314	pci_common_t *cmn_p = pci_p->pci_common_p;
315
316	/* schizo non-shared objects */
317	ddi_fm_handler_unregister(pci_p->pci_dip);
318	ddi_fm_fini(pci_p->pci_dip);
319
320	if (cmn_p->pci_common_refcnt != 0)
321		return;
322
323	mutex_destroy(&cmn_p->pci_fm_mutex);
324}
325
326/*
327 * Function used to post PCI block module specific ereports.
328 */
329void
330pbm_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err)
331{
332	char buf[FM_MAX_CLASS];
333
334	(void) snprintf(buf, FM_MAX_CLASS, "%s.%s",
335	    pbm_err->pbm_bridge_type, pbm_err->pbm_err_class);
336
337	ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1);
338
339	ddi_fm_ereport_post(dip, buf, ena, DDI_NOSLEEP,
340	    FM_VERSION, DATA_TYPE_UINT8, 0,
341	    PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat,
342	    PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm,
343	    PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat,
344	    PCI_PBM_AFSR, DATA_TYPE_UINT64, pbm_err->pbm_afsr,
345	    PCI_PBM_AFAR, DATA_TYPE_UINT64, pbm_err->pbm_afar,
346	    PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl,
347	    PCI_PBM_VALOG, DATA_TYPE_UINT64, pbm_err->pbm_va_log,
348	    NULL);
349}
350