px_ioapi.h revision 9707:ef822325a809
138494Sobrien/* 238494Sobrien * CDDL HEADER START 338494Sobrien * 438494Sobrien * The contents of this file are subject to the terms of the 538494Sobrien * Common Development and Distribution License (the "License"). 638494Sobrien * You may not use this file except in compliance with the License. 738494Sobrien * 838494Sobrien * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 938494Sobrien * or http://www.opensolaris.org/os/licensing. 1038494Sobrien * See the License for the specific language governing permissions 1138494Sobrien * and limitations under the License. 1238494Sobrien * 1338494Sobrien * When distributing Covered Code, include this CDDL HEADER in each 1438494Sobrien * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1538494Sobrien * If applicable, add the following below this CDDL HEADER, with the 1638494Sobrien * fields enclosed by brackets "[]" replaced with your own identifying 1738494Sobrien * information: Portions Copyright [yyyy] [name of copyright owner] 1838494Sobrien * 1938494Sobrien * CDDL HEADER END 2038494Sobrien */ 2138494Sobrien/* 2238494Sobrien * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 2338494Sobrien * Use is subject to license terms. 2438494Sobrien */ 2538494Sobrien 2638494Sobrien#ifndef _SYS_PX_IOAPI_H 2738494Sobrien#define _SYS_PX_IOAPI_H 2838494Sobrien 2938494Sobrien#ifdef __cplusplus 3038494Sobrienextern "C" { 3138494Sobrien#endif 3238494Sobrien 3338494Sobrien#ifndef _ASM 3438494Sobrien 3538494Sobrien/* 3638494Sobrien * SUN4V IO Data Definitions 3738494Sobrien * 3838494Sobrien * cpuid - A unique opaque value which represents a target cpu. 3938494Sobrien * 4038494Sobrien * devhandle - Device handle. The device handle uniquely 4141145Sobrien * identifies a SUN4V device. It consists of the 4238494Sobrien * the lower 28-bits of the hi-cell of the first 4338494Sobrien * entry of the SUN4V device's "reg" property as defined 4438494Sobrien * by the SUN4V Bus Binding to Open Firmware. 4538494Sobrien * 4638494Sobrien * devino - Device Interrupt Number. An unsigned integer representing 4738494Sobrien * an interrupt within a specific device. 4838494Sobrien * 4938494Sobrien * sysino - System Interrupt Number. A 64-bit unsigned integer 5038494Sobrien * representing a unique interrupt within a "system". 5138494Sobrien * 5238494Sobrien * intr_state - A flag representing the interrupt state for a 5338494Sobrien * a given sysino. The state values are defined as: 5438494Sobrien * 5538494Sobrien * INTR_IDLE 0 5638494Sobrien * INTR_RECEIVED 1 5738494Sobrien * INTR_DELIVERED 2 5838494Sobrien * 5938494Sobrien * intr_valid_state - A flag representing the 'valid' state for 6041145Sobrien * a given sysino. The state values are defined as: 6141145Sobrien * 6238494Sobrien * INTR_NOTVALID 0 sysino not enabled 6338494Sobrien * INTR_VALID 1 sysino enabled 6438494Sobrien */ 6538494Sobrien 6638494Sobrientypedef uint64_t devhandle_t; 6738494Sobrien 6838494Sobrientypedef uint32_t cpuid_t; 6938494Sobrientypedef uint32_t devino_t; 7038494Sobrientypedef uint64_t sysino_t; 7138494Sobrien 7238494Sobrientypedef enum intr_state { 7338494Sobrien INTR_IDLE_STATE = (uint32_t)0, 7438494Sobrien INTR_RECEIVED_STATE = (uint32_t)1, 7538494Sobrien INTR_DELIVERED_STATE = (uint32_t)2 7638494Sobrien} intr_state_t; 7738494Sobrien 7838494Sobrientypedef enum intr_valid_state { 7938494Sobrien INTR_NOTVALID = (uint32_t)0, 8038494Sobrien INTR_VALID = (uint32_t)1 8138494Sobrien} intr_valid_state_t; 8238494Sobrien 8338494Sobrien/* 8438494Sobrien * PCI IO Data Definitions 8538494Sobrien * 8638494Sobrien * tsbnum - TSB Number. Identifies which io-tsb is used. 8738494Sobrien * For this version of the spec, tsbnum must be zero. 8838494Sobrien * 8938494Sobrien * tsbindex - TSB Index. Identifies which entry in the tsb is 9038494Sobrien * is used. The first entry is zero. 9138494Sobrien * 9238494Sobrien * tsbid - A 64-bit aligned data structure which contains 9338494Sobrien * a tsbnum and a tsbindex. 9438494Sobrien * bits 63:32 contain the tsbnum. 9538494Sobrien * bits 31:00 contain the tsbindex. 9638494Sobrien * 9738494Sobrien * io_attributes - IO Attributes for iommu mappings. 9838494Sobrien * Attributes for iommu mappings. One or more of the 9938494Sobrien * following attribute bits stored in a 64-bit unsigned int. 10038494Sobrien * 10138494Sobrien * 6 3 0 10238494Sobrien * 3 1 0 10338494Sobrien * 00000000 00000000 00000000 00000000 BBBBBBBB DDDDDFFF 00000000 00PP0LWR 10438494Sobrien * 10538494Sobrien * R: DMA data is transferred from main memory to device. 10638494Sobrien * W: DMA data is transferred from device to main memory. 10738494Sobrien * L: Requested DMA transaction can be relaxed ordered within RC. 10838494Sobrien * P: Value of PCI Express and PCI-X phantom function 10938494Sobrien * configuration. Its encoding is identical to the 11038494Sobrien * "Phantom Function Supported" field of the 11138494Sobrien * "Device Capabilities Register (offset 0x4)" 11238494Sobrien * in the "PCI Express Capability Structure". 11338494Sobrien * The structure is part of a device's config space. 11438494Sobrien * BDF: Bus, device and function number of the device 11538494Sobrien * that is going to issue DMA transactions. 11638494Sobrien * The BDF values are used to guarantee the mapping 11738494Sobrien * only be accessed by the specified device. 11838494Sobrien * If the BDF is set to all 0, RID based protection 11938494Sobrien * will be turned off. 12038494Sobrien * 12138494Sobrien * Relaxed Ordering (L) is advisory. Not all hardware implements a 12238494Sobrien * relaxed ordering attribute. If L attribute is not implemented in 12338494Sobrien * hardware, the implementation is permitted to ignore the L bit. 12438494Sobrien * 12538494Sobrien * Bits 3, 15:6 and 63:32 are unused and must be set to zero for 12638494Sobrien * this version of the specification. 12738494Sobrien * 12838494Sobrien * Note: For compatibility with future versions of this 12938494Sobrien * specification, the caller must set bits 3, 15:6 and 63:32 to 13038494Sobrien * zero. The implementation shall ignore these bits. 13138494Sobrien * 13238494Sobrien * r_addr - 64-bit Real Address. 13338494Sobrien * 13438494Sobrien * io_addr - 64-bit IO Address. 13538494Sobrien * 13638494Sobrien * pci_device - PCI device address. A PCI device address 13738494Sobrien * identifies a specific device on a specific PCI 13838494Sobrien * bus segment. A PCI device address is a 32-bit unsigned 13938494Sobrien * integer with the following format: 14038494Sobrien * 14138494Sobrien * 00000000.bbbbbbbb.dddddfff.00000000 14238494Sobrien * 14338494Sobrien * Where: 14438494Sobrien * 14538494Sobrien * bbbbbbbb is the 8-bit pci bus number 14638494Sobrien * ddddd is the 5-bit pci device number 14738494Sobrien * fff is the 3-bit pci function number 14838494Sobrien * 14938494Sobrien * 00000000 is the 8-bit literal zero. 15038494Sobrien * 15138494Sobrien * pci_config_offset - PCI Configuration Space offset. 15238494Sobrien * 15338494Sobrien * For conventional PCI, an unsigned integer in the range 15438494Sobrien * 0 .. 255 representing the offset of the field in pci config 15538494Sobrien * space. 15638494Sobrien * 15738494Sobrien * For PCI implementations with extended configuration space, 15838494Sobrien * an unsigned integer in the range 0 .. 4095, representing 15938494Sobrien * the offset of the field in configuration space. Conventional 16038494Sobrien * PCI config space is offset 0 .. 255. Extended config space 16138494Sobrien * is offset 256 .. 4095 16238494Sobrien * 16338494Sobrien * Note: For pci config space accesses, the offset must be 'size' 16438494Sobrien * aligned. 16538494Sobrien * 16638494Sobrien * error_flag - Error flag 16738494Sobrien * 16838494Sobrien * A return value specifies if the action succeeded 16938494Sobrien * or failed, where: 17038494Sobrien * 17138494Sobrien * 0 - No error occurred while performing the service. 17238494Sobrien * non-zero - Error occurred while performing the service. 17338494Sobrien * 17438494Sobrien * io_sync_direction - "direction" definition for pci_dma_sync 17538494Sobrien * 17638494Sobrien * A value specifying the direction for a memory/io sync 17738494Sobrien * operation, The direction value is a flag, one or both 17838494Sobrien * directions may be specified by the caller. 17938494Sobrien * 18038494Sobrien * 0x01 - For device (device read from memory) 18138494Sobrien * 0x02 - For cpu (device write to memory) 18238494Sobrien * 18338494Sobrien * io_page_list - A list of io_page_addresses. An io_page_address 18438494Sobrien * is an r_addr. 18538494Sobrien * 18638494Sobrien * io_page_list_p - A pointer to an io_page_list. 18738494Sobrien */ 18838494Sobrientypedef uint32_t tsbnum_t; 18938494Sobrientypedef uint32_t tsbindex_t; 19038494Sobrientypedef uint64_t tsbid_t; 19138494Sobrientypedef uint64_t r_addr_t; 19238494Sobrientypedef uint64_t io_addr_t; 19338494Sobrientypedef uint64_t io_page_list_t; 19438494Sobrientypedef uint32_t pages_t; 19538494Sobrientypedef uint32_t error_flag_t; 19638494Sobrien 19738494Sobrientypedef uint32_t pci_config_offset_t; 19838494Sobrientypedef uint64_t pci_device_t; 19938494Sobrien 20038494Sobrien#define PCI_TSB_INDEX 0 20138494Sobrien#define PCI_TSB_INDEX_MASK 0xFFFFFFFF 20238494Sobrien#define PCI_TSB_NUM 32 20338494Sobrien#define PCI_TSB_NUM_MASK 0xFFFFFFFF 20438494Sobrien 20538494Sobrien#define PCI_TSBID(tsbnum, tsbindex) \ 20638494Sobrien ((((tsbid_t)tsbnum & PCI_TSB_NUM_MASK) << PCI_TSB_NUM) | \ 20738494Sobrien (((tsbid_t)tsbindex & PCI_TSB_INDEX_MASK) << PCI_TSB_INDEX)) 20838494Sobrien 20938494Sobrien#define PCI_TSBID_TO_TSBNUM(tsbid) \ 21038494Sobrien ((tsbid >> PCI_TSB_NUM) & PCI_TSB_NUM_MASK) 21138494Sobrien 21238494Sobrien#define PCI_TSBID_TO_TSBINDEX(tsbid) \ 21338494Sobrien ((tsbid >> PCI_TSB_INDEX) & PCI_TSB_INDEX_MASK) 21438494Sobrien 21538494Sobrientypedef uint64_t io_attributes_t; 21638494Sobrien 21738494Sobrien#define PCI_MAP_ATTR_READ 0x1ull 21838494Sobrien#define PCI_MAP_ATTR_WRITE 0x2ull 21938494Sobrien#define PCI_MAP_ATTR_RO 0x4ull 22038494Sobrien 22138494Sobrien#define PCI_MAP_ATTR_PHFUN 4 22238494Sobrien#define PCI_MAP_ATTR_BDF 16 22338494Sobrien 22438494Sobrien#define PCI_MAP_ATTR_PHFUN_MASK 0x30 22538494Sobrien#define PCI_MAP_ATTR_BDF_MASK 0xffff0000 22638494Sobrien 22738494Sobrien#define PX_ADD_ATTR_EXTNS(attr, bdf) \ 22838494Sobrien (attr | (bdf << PCI_MAP_ATTR_BDF)) 22938494Sobrien 23038494Sobrientypedef enum io_sync_direction { 23138494Sobrien IO_SYNC_DEVICE = (uint32_t)0x01, 23238494Sobrien IO_SYNC_CPU = (uint32_t)0x02 23338494Sobrien} io_sync_direction_t; 23438494Sobrien 23538494Sobrientypedef enum pci_config_size { 23638494Sobrien PCI_CFG_SIZE_BYTE = 0, 23738494Sobrien PCI_CFG_SIZE_WORD, 23838494Sobrien PCI_CFG_SIZE_DWORD 23938494Sobrien} pci_config_size_t; 24038494Sobrien 24138494Sobrientypedef union pci_cfg_data { 24238494Sobrien uint8_t b; 24338494Sobrien uint16_t w; 24438494Sobrien uint32_t dw; 24538494Sobrien uint64_t qw; 24638494Sobrien} pci_cfg_data_t; 24738494Sobrien 24838494Sobrien/* 24938494Sobrien * MSI Definitions 25038494Sobrien * 25138494Sobrien * MSI - Message Signaled Interrupt 25238494Sobrien * 25338494Sobrien * Message Signaled Interrupt as defined in the PCI Local Bus 25438494Sobrien * Specification and the PCI Express Base Specification. 25538494Sobrien * A device signals an interrupt via MSI using a posted 25638494Sobrien * write cycle to an address specified by system software 25738494Sobrien * using a data value specified by system software. 25838494Sobrien * The MSI capability data structure contains fields for 25938494Sobrien * the PCI address and data values the device uses when 26038494Sobrien * sending an MSI message on the bus. MSI-X is an extended 26138494Sobrien * form of MSI, but uses the same mechanism for signaling 26238494Sobrien * the interrupt as MSI. For the purposes of this document, 26338494Sobrien * the term "MSI" refers to MSI or MSI-X. 26438494Sobrien * 26538494Sobrien * Root complexes that support MSI define an address range 26638494Sobrien * and set of data values that can be used to signal MSIs. 26738494Sobrien * 26838494Sobrien * SUN4V/pci requirements for MSI: 26938494Sobrien * 27038494Sobrien * The root complex defines two address ranges. One in 27138494Sobrien * the 32-bit pci memory space and one in the 64-bit 27238494Sobrien * pci memory address space used as the target of a posted 27338494Sobrien * write to signal an MSI. 27438494Sobrien * 27538494Sobrien * The root complex treats any write to these address 27638494Sobrien * ranges as signaling an MSI, however, only the data 27738494Sobrien * value used in the posted write signals the MSI. 27838494Sobrien * 27938494Sobrien * 28038494Sobrien * MSI EQ - MSI Event Queue 28138494Sobrien * 28238494Sobrien * The MSI Event Queue is a page-aligned main memory data 28338494Sobrien * structure used to store MSI data records. 28438494Sobrien * 28538494Sobrien * Each root port supports several MSI EQs, and each EQ has a 28638494Sobrien * system interrupt associated with it, and can be targeted 28738494Sobrien * (individually) to any cpu. The number of MSI EQs supported 28838494Sobrien * by a root complex is described by a property defined in [3]. 28938494Sobrien * Each MSI EQ must be large enough to contain all possible MSI 29038494Sobrien * data records generated by any one PCI root port. The number 29138494Sobrien * of entries in each MSI EQ is described by a property defined 29238494Sobrien * in [3]. 29338494Sobrien * 29438494Sobrien * Each MSI EQ is compliant with the definition of interrupt 29538494Sobrien * queues described in [5], however, instead of accessing the 29638494Sobrien * queue head/tail registers via ASI-based registers, an API 29738494Sobrien * is provided to access the head/tail registers. 29838494Sobrien * 29938494Sobrien * The SUN4V/pci compliant root complex has the ability to 30038494Sobrien * generate a system interrupt when the MSI EQ is non-empty. 30138494Sobrien * 30238494Sobrien * MSI/Message/INTx Data Record format 30338494Sobrien * 30438494Sobrien * Each data record consists of 64 bytes of data, aligned 30538494Sobrien * on a 64-byte boundary. 30638494Sobrien * 30738494Sobrien * The data record is defined as follows: 30838494Sobrien * 30938494Sobrien * 31038494Sobrien * 6666555555555544444444443333333333222222222211111111110000000000 31138494Sobrien * 3210987654321098765432109876543210987654321098765432109876543210 31238494Sobrien * 31338494Sobrien * 0x00: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVxxxxxxxxxxxxxxxxxxxxxxxxTTTTTTTT 31438494Sobrien * 0x08: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 31538494Sobrien * 0x10: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31638494Sobrien * 0x18: SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 31738494Sobrien * 0x20: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxRRRRRRRRRRRRRRRR 31838494Sobrien * 0x28: AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 31938494Sobrien * 0x30: DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 32038494Sobrien * 0x38: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 32138494Sobrien * 32238494Sobrien * Where, 32338494Sobrien * 32438494Sobrien * xx..xx are unused bits and must be ignored by sw. 32538494Sobrien * 32638494Sobrien * VV..VV is the version number of this data record 32738494Sobrien * 32838494Sobrien * For this release of the spec, the version number 32938494Sobrien * field must be zero. 33038494Sobrien * 33138494Sobrien * TTTTTTTT is the data record type: 33238494Sobrien * 33338494Sobrien * Upper 4 bits are reserved, and must be zero 33438494Sobrien * 33538494Sobrien * 0000 - Not an MSI data record - reserved for sw use. 33638494Sobrien * 0001 - MSG 33738494Sobrien * 0010 - MSI32 33838494Sobrien * 0011 - MSI64 33938494Sobrien * 0010 - Reserved 34038494Sobrien * ... 34138494Sobrien * 0111 - Reserved 34238494Sobrien * 1000 - INTx 34338494Sobrien * 1001 - Reserved 34438494Sobrien * ... 34538494Sobrien * 1110 - Reserved 34638494Sobrien * 1111 - Not an MSI data record - reserved for sw use. 34738494Sobrien * 34838494Sobrien * All other encodings are reserved. 34938494Sobrien * 35038494Sobrien * II..II is the sysino for INTx (sw defined value), 35138494Sobrien * otherwise zero. 35238500Sobrien * 35338494Sobrien * SS..SS is the message timestamp if available. 35438494Sobrien * If supported by the implementation, a non-zero 35538494Sobrien * value in this field is a copy of the %stick register 35638494Sobrien * at the time the message is created. 35738494Sobrien * 35838494Sobrien * If unsupported, this field will contain zero. 35938494Sobrien * 36038494Sobrien * RR..RR is the requester ID of the device that initiated the MSI/MSG 36138494Sobrien * and has the following format: 36238494Sobrien * 36338494Sobrien * bbbbbbbb.dddddfff 36438494Sobrien * 36538494Sobrien * Where bb..bb is the bus number, 36638494Sobrien * dd..dd is the device number 36738494Sobrien * and fff is the function number. 36838494Sobrien * 36938494Sobrien * Note that for PCI devices or any message where 37038494Sobrien * the requester is unknown, this may be zero, 37138494Sobrien * or the device-id of an intermediate bridge. 37238494Sobrien * 37338494Sobrien * For intx messages, this field should be ignored. 37438494Sobrien * 37538494Sobrien * AA..AA is the MSI address. For MSI32, the upper 32-bits must be zero. 37638494Sobrien * (for data record type MSG or INTx, this field is ignored) 37738494Sobrien * 37838494Sobrien * DD..DD is the MSI/MSG data or INTx number 37938494Sobrien * 38038494Sobrien * For MSI-X, bits 31..0 contain the data from the MSI packet 38138494Sobrien * which is the msi-number. bits 63..32 shall be zero. 38238494Sobrien * 38338494Sobrien * For MSI, bits 15..0 contain the data from the MSI message 38438494Sobrien * which is the msi-number. bits 63..16 shall be zero 38538494Sobrien * 38638494Sobrien * For MSG data, the message code and message routing code 38738494Sobrien * are encoded as follows: 38838494Sobrien * 38938494Sobrien * 63:32 - 0000.0000.0000.0000.0000.0000.GGGG.GGGG 39038494Sobrien * 32:00 - 0000.0000.0000.0CCC.0000.0000.MMMM.MMMM 39138494Sobrien * 39238494Sobrien * Where, 39338494Sobrien * 39438494Sobrien * GG..GG is the target-id of the message in the 39538494Sobrien * following form: 39638494Sobrien * 39738494Sobrien * bbbbbbbb.dddddfff 39838494Sobrien * 39938494Sobrien * where bb..bb is the target bus number. 40038494Sobrien * ddddd is the target deviceid 40138494Sobrien * fff is the target function number. 40238494Sobrien * 40338494Sobrien * CCC is the message routing code as defined by [4] 40438494Sobrien * 40538494Sobrien * MM..MM is the message code as defined by [4] 40638494Sobrien * 40738494Sobrien * For INTx data, bits 63:2 must be zero and 40838494Sobrien * the low order 2 bits are defined as follows: 40938494Sobrien * 41038494Sobrien * 00 - INTA 41138494Sobrien * 01 - INTB 41238494Sobrien * 10 - INTC 41338494Sobrien * 11 - INTD 41438494Sobrien * 41538494Sobrien * cpuid - A unique opaque value which represents a target cpu. 41638494Sobrien * 41738494Sobrien * devhandle - Device handle. The device handle uniquely identifies a 41838494Sobrien * SUN4V device. It consists of the the lower 28-bits of the hi-cell 41938494Sobrien * of the first entry of the SUN4V device's "reg" property as defined 42038494Sobrien * by the SUN4V Bus Binding to Open Firmware. 42138494Sobrien * 42238494Sobrien * msinum - A value defining which MSI is being used. 42338494Sobrien * 42438494Sobrien * msiqhead - The index value of the current head index for a given 42538494Sobrien * MSI-EQ. 42638494Sobrien * 42738494Sobrien * msiqtail - The index value of the current tail index for a given 42838494Sobrien * MSI-EQ. 42938494Sobrien * 43038494Sobrien * msitype - Type specifier for MSI32 or MSI64 43138494Sobrien * 0 - type is MSI32 43238494Sobrien * 1 - type is MSI64 43338494Sobrien * 43438494Sobrien * msiqid - A number from 0 .. 'number of MSI-EQs - 1', defining 43538494Sobrien * which MSI EQ within the device is being used. 43638494Sobrien * 43738494Sobrien * msiqstate - An unsigned integer containing one of the 43838494Sobrien * following values: 43938494Sobrien * 44038494Sobrien * PCI_MSIQSTATE_IDLE 0 # idle (non-error) state 44138494Sobrien * PCI_MSIQSTATE_ERROR 1 # error state 44238494Sobrien * 44338494Sobrien * msiqvalid - An unsigned integer containing one of the 44438494Sobrien * following values: 44538494Sobrien * 44638494Sobrien * PCI_MSIQ_INVALID 0 # disabled/invalid 44738494Sobrien * PCI_MSIQ_VALID 1 # enabled/valid 44838494Sobrien * 44938494Sobrien * msistate - An unsigned integer containing one of the following 45038494Sobrien * values: 45138494Sobrien * 45238494Sobrien * PCI_MSISTATE_IDLE 0 # idle/not enabled 45338494Sobrien * PCI_MSISTATE_DELIVERED 1 # MSI Delivered 45438494Sobrien * 45538494Sobrien * msivalid - An unsigned integer containing one of the 45638494Sobrien * following values: 45738494Sobrien * 45838494Sobrien * PCI_MSI_INVALID 0 # disabled/invalid 45938494Sobrien * PCI_MSI_VALID 1 # enabled/valid 46038494Sobrien * 46138494Sobrien * msgtype - A value defining which MSG type is being used. An unsigned 46238494Sobrien * integer containing one of the following values: 46338494Sobrien * (as per PCIe spec 1.0a) 46438494Sobrien * 46538494Sobrien * PCIE_PME_MSG 0x18 PME message 46638494Sobrien * PCIE_PME_ACK_MSG 0x1b PME ACK message 46738494Sobrien * PCIE_CORR_MSG 0x30 Correctable message 46838494Sobrien * PCIE_NONFATAL_MSG 0x31 Non fatal message 46938494Sobrien * PCIE_FATAL_MSG 0x33 Fatal message 47038494Sobrien */ 47138494Sobrien 47238494Sobrientypedef uint32_t msinum_t; 47338494Sobrientypedef uint32_t msiqid_t; 47438494Sobrientypedef uint32_t msgcode_t; 47538494Sobrientypedef uint64_t msiqhead_t; 47638494Sobrientypedef uint64_t msiqtail_t; 47738494Sobrien 47838494Sobrien/* MSIQ state */ 47938494Sobrientypedef enum pci_msiq_state { 48038494Sobrien PCI_MSIQ_STATE_IDLE = (uint32_t)0, /* idle (non-error) state */ 48138494Sobrien PCI_MSIQ_STATE_ERROR = (uint32_t)1 /* error state */ 48238494Sobrien} pci_msiq_state_t; 48338494Sobrien 48438494Sobrien/* MSIQ valid */ 48538494Sobrientypedef enum pci_msiq_valid_state { 48638494Sobrien PCI_MSIQ_INVALID = (uint32_t)0, /* disabled/invalid */ 48738494Sobrien PCI_MSIQ_VALID = (uint32_t)1 /* enabled/valid */ 48838494Sobrien} pci_msiq_valid_state_t; 48938494Sobrien 49038494Sobrien/* MSIQ Record data structure */ 49138494Sobrientypedef struct msiq_rec { 49238494Sobrien uint64_t msiq_rec_version : 32, /* DW 0 - 63:32 */ 49338494Sobrien msiq_rec_rsvd0 : 24, /* DW 0 - 31:09 */ 49438494Sobrien msiq_rec_type : 8; /* DW 0 - 07:00 */ 49538494Sobrien uint64_t msiq_rec_intx; /* DW 1 */ 49638494Sobrien uint64_t msiq_rec_rsvd1; /* DW 2 */ 49738494Sobrien uint64_t msiq_rec_timestamp; /* DW 3 */ 49838494Sobrien uint64_t msiq_rec_rsvd2 : 48, /* DW 4 - 63:16 */ 49938494Sobrien msiq_rec_rid : 16; /* DW 4 - 15:00 */ 50038494Sobrien uint64_t msiq_rec_msi_addr; /* DW 5 - 63:00 */ 50138494Sobrien union { 50238494Sobrien struct { 50338494Sobrien uint64_t msix_rsvd0 : 32, /* DW 6 - 63:32 */ 50438494Sobrien msix_data : 32; /* DW 6 - 31:00 */ 50538494Sobrien } msix; 50638494Sobrien struct { 50738494Sobrien uint64_t msi_rsvd0 : 48, /* DW 6 - 63:16 */ 50838494Sobrien msi_data: 16; /* DW 6 - 15:00 */ 50938494Sobrien } msi; 51038494Sobrien struct { 51138494Sobrien uint64_t msg_rsvd0: 24, /* DW 6 - 63:40 */ 51238494Sobrien msg_targ: 8, /* DW 6 - 39:32 */ 51338494Sobrien msg_rsvd1: 13, /* DW 6 - 31:19 */ 51438494Sobrien msg_route: 3, /* DW 6 - 18:16 */ 51538494Sobrien msg_rsvd2: 8, /* DW 6 - 15:08 */ 51638494Sobrien msg_code: 8; /* DW 6 - 07:00 */ 51738494Sobrien } msg; 51838494Sobrien } msiq_rec_data; 51938494Sobrien uint64_t msiq_rec_rsvd3; /* DW 7 */ 52038494Sobrien} msiq_rec_t; 52138494Sobrien 52238494Sobrien/* MSIQ Record type */ 52338494Sobrientypedef enum msiq_rec_type { 52438494Sobrien MSG_REC = (uint32_t)1, /* PCIe message record */ 52538494Sobrien MSI32_REC = (uint32_t)2, /* MSI32 record */ 52638494Sobrien MSI64_REC = (uint32_t)3, /* MSI64 record */ 52738494Sobrien INTX_REC = (uint32_t)8 /* INTx record */ 52838494Sobrien} msiq_rec_type_t; 52938494Sobrien 53038494Sobrien/* MSIQ Record type */ 53138494Sobrientypedef enum msi_type { 53238494Sobrien MSI32_TYPE = (uint32_t)0, /* MSI32 type */ 53338494Sobrien MSI64_TYPE = (uint32_t)1 /* MSI64 type */ 53438494Sobrien} msi_type_t; 53538494Sobrien 53638494Sobrien/* MSI state */ 537typedef enum pci_msi_state { 538 PCI_MSI_STATE_IDLE = (uint32_t)0, /* idle/not enabled */ 539 PCI_MSI_STATE_DELIVERED = (uint32_t)1 /* MSI delivered */ 540} pci_msi_state_t; 541 542/* MSI valid */ 543typedef enum pci_msi_valid_state { 544 PCI_MSI_INVALID = (uint32_t)0, /* disabled/invalid */ 545 PCI_MSI_VALID = (uint32_t)1 /* enabled/valid */ 546} pci_msi_valid_state_t; 547 548/* MSG valid */ 549typedef enum pcie_msg_valid_state { 550 PCIE_MSG_INVALID = (uint32_t)0, /* disabled/invalid */ 551 PCIE_MSG_VALID = (uint32_t)1 /* enabled/valid */ 552} pcie_msg_valid_state_t; 553 554/* PCIe MSG types */ 555typedef enum pcie_msg_type { 556 PCIE_PME_MSG = (uint64_t)0x18, /* PME message */ 557 PCIE_PME_ACK_MSG = (uint64_t)0x1b, /* PME ACK message */ 558 PCIE_CORR_MSG = (uint64_t)0x30, /* Correctable message */ 559 PCIE_NONFATAL_MSG = (uint64_t)0x31, /* Non fatal message */ 560 PCIE_FATAL_MSG = (uint64_t)0x33 /* Fatal message */ 561} pcie_msg_type_t; 562 563#endif /* _ASM */ 564 565#ifdef __cplusplus 566} 567#endif 568 569#endif /* _SYS_PX_IOAPI_H */ 570