1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_PX_IOAPI_H 27#define _SYS_PX_IOAPI_H 28 29#ifdef __cplusplus 30extern "C" { 31#endif 32 33#ifndef _ASM 34 35/* 36 * SUN4V IO Data Definitions 37 * 38 * cpuid - A unique opaque value which represents a target cpu. 39 * 40 * devhandle - Device handle. The device handle uniquely 41 * identifies a SUN4V device. It consists of the 42 * the lower 28-bits of the hi-cell of the first 43 * entry of the SUN4V device's "reg" property as defined 44 * by the SUN4V Bus Binding to Open Firmware. 45 * 46 * devino - Device Interrupt Number. An unsigned integer representing 47 * an interrupt within a specific device. 48 * 49 * sysino - System Interrupt Number. A 64-bit unsigned integer 50 * representing a unique interrupt within a "system". 51 * 52 * intr_state - A flag representing the interrupt state for a 53 * a given sysino. The state values are defined as: 54 * 55 * INTR_IDLE 0 56 * INTR_RECEIVED 1 57 * INTR_DELIVERED 2 58 * 59 * intr_valid_state - A flag representing the 'valid' state for 60 * a given sysino. The state values are defined as: 61 * 62 * INTR_NOTVALID 0 sysino not enabled 63 * INTR_VALID 1 sysino enabled 64 */ 65 66typedef uint64_t devhandle_t; 67 68typedef uint32_t cpuid_t; 69typedef uint32_t devino_t; 70typedef uint64_t sysino_t; 71 72typedef enum intr_state { 73 INTR_IDLE_STATE = (uint32_t)0, 74 INTR_RECEIVED_STATE = (uint32_t)1, 75 INTR_DELIVERED_STATE = (uint32_t)2 76} intr_state_t; 77 78typedef enum intr_valid_state { 79 INTR_NOTVALID = (uint32_t)0, 80 INTR_VALID = (uint32_t)1 81} intr_valid_state_t; 82 83/* 84 * PCI IO Data Definitions 85 * 86 * tsbnum - TSB Number. Identifies which io-tsb is used. 87 * For this version of the spec, tsbnum must be zero. 88 * 89 * tsbindex - TSB Index. Identifies which entry in the tsb is 90 * is used. The first entry is zero. 91 * 92 * tsbid - A 64-bit aligned data structure which contains 93 * a tsbnum and a tsbindex. 94 * bits 63:32 contain the tsbnum. 95 * bits 31:00 contain the tsbindex. 96 * 97 * io_attributes - IO Attributes for iommu mappings. 98 * Attributes for iommu mappings. One or more of the 99 * following attribute bits stored in a 64-bit unsigned int. 100 * 101 * 6 3 0 102 * 3 1 0 103 * 00000000 00000000 00000000 00000000 BBBBBBBB DDDDDFFF 00000000 00PP0LWR 104 * 105 * R: DMA data is transferred from main memory to device. 106 * W: DMA data is transferred from device to main memory. 107 * L: Requested DMA transaction can be relaxed ordered within RC. 108 * P: Value of PCI Express and PCI-X phantom function 109 * configuration. Its encoding is identical to the 110 * "Phantom Function Supported" field of the 111 * "Device Capabilities Register (offset 0x4)" 112 * in the "PCI Express Capability Structure". 113 * The structure is part of a device's config space. 114 * BDF: Bus, device and function number of the device 115 * that is going to issue DMA transactions. 116 * The BDF values are used to guarantee the mapping 117 * only be accessed by the specified device. 118 * If the BDF is set to all 0, RID based protection 119 * will be turned off. 120 * 121 * Relaxed Ordering (L) is advisory. Not all hardware implements a 122 * relaxed ordering attribute. If L attribute is not implemented in 123 * hardware, the implementation is permitted to ignore the L bit. 124 * 125 * Bits 3, 15:6 and 63:32 are unused and must be set to zero for 126 * this version of the specification. 127 * 128 * Note: For compatibility with future versions of this 129 * specification, the caller must set bits 3, 15:6 and 63:32 to 130 * zero. The implementation shall ignore these bits. 131 * 132 * r_addr - 64-bit Real Address. 133 * 134 * io_addr - 64-bit IO Address. 135 * 136 * pci_device - PCI device address. A PCI device address 137 * identifies a specific device on a specific PCI 138 * bus segment. A PCI device address is a 32-bit unsigned 139 * integer with the following format: 140 * 141 * 00000000.bbbbbbbb.dddddfff.00000000 142 * 143 * Where: 144 * 145 * bbbbbbbb is the 8-bit pci bus number 146 * ddddd is the 5-bit pci device number 147 * fff is the 3-bit pci function number 148 * 149 * 00000000 is the 8-bit literal zero. 150 * 151 * pci_config_offset - PCI Configuration Space offset. 152 * 153 * For conventional PCI, an unsigned integer in the range 154 * 0 .. 255 representing the offset of the field in pci config 155 * space. 156 * 157 * For PCI implementations with extended configuration space, 158 * an unsigned integer in the range 0 .. 4095, representing 159 * the offset of the field in configuration space. Conventional 160 * PCI config space is offset 0 .. 255. Extended config space 161 * is offset 256 .. 4095 162 * 163 * Note: For pci config space accesses, the offset must be 'size' 164 * aligned. 165 * 166 * error_flag - Error flag 167 * 168 * A return value specifies if the action succeeded 169 * or failed, where: 170 * 171 * 0 - No error occurred while performing the service. 172 * non-zero - Error occurred while performing the service. 173 * 174 * io_sync_direction - "direction" definition for pci_dma_sync 175 * 176 * A value specifying the direction for a memory/io sync 177 * operation, The direction value is a flag, one or both 178 * directions may be specified by the caller. 179 * 180 * 0x01 - For device (device read from memory) 181 * 0x02 - For cpu (device write to memory) 182 * 183 * io_page_list - A list of io_page_addresses. An io_page_address 184 * is an r_addr. 185 * 186 * io_page_list_p - A pointer to an io_page_list. 187 */ 188typedef uint32_t tsbnum_t; 189typedef uint32_t tsbindex_t; 190typedef uint64_t tsbid_t; 191typedef uint64_t r_addr_t; 192typedef uint64_t io_addr_t; 193typedef uint64_t io_page_list_t; 194typedef uint32_t pages_t; 195typedef uint32_t error_flag_t; 196 197typedef uint32_t pci_config_offset_t; 198typedef uint64_t pci_device_t; 199 200#define PCI_TSB_INDEX 0 201#define PCI_TSB_INDEX_MASK 0xFFFFFFFF 202#define PCI_TSB_NUM 32 203#define PCI_TSB_NUM_MASK 0xFFFFFFFF 204 205#define PCI_TSBID(tsbnum, tsbindex) \ 206 ((((tsbid_t)tsbnum & PCI_TSB_NUM_MASK) << PCI_TSB_NUM) | \ 207 (((tsbid_t)tsbindex & PCI_TSB_INDEX_MASK) << PCI_TSB_INDEX)) 208 209#define PCI_TSBID_TO_TSBNUM(tsbid) \ 210 ((tsbid >> PCI_TSB_NUM) & PCI_TSB_NUM_MASK) 211 212#define PCI_TSBID_TO_TSBINDEX(tsbid) \ 213 ((tsbid >> PCI_TSB_INDEX) & PCI_TSB_INDEX_MASK) 214 215typedef uint64_t io_attributes_t; 216 217#define PCI_MAP_ATTR_READ 0x1ull 218#define PCI_MAP_ATTR_WRITE 0x2ull 219#define PCI_MAP_ATTR_RO 0x4ull 220 221#define PCI_MAP_ATTR_PHFUN 4 222#define PCI_MAP_ATTR_BDF 16 223 224#define PCI_MAP_ATTR_PHFUN_MASK 0x30 225#define PCI_MAP_ATTR_BDF_MASK 0xffff0000 226 227#define PX_ADD_ATTR_EXTNS(attr, bdf) \ 228 (attr | (PCIE_CHECK_VALID_BDF(bdf) ? (bdf << PCI_MAP_ATTR_BDF) : 0)) 229 230typedef enum io_sync_direction { 231 IO_SYNC_DEVICE = (uint32_t)0x01, 232 IO_SYNC_CPU = (uint32_t)0x02 233} io_sync_direction_t; 234 235/* 236 * MSI Definitions 237 * 238 * MSI - Message Signaled Interrupt 239 * 240 * Message Signaled Interrupt as defined in the PCI Local Bus 241 * Specification and the PCI Express Base Specification. 242 * A device signals an interrupt via MSI using a posted 243 * write cycle to an address specified by system software 244 * using a data value specified by system software. 245 * The MSI capability data structure contains fields for 246 * the PCI address and data values the device uses when 247 * sending an MSI message on the bus. MSI-X is an extended 248 * form of MSI, but uses the same mechanism for signaling 249 * the interrupt as MSI. For the purposes of this document, 250 * the term "MSI" refers to MSI or MSI-X. 251 * 252 * Root complexes that support MSI define an address range 253 * and set of data values that can be used to signal MSIs. 254 * 255 * SUN4V/pci requirements for MSI: 256 * 257 * The root complex defines two address ranges. One in 258 * the 32-bit pci memory space and one in the 64-bit 259 * pci memory address space used as the target of a posted 260 * write to signal an MSI. 261 * 262 * The root complex treats any write to these address 263 * ranges as signaling an MSI, however, only the data 264 * value used in the posted write signals the MSI. 265 * 266 * 267 * MSI EQ - MSI Event Queue 268 * 269 * The MSI Event Queue is a page-aligned main memory data 270 * structure used to store MSI data records. 271 * 272 * Each root port supports several MSI EQs, and each EQ has a 273 * system interrupt associated with it, and can be targeted 274 * (individually) to any cpu. The number of MSI EQs supported 275 * by a root complex is described by a property defined in [3]. 276 * Each MSI EQ must be large enough to contain all possible MSI 277 * data records generated by any one PCI root port. The number 278 * of entries in each MSI EQ is described by a property defined 279 * in [3]. 280 * 281 * Each MSI EQ is compliant with the definition of interrupt 282 * queues described in [5], however, instead of accessing the 283 * queue head/tail registers via ASI-based registers, an API 284 * is provided to access the head/tail registers. 285 * 286 * The SUN4V/pci compliant root complex has the ability to 287 * generate a system interrupt when the MSI EQ is non-empty. 288 * 289 * MSI/Message/INTx Data Record format 290 * 291 * Each data record consists of 64 bytes of data, aligned 292 * on a 64-byte boundary. 293 * 294 * The data record is defined as follows: 295 * 296 * 297 * 6666555555555544444444443333333333222222222211111111110000000000 298 * 3210987654321098765432109876543210987654321098765432109876543210 299 * 300 * 0x00: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVxxxxxxxxxxxxxxxxxxxxxxxxTTTTTTTT 301 * 0x08: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 302 * 0x10: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 303 * 0x18: SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 304 * 0x20: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxRRRRRRRRRRRRRRRR 305 * 0x28: AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 306 * 0x30: DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 307 * 0x38: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 308 * 309 * Where, 310 * 311 * xx..xx are unused bits and must be ignored by sw. 312 * 313 * VV..VV is the version number of this data record 314 * 315 * For this release of the spec, the version number 316 * field must be zero. 317 * 318 * TTTTTTTT is the data record type: 319 * 320 * Upper 4 bits are reserved, and must be zero 321 * 322 * 0000 - Not an MSI data record - reserved for sw use. 323 * 0001 - MSG 324 * 0010 - MSI32 325 * 0011 - MSI64 326 * 0010 - Reserved 327 * ... 328 * 0111 - Reserved 329 * 1000 - INTx 330 * 1001 - Reserved 331 * ... 332 * 1110 - Reserved 333 * 1111 - Not an MSI data record - reserved for sw use. 334 * 335 * All other encodings are reserved. 336 * 337 * II..II is the sysino for INTx (sw defined value), 338 * otherwise zero. 339 * 340 * SS..SS is the message timestamp if available. 341 * If supported by the implementation, a non-zero 342 * value in this field is a copy of the %stick register 343 * at the time the message is created. 344 * 345 * If unsupported, this field will contain zero. 346 * 347 * RR..RR is the requester ID of the device that initiated the MSI/MSG 348 * and has the following format: 349 * 350 * bbbbbbbb.dddddfff 351 * 352 * Where bb..bb is the bus number, 353 * dd..dd is the device number 354 * and fff is the function number. 355 * 356 * Note that for PCI devices or any message where 357 * the requester is unknown, this may be zero, 358 * or the device-id of an intermediate bridge. 359 * 360 * For intx messages, this field should be ignored. 361 * 362 * AA..AA is the MSI address. For MSI32, the upper 32-bits must be zero. 363 * (for data record type MSG or INTx, this field is ignored) 364 * 365 * DD..DD is the MSI/MSG data or INTx number 366 * 367 * For MSI-X, bits 31..0 contain the data from the MSI packet 368 * which is the msi-number. bits 63..32 shall be zero. 369 * 370 * For MSI, bits 15..0 contain the data from the MSI message 371 * which is the msi-number. bits 63..16 shall be zero 372 * 373 * For MSG data, the message code and message routing code 374 * are encoded as follows: 375 * 376 * 63:32 - 0000.0000.0000.0000.0000.0000.GGGG.GGGG 377 * 32:00 - 0000.0000.0000.0CCC.0000.0000.MMMM.MMMM 378 * 379 * Where, 380 * 381 * GG..GG is the target-id of the message in the 382 * following form: 383 * 384 * bbbbbbbb.dddddfff 385 * 386 * where bb..bb is the target bus number. 387 * ddddd is the target deviceid 388 * fff is the target function number. 389 * 390 * CCC is the message routing code as defined by [4] 391 * 392 * MM..MM is the message code as defined by [4] 393 * 394 * For INTx data, bits 63:2 must be zero and 395 * the low order 2 bits are defined as follows: 396 * 397 * 00 - INTA 398 * 01 - INTB 399 * 10 - INTC 400 * 11 - INTD 401 * 402 * cpuid - A unique opaque value which represents a target cpu. 403 * 404 * devhandle - Device handle. The device handle uniquely identifies a 405 * SUN4V device. It consists of the the lower 28-bits of the hi-cell 406 * of the first entry of the SUN4V device's "reg" property as defined 407 * by the SUN4V Bus Binding to Open Firmware. 408 * 409 * msinum - A value defining which MSI is being used. 410 * 411 * msiqhead - The index value of the current head index for a given 412 * MSI-EQ. 413 * 414 * msiqtail - The index value of the current tail index for a given 415 * MSI-EQ. 416 * 417 * msitype - Type specifier for MSI32 or MSI64 418 * 0 - type is MSI32 419 * 1 - type is MSI64 420 * 421 * msiqid - A number from 0 .. 'number of MSI-EQs - 1', defining 422 * which MSI EQ within the device is being used. 423 * 424 * msiqstate - An unsigned integer containing one of the 425 * following values: 426 * 427 * PCI_MSIQSTATE_IDLE 0 # idle (non-error) state 428 * PCI_MSIQSTATE_ERROR 1 # error state 429 * 430 * msiqvalid - An unsigned integer containing one of the 431 * following values: 432 * 433 * PCI_MSIQ_INVALID 0 # disabled/invalid 434 * PCI_MSIQ_VALID 1 # enabled/valid 435 * 436 * msistate - An unsigned integer containing one of the following 437 * values: 438 * 439 * PCI_MSISTATE_IDLE 0 # idle/not enabled 440 * PCI_MSISTATE_DELIVERED 1 # MSI Delivered 441 * 442 * msivalid - An unsigned integer containing one of the 443 * following values: 444 * 445 * PCI_MSI_INVALID 0 # disabled/invalid 446 * PCI_MSI_VALID 1 # enabled/valid 447 * 448 * msgtype - A value defining which MSG type is being used. An unsigned 449 * integer containing one of the following values: 450 * (as per PCIe spec 1.0a) 451 * 452 * PCIE_PME_MSG 0x18 PME message 453 * PCIE_PME_ACK_MSG 0x1b PME ACK message 454 * PCIE_CORR_MSG 0x30 Correctable message 455 * PCIE_NONFATAL_MSG 0x31 Non fatal message 456 * PCIE_FATAL_MSG 0x33 Fatal message 457 */ 458 459typedef uint32_t msinum_t; 460typedef uint32_t msiqid_t; 461typedef uint32_t msgcode_t; 462typedef uint64_t msiqhead_t; 463typedef uint64_t msiqtail_t; 464 465/* MSIQ state */ 466typedef enum pci_msiq_state { 467 PCI_MSIQ_STATE_IDLE = (uint32_t)0, /* idle (non-error) state */ 468 PCI_MSIQ_STATE_ERROR = (uint32_t)1 /* error state */ 469} pci_msiq_state_t; 470 471/* MSIQ valid */ 472typedef enum pci_msiq_valid_state { 473 PCI_MSIQ_INVALID = (uint32_t)0, /* disabled/invalid */ 474 PCI_MSIQ_VALID = (uint32_t)1 /* enabled/valid */ 475} pci_msiq_valid_state_t; 476 477/* MSIQ Record data structure */ 478typedef struct msiq_rec { 479 uint64_t msiq_rec_version : 32, /* DW 0 - 63:32 */ 480 msiq_rec_rsvd0 : 24, /* DW 0 - 31:09 */ 481 msiq_rec_type : 8; /* DW 0 - 07:00 */ 482 uint64_t msiq_rec_intx; /* DW 1 */ 483 uint64_t msiq_rec_rsvd1; /* DW 2 */ 484 uint64_t msiq_rec_timestamp; /* DW 3 */ 485 uint64_t msiq_rec_rsvd2 : 48, /* DW 4 - 63:16 */ 486 msiq_rec_rid : 16; /* DW 4 - 15:00 */ 487 uint64_t msiq_rec_msi_addr; /* DW 5 - 63:00 */ 488 union { 489 struct { 490 uint64_t msix_rsvd0 : 32, /* DW 6 - 63:32 */ 491 msix_data : 32; /* DW 6 - 31:00 */ 492 } msix; 493 struct { 494 uint64_t msi_rsvd0 : 48, /* DW 6 - 63:16 */ 495 msi_data: 16; /* DW 6 - 15:00 */ 496 } msi; 497 struct { 498 uint64_t msg_rsvd0: 24, /* DW 6 - 63:40 */ 499 msg_targ: 8, /* DW 6 - 39:32 */ 500 msg_rsvd1: 13, /* DW 6 - 31:19 */ 501 msg_route: 3, /* DW 6 - 18:16 */ 502 msg_rsvd2: 8, /* DW 6 - 15:08 */ 503 msg_code: 8; /* DW 6 - 07:00 */ 504 } msg; 505 } msiq_rec_data; 506 uint64_t msiq_rec_rsvd3; /* DW 7 */ 507} msiq_rec_t; 508 509/* MSIQ Record type */ 510typedef enum msiq_rec_type { 511 MSG_REC = (uint32_t)1, /* PCIe message record */ 512 MSI32_REC = (uint32_t)2, /* MSI32 record */ 513 MSI64_REC = (uint32_t)3, /* MSI64 record */ 514 INTX_REC = (uint32_t)8 /* INTx record */ 515} msiq_rec_type_t; 516 517/* MSIQ Record type */ 518typedef enum msi_type { 519 MSI32_TYPE = (uint32_t)0, /* MSI32 type */ 520 MSI64_TYPE = (uint32_t)1 /* MSI64 type */ 521} msi_type_t; 522 523/* MSI state */ 524typedef enum pci_msi_state { 525 PCI_MSI_STATE_IDLE = (uint32_t)0, /* idle/not enabled */ 526 PCI_MSI_STATE_DELIVERED = (uint32_t)1 /* MSI delivered */ 527} pci_msi_state_t; 528 529/* MSI valid */ 530typedef enum pci_msi_valid_state { 531 PCI_MSI_INVALID = (uint32_t)0, /* disabled/invalid */ 532 PCI_MSI_VALID = (uint32_t)1 /* enabled/valid */ 533} pci_msi_valid_state_t; 534 535/* MSG valid */ 536typedef enum pcie_msg_valid_state { 537 PCIE_MSG_INVALID = (uint32_t)0, /* disabled/invalid */ 538 PCIE_MSG_VALID = (uint32_t)1 /* enabled/valid */ 539} pcie_msg_valid_state_t; 540 541/* PCIe MSG types */ 542typedef enum pcie_msg_type { 543 PCIE_PME_MSG = (uint64_t)0x18, /* PME message */ 544 PCIE_PME_ACK_MSG = (uint64_t)0x1b, /* PME ACK message */ 545 PCIE_CORR_MSG = (uint64_t)0x30, /* Correctable message */ 546 PCIE_NONFATAL_MSG = (uint64_t)0x31, /* Non fatal message */ 547 PCIE_FATAL_MSG = (uint64_t)0x33 /* Fatal message */ 548} pcie_msg_type_t; 549 550#endif /* _ASM */ 551 552#ifdef __cplusplus 553} 554#endif 555 556#endif /* _SYS_PX_IOAPI_H */ 557