1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#ifndef	_FPC_H
28#define	_FPC_H
29
30#pragma ident	"%Z%%M%	%I%	%E% SMI"
31
32#ifdef	__cplusplus
33extern "C" {
34#endif
35
36#define	SUCCESS	0
37#define	FAILURE	-1
38
39#define	NUM_LEAVES	2
40
41extern int fpc_debug;
42#define	FPC_DBG1 if (fpc_debug >= 1) printf
43#define	FPC_DBG2 if (fpc_debug >= 2) printf
44
45/*
46 * Defs for fpc-kstat.c.  Put'em here for now even though they don't
47 * have to do with the lower-level implementation.
48 */
49extern int fpc_kstat_init(dev_info_t *dip);
50extern void fpc_kstat_fini(dev_info_t *dip);
51
52typedef enum fire_perfcnt {
53	jbc = 0,
54	imu,
55	mmu,
56	tlu,
57	lpu
58} fire_perfcnt_t;
59
60/* Set to the last entry in fire_perfcnt_t. */
61#define	MAX_REG_TYPES		((int)lpu + 1)
62
63#define	NUM_JBC_COUNTERS	2
64#define	NUM_IMU_COUNTERS	2
65#define	NUM_MMU_COUNTERS	2
66#define	NUM_TLU_COUNTERS	3
67#define	NUM_LPU_COUNTERS	2
68
69/* Sum of all NUM_xxx_COUNTERS above. */
70#define	NUM_TOTAL_COUNTERS	11
71
72/* largest group of counters */
73#define	NUM_MAX_COUNTERS	NUM_TLU_COUNTERS
74
75/* Event mask related. */
76
77/* How much an event for a given PIC is shifted within the event mask. */
78
79#define	PIC0_EVT_SEL_SHIFT	0
80#define	PIC1_EVT_SEL_SHIFT	8
81#define	PIC2_EVT_SEL_SHIFT	16
82
83/* Width or mask of a single event within an event mask. */
84
85#define	JBC01_EVT_MASK		0xFF
86#define	IMU01_EVT_MASK		0xFF
87#define	MMU01_EVT_MASK		0xFF
88#define	TLU01_EVT_MASK		0xFF
89#define	TLU2_EVT_MASK		0x3
90#define	LPU12_EVT_MASK		0xFFFF
91
92/* Positioned masks for different event fields within an event mask. */
93
94#define	JBC_PIC0_EVT_MASK	((uint64_t)JBC01_EVT_MASK << PIC0_EVT_SEL_SHIFT)
95#define	JBC_PIC1_EVT_MASK	((uint64_t)JBC01_EVT_MASK << PIC1_EVT_SEL_SHIFT)
96#define	IMU_PIC0_EVT_MASK	((uint64_t)IMU01_EVT_MASK << PIC0_EVT_SEL_SHIFT)
97#define	IMU_PIC1_EVT_MASK	((uint64_t)IMU01_EVT_MASK << PIC1_EVT_SEL_SHIFT)
98#define	MMU_PIC0_EVT_MASK	((uint64_t)MMU01_EVT_MASK << PIC0_EVT_SEL_SHIFT)
99#define	MMU_PIC1_EVT_MASK	((uint64_t)MMU01_EVT_MASK << PIC1_EVT_SEL_SHIFT)
100#define	TLU_PIC0_EVT_MASK	((uint64_t)TLU01_EVT_MASK << PIC0_EVT_SEL_SHIFT)
101#define	TLU_PIC1_EVT_MASK	((uint64_t)TLU01_EVT_MASK << PIC1_EVT_SEL_SHIFT)
102#define	TLU_PIC2_EVT_MASK	((uint64_t)TLU2_EVT_MASK << PIC2_EVT_SEL_SHIFT)
103#define	LPU_PIC0_EVT_MASK	((uint64_t)LPU12_EVT_MASK << PIC0_EVT_SEL_SHIFT)
104#define	LPU_PIC1_EVT_MASK	((uint64_t)LPU12_EVT_MASK << PIC2_EVT_SEL_SHIFT)
105
106/*
107 * Take a dip to define the device...
108 *   sun4v: can convert dip to a dev_hdl needed for hyp. perf ctr interface.
109 *   sun4u: can convert dip to an ldi_ident_t I can use for a layered PCItool
110 *	ioctl.
111 *
112 * Define which of JBUS, PCIE_A and PCIE_B regs are available.  HW partitioning
113 * may make some register sets unavailable to certain virtual nodes.
114 */
115
116#define	JBUS_REGS_AVAIL		0x1	/* JBUS regs avail */
117#define	PCIE_A_REGS_AVAIL	0x2
118#define	PCIE_B_REGS_AVAIL	0x4
119
120/* For checking platform from _init before installing module */
121extern int fpc_init_platform_check();
122
123/* Low level module initialization done at attach time. */
124extern int fpc_perfcnt_module_init(dev_info_t *dip, int *avail);
125extern int fpc_perfcnt_module_fini(dev_info_t *dip);
126
127/*
128 * Program a performance counter.
129 *
130 * reggroup is which type of counter.
131 * counter is the counter number.
132 * event is the event to program for that counter.
133 */
134extern int fpc_perfcnt_program(int devnum, fire_perfcnt_t reggroup,
135    uint64_t event);
136
137/*
138 * Read a performance counter.
139 *
140 * reggroup is which type of counter.
141 * counter is the counter number.
142 * event_p returns the event programmed for that counter.
143 * value_p returns the counter value.
144 */
145extern int fpc_perfcnt_read(int devnum, fire_perfcnt_t reggroup,
146    uint64_t *event_p, uint64_t values[NUM_MAX_COUNTERS]);
147
148/*
149 * Definitions of the different types of events.
150 *
151 * The first part says which registers these events are for.
152 * For example, JBC01 means the JBC performance counters 0 and 1
153 */
154
155#define	JBC01_S_EVT_NONE		"event_none"
156#define	JBC01_S_EVT_CLK			"clock_cyc"
157#define	JBC01_S_EVT_IDLE		"idle_cyc"
158#define	JBC01_S_EVT_FIRE		"fire_jbus_cyc"
159#define	JBC01_S_EVT_READ_LATENCY	"rd_latency_cyc"
160#define	JBC01_S_EVT_READ_SAMPLE		"rd_sample"
161#define	JBC01_S_EVT_I2C_PIO		"pios_i2c"
162#define	JBC01_S_EVT_EBUS_PIO		"pios_ebus"
163#define	JBC01_S_EVT_RINGA_PIO		"pios_ringA"
164#define	JBC01_S_EVT_RINGB_PIO		"pios_ringB"
165#define	JBC01_S_EVT_PARTIAL_WR		"partial_wr"
166#define	JBC01_S_EVT_TOTAL_WR		"total_wr"
167#define	JBC01_S_EVT_TOTAL_RD		"total_rd"
168#define	JBC01_S_EVT_AOKOFF		"aokoff"
169#define	JBC01_S_EVT_DOKOFF		"dokoff"
170#define	JBC01_S_EVT_DAOKOFF		"daokoff"
171#define	JBC01_S_EVT_JBUS_COH_XACT	"jbus_coh_tr"
172#define	JBC01_S_EVT_FIRE_COH_XACT	"fire_coh_tr"
173#define	JBC01_S_EVT_JBUS_NCOH_XACT	"jbus_ncoh_tr"
174#define	JBC01_S_EVT_FGN_IO_HIT		"fgn_pio_hit"
175#define	JBC01_S_EVT_FIRE_WBS		"fire_wb"
176#define	JBC01_S_EVT_PCIEA_PIO_WR	"pio_wr_pcieA"
177#define	JBC01_S_EVT_PCIEA_PIO_RD	"pio_rd_pcieA"
178#define	JBC01_S_EVT_PCIEB_PIO_WR	"pio_wr_pcieB"
179#define	JBC01_S_EVT_PCIEB_PIO_RD	"pio_rd_pcieB"
180
181#define	JBC01_EVT_NONE			0x0
182#define	JBC01_EVT_CLK			0x1
183#define	JBC01_EVT_IDLE			0x2
184#define	JBC01_EVT_FIRE			0x3
185#define	JBC01_EVT_READ_LATENCY		0x4
186#define	JBC01_EVT_READ_SAMPLE		0x5
187#define	JBC01_EVT_I2C_PIO		0x6
188#define	JBC01_EVT_EBUS_PIO		0x7
189#define	JBC01_EVT_RINGA_PIO		0x8
190#define	JBC01_EVT_RINGB_PIO		0x9
191#define	JBC01_EVT_PARTIAL_WR		0xA
192#define	JBC01_EVT_TOTAL_WR		0xB
193#define	JBC01_EVT_TOTAL_RD		0xC
194#define	JBC01_EVT_AOKOFF		0xD
195#define	JBC01_EVT_DOKOFF		0xE
196#define	JBC01_EVT_DAOKOFF		0xF
197#define	JBC01_EVT_JBUS_COH_XACT		0x10
198#define	JBC01_EVT_FIRE_COH_XACT		0x11
199#define	JBC01_EVT_JBUS_NCOH_XACT	0x12
200#define	JBC01_EVT_FGN_IO_HIT		0x13
201#define	JBC01_EVT_FIRE_WBS		0x14
202#define	JBC01_EVT_PCIEA_PIO_WR		0x15
203#define	JBC01_EVT_PCIEA_PIO_RD		0x16
204#define	JBC01_EVT_PCIEB_PIO_WR		0x17
205#define	JBC01_EVT_PCIEB_PIO_RD		0x18
206
207#define	IMU01_S_EVT_NONE		"event_none"
208#define	IMU01_S_EVT_CLK			"clock_cyc"
209#define	IMU01_S_EVT_MONDO		"mondos_iss"
210#define	IMU01_S_EVT_MSI			"msi_iss"
211#define	IMU01_S_EVT_MONDO_NAKS		"mondos_nacks"
212#define	IMU01_S_EVT_EQ_WR		"eq_wr"
213#define	IMU01_S_EVT_EQ_MONDO		"eq_mondos"
214
215#define	IMU01_EVT_NONE			0x0
216#define	IMU01_EVT_CLK			0x1
217#define	IMU01_EVT_MONDO			0x2
218#define	IMU01_EVT_MSI			0x3
219#define	IMU01_EVT_MONDO_NAKS		0x4
220#define	IMU01_EVT_EQ_WR			0x5
221#define	IMU01_EVT_EQ_MONDO		0x6
222
223#define	MMU01_S_EVT_NONE		"event_none"
224#define	MMU01_S_EVT_CLK			"clock_cyc"
225#define	MMU01_S_EVT_TRANS		"total_transl"
226#define	MMU01_S_EVT_STALL		"total_stall_cyc"
227#define	MMU01_S_EVT_TRANSL_MISS		"total_tranl_miss"
228#define	MMU01_S_EVT_TBLWLK_STALL	"tblwlk_stall_cyc"
229#define	MMU01_S_EVT_BYPASS_TRANSL	"bypass_transl"
230#define	MMU01_S_EVT_TRANSL_TRANSL	"transl_transl"
231#define	MMU01_S_EVT_FLOW_CNTL_STALL	"flow_stall_cyc"
232#define	MMU01_S_EVT_FLUSH_CACHE_ENT	"cache_entr_flush"
233
234#define	MMU01_EVT_NONE			0x0
235#define	MMU01_EVT_CLK			0x1
236#define	MMU01_EVT_TRANSL		0x2
237#define	MMU01_EVT_STALL			0x3
238#define	MMU01_EVT_TRANSL_MISS		0x4
239#define	MMU01_EVT_TBLWLK_STALL		0x5
240#define	MMU01_EVT_BYPASS_TRANSL		0x6
241#define	MMU01_EVT_TRANSL_TRANSL		0x7
242#define	MMU01_EVT_FLOW_CNTL_STALL	0x8
243#define	MMU01_EVT_FLUSH_CACHE_ENT	0x9
244
245#define	TLU01_S_EVT_NONE		"event_none"
246#define	TLU01_S_EVT_CLK			"clock_cyc"
247#define	TLU01_S_EVT_COMPL		"compl_recvd"
248#define	TLU01_S_EVT_XMT_POST_CR_UNAV	"post_cr_unav_cyc"
249#define	TLU01_S_EVT_XMT_NPOST_CR_UNAV	"npost_cr_unav_cyc"
250#define	TLU01_S_EVT_XMT_CMPL_CR_UNAV	"compl_cr_unav_cyc"
251#define	TLU01_S_EVT_XMT_ANY_CR_UNAV	"trans_cr_any_unav"
252#define	TLU01_S_EVT_RETRY_CR_UNAV	"retry_cr_unav"
253#define	TLU01_S_EVT_MEMRD_PKT_RCVD	"recvd_mem_rd_pkt"
254#define	TLU01_S_EVT_MEMWR_PKT_RCVD	"recvd_mem_wr_pkt"
255#define	TLU01_S_EVT_RCV_CR_THRESH	"recv_cr_thresh"
256#define	TLU01_S_EVT_RCV_PST_HDR_CR_EXH	"recv_hdr_cr_exh_cyc"
257#define	TLU01_S_EVT_RCV_PST_DA_CR_MPS	"recv_post_da_cr_mps"
258#define	TLU01_S_EVT_RCV_NPST_HDR_CR_EXH	"recv_npost_hdr_cr_exh"
259#define	TLU01_S_EVT_RCVR_L0S		"recvr_l0s_cyc"
260#define	TLU01_S_EVT_RCVR_L0S_TRANS	"recvr_l0s_trans"
261#define	TLU01_S_EVT_XMTR_L0S		"trans_l0s_cyc"
262#define	TLU01_S_EVT_XMTR_L0S_TRANS	"trans_l0s_trans"
263#define	TLU01_S_EVT_RCVR_ERR		"recvr_err"
264#define	TLU01_S_EVT_BAD_TLP		"bad_tlp"
265#define	TLU01_S_EVT_BAD_DLLP		"bad_dllp"
266#define	TLU01_S_EVT_REPLAY_ROLLOVER	"replay_rollover"
267#define	TLU01_S_EVT_REPLAY_TMO		"replay_to"
268
269#define	TLU01_EVT_NONE			0x0
270#define	TLU01_EVT_CLK			0x1
271#define	TLU01_EVT_COMPL			0x2
272#define	TLU01_EVT_XMT_POST_CR_UNAV	0x10
273#define	TLU01_EVT_XMT_NPOST_CR_UNAV	0x11
274#define	TLU01_EVT_XMT_CMPL_CR_UNAV	0x12
275#define	TLU01_EVT_XMT_ANY_CR_UNAV	0x13
276#define	TLU01_EVT_RETRY_CR_UNAV		0x14
277#define	TLU01_EVT_MEMRD_PKT_RCVD	0x20
278#define	TLU01_EVT_MEMWR_PKT_RCVD	0x21
279#define	TLU01_EVT_RCV_CR_THRESH		0x22
280#define	TLU01_EVT_RCV_PST_HDR_CR_EXH	0x23
281#define	TLU01_EVT_RCV_PST_DA_CR_MPS	0x24
282#define	TLU01_EVT_RCV_NPST_HDR_CR_EXH	0x25
283#define	TLU01_EVT_RCVR_L0S		0x30
284#define	TLU01_EVT_RCVR_L0S_TRANS	0x31
285#define	TLU01_EVT_XMTR_L0S		0x32
286#define	TLU01_EVT_XMTR_L0S_TRANS	0x33
287#define	TLU01_EVT_RCVR_ERR		0x40
288#define	TLU01_EVT_BAD_TLP		0x42
289#define	TLU01_EVT_BAD_DLLP		0x43
290#define	TLU01_EVT_REPLAY_ROLLOVER	0x44
291#define	TLU01_EVT_REPLAY_TMO		0x47
292
293#define	TLU2_S_EVT_NONE			"event_none"
294#define	TLU2_S_EVT_NON_POST_COMPL_TIME	"non_post_compl"
295#define	TLU2_S_EVT_XMT_DATA_WORD	"trans_data_words"
296#define	TLU2_S_EVT_RCVD_DATA_WORD	"recvd_data_words"
297
298#define	TLU2_EVT_NONE			0x0
299#define	TLU2_EVT_NON_POST_COMPL_TIME	0x1
300#define	TLU2_EVT_XMT_DATA_WORD		0x2
301#define	TLU2_EVT_RCVD_DATA_WORD		0x3
302
303#define	LPU12_S_EVT_RESET		"event_reset"
304#define	LPU12_S_EVT_TLP_RCVD		"tlp_recvd"
305#define	LPU12_S_EVT_DLLP_RCVD		"dllp_recvd"
306#define	LPU12_S_EVT_ACK_DLLP_RCVD	"ack_dllp_recvd"
307#define	LPU12_S_EVT_NAK_DLLP_RCVD	"nak_dllp_recvd"
308#define	LPU12_S_EVT_RETRY_START		"retries_started"
309#define	LPU12_S_EVT_REPLAY_TMO		"replay_timer_to"
310#define	LPU12_S_EVT_ACK_NAK_LAT_TMO	"ack_nak_lat_to"
311#define	LPU12_S_EVT_BAD_DLLP		"bad_dllp"
312#define	LPU12_S_EVT_BAD_TLP		"bad_tlp"
313#define	LPU12_S_EVT_NAK_DLLP_SENT	"nak_dllp_sent"
314#define	LPU12_S_EVT_ACK_DLLP_SENT	"ack_dllp_sent"
315#define	LPU12_S_EVT_RCVR_ERROR		"recvr_err"
316#define	LPU12_S_EVT_LTSSM_RECOV_ENTRY	"ltssm_recov_entr"
317#define	LPU12_S_EVT_REPLAY_IN_PROG	"replay_prog_cyc"
318#define	LPU12_S_EVT_TLP_XMT_IN_PROG	"tlp_trans_prog_cyc"
319#define	LPU12_S_EVT_CLK_CYC		"clock_cyc"
320#define	LPU12_S_EVT_TLP_DLLP_XMT_PROG	"tlp_dllp_trans_cyc"
321#define	LPU12_S_EVT_TLP_DLLP_RCV_PROG	"tlp_dllp_recv_cyc"
322
323#define	LPU12_EVT_RESET			0x0
324#define	LPU12_EVT_TLP_RCVD		0x1
325#define	LPU12_EVT_DLLP_RCVD		0x2
326#define	LPU12_EVT_ACK_DLLP_RCVD		0x3
327#define	LPU12_EVT_NAK_DLLP_RCVD		0x4
328#define	LPU12_EVT_RETRY_START		0x5
329#define	LPU12_EVT_REPLAY_TMO		0x6
330#define	LPU12_EVT_ACK_NAK_LAT_TMO	0x7
331#define	LPU12_EVT_BAD_DLLP		0x8
332#define	LPU12_EVT_BAD_TLP		0x9
333#define	LPU12_EVT_NAK_DLLP_SENT		0xA
334#define	LPU12_EVT_ACK_DLLP_SENT		0xB
335#define	LPU12_EVT_RCVR_ERROR		0xC
336#define	LPU12_EVT_LTSSM_RECOV_ENTRY	0xD
337#define	LPU12_EVT_REPLAY_IN_PROG	0xE
338#define	LPU12_EVT_TLP_XMT_IN_PROG	0xF
339#define	LPU12_EVT_CLK_CYC		0x10
340#define	LPU12_EVT_TLP_DLLP_XMT_PROG	0x11
341#define	LPU12_EVT_TLP_DLLP_RCV_PROG	0x12
342
343#define	COMMON_S_CLEAR_PIC		"clear_pic"
344
345#ifdef	__cplusplus
346}
347#endif
348
349#endif	/* _FPC_H */
350