1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_ERI_COMMON_H 27#define _SYS_ERI_COMMON_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#ifdef _KERNEL 36 37typedef void (*fptrv_t)(); 38 39typedef enum { 40 ERI_NO_MSG = 0, 41 ERI_CON_MSG = 1, 42 ERI_BUF_MSG = 2, 43 ERI_VERB_MSG = 3, 44 ERI_LOG_MSG = 4 45} msg_t; 46 47 48#ifdef DEBUG 49static msg_t eri_msg_out = ERI_VERB_MSG; 50#endif 51 52#ifdef LATER 53static char *fault_msg_string[] = { 54 "NONE ", 55 "LOW ", 56 "MID ", 57 "HIGH ", 58 "UNKNOWN " 59 60}; 61#endif 62 63#define SEVERITY_UNKNOWN 0 64#define SEVERITY_NONE 0 65#define SEVERITY_LOW 0 66#define SEVERITY_MID 1 67#define SEVERITY_HIGH 2 68 69 70#define ERI_FAULT_MSG1(p, t, f, a) \ 71 eri_fault_msg((p), (t), (f), (a)); 72 73#define ERI_FAULT_MSG2(p, t, f, a, b) \ 74 eri_fault_msg((p), (t), (f), (a), (b)); 75 76#define ERI_FAULT_MSG3(p, t, f, a, b, c) \ 77 eri_fault_msg((p), (t), (f), (a), (b), (c)); 78 79#define ERI_FAULT_MSG4(p, t, f, a, b, c, d) \ 80 eri_fault_msg((p), (t), (f), (a), (b), (c), (d)); 81 82#ifdef DEBUG 83typedef enum { 84 NO_MSG = 0, 85 AUTOCONFIG_MSG = 1, 86 STREAMS_MSG = 2, 87 IOCTL_MSG = 3, 88 PROTO_MSG = 4, 89 INIT_MSG = 5, 90 TX_MSG = 6, 91 RX_MSG = 7, 92 INTR_MSG = 8, 93 UNINIT_MSG = 9, 94 CONFIG_MSG = 10, 95 PROP_MSG = 11, 96 ENTER_MSG = 12, 97 RESUME_MSG = 13, 98 AUTONEG_MSG = 14, 99 NAUTONEG_MSG = 15, 100 FATAL_ERR_MSG = 16, 101 NONFATAL_MSG = 17, 102 NDD_MSG = 18, 103 PHY_MSG = 19, 104 XCVR_MSG = 20, 105 NSUPPORT_MSG = 21, 106 ERX_MSG = 22, 107 FREE_MSG = 23, 108 IPG_MSG = 24, 109 DDI_MSG = 25, 110 DEFAULT_MSG = 26, 111 DISPLAY_MSG = 27, 112 DIAG_MSG = 28, 113 END_TRACE1_MSG = 29, 114 END_TRACE2_MSG = 30, 115 ASSERT_MSG = 31, 116 FRM_MSG = 32, 117 MIF_MSG = 33, 118 LINK_MSG = 34, 119 RESOURCE_MSG = 35, 120 LOOPBACK_MSG = 36, 121 VERBOSE_MSG = 37, 122 MODCTL_MSG = 38, 123 HWCSUM_MSG = 39, 124 CORRUPTION_MSG = 40, 125 EXIT_MSG = 41, 126 DLCAPAB_MSG = 42 127 128} debug_msg_t; 129 130static debug_msg_t eri_debug_level = NO_MSG; 131static debug_msg_t eri_debug_all = NO_MSG; 132 133static char *debug_msg_string[] = { 134 "NONE ", 135 "AUTOCONFIG ", 136 "STREAMS ", 137 "IOCTL ", 138 "PROTO ", 139 "INIT ", 140 "TX ", 141 "RX ", 142 "INTR ", 143 "UNINIT ", 144 "CONFIG ", 145 "PROP ", 146 "ENTER ", 147 "RESUME ", 148 "AUTONEG ", 149 "NAUTONEG ", 150 "FATAL_ERR ", 151 "NFATAL_ERR ", 152 "NDD ", 153 "PHY ", 154 "XCVR ", 155 "NSUPPOR ", 156 "ERX ", 157 "FREE ", 158 "IPG ", 159 "DDI ", 160 "DEFAULT ", 161 "DISPLAY ", 162 "DIAG ", 163 "TRACE1 ", 164 "TRACE2 ", 165 "ASSERT", 166 "FRM ", 167 "MIF ", 168 "LINK ", 169 "RESOURCE", 170 "LOOPBACK", 171 "VERBOSE", 172 "MODCTL", 173 "HWCSUM", 174 "CORRUPTION", 175 "EXIT", 176 "DLCAPAB" 177}; 178 179static void eri_debug_msg(const char *, int, struct eri *, debug_msg_t, 180 const char *, ...); 181 182#define ERI_DEBUG_MSG1(t, f, a) \ 183 eri_debug_msg(__FILE__, __LINE__, (t), (f), (a)); 184 185#define ERI_DEBUG_MSG2(t, f, a, b) \ 186 eri_debug_msg(__FILE__, __LINE__, (t), (f), (a), (b)); 187 188#define ERI_DEBUG_MSG3(t, f, a, b, c) \ 189 eri_debug_msg(__FILE__, __LINE__, (t), (f), (a), (b), (c)); 190 191#define ERI_DEBUG_MSG4(t, f, a, b, c, d) \ 192 eri_debug_msg(__FILE__, __LINE__, (t), (f), (a), (b), (c), (d)); 193 194#define ERI_DEBUG_MSG5(t, f, a, b, c, d, e) \ 195 eri_debug_msg(__FILE__, __LINE__, (t), (f), (a), (b), (c), (d), (e)); 196 197#else 198 199#define ERI_DEBUG_MSG1(t, f, a) 200#define ERI_DEBUG_MSG2(t, f, a, b) 201#define ERI_DEBUG_MSG3(t, f, a, b, c) 202#define ERI_DEBUG_MSG4(t, f, a, b, c, d) 203#define ERI_DEBUG_MSG5(t, f, a, b, c, d, e) 204#define ERI_DEBUG_MSG6(t, f, a, b, c, d, e, g, h) 205#endif 206 207#define ERI_HWCSUM 208 209/* 210 * ERI REV 1.0 has some hardware bugs which doesn't alow it 211 * to function to full features. We define this flag to disable 212 * the features affected by these bugs. 213 */ 214#ifdef ERI_ERI_REV_1_0 215#define RCV_OVRFLOW_CORRUPTION_BUG 216#endif 217 218#define ERI_HDX_BUG_WORKAROUND 219#define ERI_TX_HUNG 220/* 221 * In forced speed mode when changing mode from 10 (force) to 222 * 10 (force), such as changing from 10/half to 10/full, 223 * the driver does not receive a MIF interrupt even though 224 * the XCVR status indicates that the link is up, and this 225 * is probably caused by the link for some reason does not 226 * go down. 227 * 228 * In forced mode, when changing speed/mode from 10 (force) to 229 * 100 (force), the user needs to make sure that the link 230 * partner is in forced mode as well by setting speed to 231 * 100 and the mode to either full or half duplex or 232 * else the link might not come up or come up with a mis-match mode. 233 */ 234#define ERI_10_10_FORCE_SPEED_WORKAROUND 235/* 236 * bits 15:0 of MIF status register contains 0 value 237 * and it is not defined as described on GEM specification 238 */ 239#define ERI_MIF_POLL_STATUS_WORKAROUND 240#define ERI_STRETCH_RCV_BUFFER 241 242#ifdef ERI_STRETCH_RCV_BUFFER 243#undef ERIBUFSIZE 244#define ERIBUFSIZE 3904 245#endif 246 247#ifdef notdef 248#define ERI_DONT_STRIP_CRC 249#endif 250 251#ifdef ERI_HWCSUM 252#define ERI_RCV_CKSUM 253#endif 254 255#ifdef notdef 256#define ERI_SERVICE_ROUTINE 257#endif 258#define ERIHIWAT (128 * 1024) /* hi-water mark */ 259#define ERIRINDEX(i) (i & erip->erirpending_mask) 260#define DONT_FLUSH -1 261 262/* 263 * ddi_dma_sync() a TMD or RMD descriptor. 264 */ 265#define ERI_SYNCIOPB(erip, a, size, who) \ 266 (void) ddi_dma_sync((erip)->md_h, \ 267 ((uintptr_t)(a) - (erip)->iopbkbase), \ 268 (size), \ 269 (who)) 270 271/* ------------------------------------------------------------------------- */ 272/* 273 * Patchable debug flag. 274 * Set this to nonzero to enable error messages. 275 */ 276 277/* 278 * The following parameters may be configured by the user. If they are not 279 * configured by the user, the values will be based on the capabilities of 280 * the transceiver. 281 * The value "ERI_NOTUSR" is ORed with the parameter value to indicate values 282 * which are NOT configured by the user. 283 */ 284 285/* command */ 286 287#define ND_BASE ('N' << 8) /* base */ 288#define ND_GET (ND_BASE + 0) /* Get a value */ 289#define ND_SET (ND_BASE + 1) /* Set a value */ 290 291#define ERI_ND_GET ND_GET 292#define ERI_ND_SET ND_SET 293#define ERI_NOTUSR 0x0f000000 294#define ERI_MASK_1BIT 0x1 295#define ERI_MASK_2BIT 0x3 296#define ERI_MASK_8BIT 0xff 297 298#define param_transceiver (erip->param_arr[0].param_val) 299#define param_linkup (erip->param_arr[1].param_val) 300#define param_speed (erip->param_arr[2].param_val) 301#define param_mode (erip->param_arr[3].param_val) 302#define param_ipg1 (erip->param_arr[4].param_val) 303#define param_ipg2 (erip->param_arr[5].param_val) 304#define param_use_intphy (erip->param_arr[6].param_val) 305#define param_pace_count (erip->param_arr[7].param_val) 306#define param_autoneg (erip->param_arr[8].param_val) 307#define param_anar_100T4 (erip->param_arr[9].param_val) 308 309#define param_anar_100fdx (erip->param_arr[10].param_val) 310#define param_anar_100hdx (erip->param_arr[11].param_val) 311#define param_anar_10fdx (erip->param_arr[12].param_val) 312#define param_anar_10hdx (erip->param_arr[13].param_val) 313#define param_bmsr_ancap (erip->param_arr[14].param_val) 314#define param_bmsr_100T4 (erip->param_arr[15].param_val) 315#define param_bmsr_100fdx (erip->param_arr[16].param_val) 316#define param_bmsr_100hdx (erip->param_arr[17].param_val) 317#define param_bmsr_10fdx (erip->param_arr[18].param_val) 318#define param_bmsr_10hdx (erip->param_arr[19].param_val) 319 320#define param_aner_lpancap (erip->param_arr[20].param_val) 321#define param_anlpar_100T4 (erip->param_arr[21].param_val) 322#define param_anlpar_100fdx (erip->param_arr[22].param_val) 323#define param_anlpar_100hdx (erip->param_arr[23].param_val) 324#define param_anlpar_10fdx (erip->param_arr[24].param_val) 325#define param_anlpar_10hdx (erip->param_arr[25].param_val) 326#define param_lance_mode (erip->param_arr[26].param_val) 327#define param_ipg0 (erip->param_arr[27].param_val) 328#define param_intr_blank_time (erip->param_arr[28].param_val) 329#define param_intr_blank_packets (erip->param_arr[29].param_val) 330#define param_serial_link (erip->param_arr[30].param_val) 331 332#define param_non_serial_link (erip->param_arr[31].param_val) 333#define param_select_link (erip->param_arr[32].param_val) 334#define param_default_link (erip->param_arr[33].param_val) 335#define param_link_in_use (erip->param_arr[34].param_val) 336#define param_anar_asm_dir (erip->param_arr[35].param_val) 337#define param_anar_pause (erip->param_arr[36].param_val) 338#define param_bmsr_asm_dir (erip->param_arr[37].param_val) 339#define param_bmsr_pause (erip->param_arr[38].param_val) 340#define param_anlpar_pauseTX (erip->param_arr[49].param_val) 341#define param_anlpar_pauseRX (erip->param_arr[40].param_val) 342 343/* <<<<<<<<<<<<<<<<<<<<<< Register operations >>>>>>>>>>>>>>>>>>>>> */ 344#define GET_PCSREG(reg) \ 345 ddi_get32(erip->pcsregh, (uint32_t *)&erip->pcsregp->reg) 346#define PUT_PCSREG(reg, value) \ 347 ddi_put32(erip->pcsregh, (uint32_t *)&erip->pcsregp->reg, value) 348#define GET_MIFREG(reg) \ 349 ddi_get32(erip->mifregh, (uint32_t *)&erip->mifregp->reg) 350#define PUT_MIFREG(reg, value) \ 351 ddi_put32(erip->mifregh, (uint32_t *)&erip->mifregp->reg, value) 352#define GET_ETXREG(reg) \ 353 ddi_get32(erip->etxregh, (uint32_t *)&erip->etxregp->reg) 354#define PUT_ETXREG(reg, value) \ 355 ddi_put32(erip->etxregh, (uint32_t *)&erip->etxregp->reg, value) 356#define GET_ERXREG(reg) \ 357 ddi_get32(erip->erxregh, (uint32_t *)&erip->erxregp->reg) 358#define PUT_ERXREG(reg, value) \ 359 ddi_put32(erip->erxregh, (uint32_t *)&erip->erxregp->reg, value) 360#define GET_MACREG(reg) \ 361 ddi_get32(erip->bmacregh, (uint32_t *)&erip->bmacregp->reg) 362#define PUT_MACREG(reg, value) \ 363 ddi_put32(erip->bmacregh, \ 364 (uint32_t *)&erip->bmacregp->reg, value) 365#define GET_GLOBREG(reg) \ 366 ddi_get32(erip->globregh, (uint32_t *)&erip->globregp->reg) 367#define PUT_GLOBREG(reg, value) \ 368 ddi_put32(erip->globregh, \ 369 (uint32_t *)&erip->globregp->reg, value) 370 371#define GET_SWRSTREG(reg) \ 372 ddi_get32(erip->sw_reset_regh, (uint32_t *)erip->sw_reset_reg) 373 374#define PUT_SWRSTREG(reg, value) \ 375 ddi_put32(erip->sw_reset_regh, \ 376 (uint32_t *)erip->sw_reset_reg, value) 377 378/* ********************** Descriptor OPerations ******************** */ 379 380/* <<<<<<<<<<<<<<<<<<<<< for Solaris 2.6 and 2.7 >>>>>>>>>>>>>>>>>>>> */ 381 382/* TMD and RMD Descriptor Operations */ 383#define PUT_TMD(ptr, cookie, len, flags) \ 384 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->tmd_addr, \ 385 cookie.dmac_laddress); \ 386 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->tmd_flags, len | flags) 387 388#define PUT_TMD_FAST(ptr, cookie, len, flags) \ 389 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->tmd_addr, \ 390 cookie.dmac_address); \ 391 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->tmd_flags, len | flags) 392 393#define GET_TMD_FLAGS(ptr) \ 394 ddi_get64(erip->mdm_h, (uint64_t *)&ptr->tmd_flags) 395 396#define PUT_RMD(ptr, cookie) \ 397 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->rmd_addr, \ 398 cookie.dmac_laddress); \ 399 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->rmd_flags, \ 400 (uint64_t)(ERI_BUFSIZE << ERI_RMD_BUFSIZE_SHIFT) | ERI_RMD_OWN) 401 402#define UPDATE_RMD(ptr) \ 403 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->rmd_flags, \ 404 (uint64_t)(ERI_BUFSIZE << ERI_RMD_BUFSIZE_SHIFT) | ERI_RMD_OWN) 405 406#define PUT_RMD_FAST(ptr, cookie) \ 407 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->rmd_addr, \ 408 cookie.dmac_address); \ 409 ddi_put64(erip->mdm_h, (uint64_t *)&ptr->rmd_flags, \ 410 (uint64_t)(ERI_BUFSIZE << ERI_RMD_BUFSIZE_SHIFT) | ERI_RMD_OWN) 411 412#define GET_RMD_FLAGS(ptr) \ 413 ddi_get64(erip->mdm_h, (uint64_t *)&ptr->rmd_flags) 414 415#define ENABLE_TXMAC(erip) \ 416 PUT_MACREG(txcfg, GET_MACREG(txcfg) | BMAC_TXCFG_ENAB) 417 418#define ENABLE_RXMAC(erip) \ 419 PUT_MACREG(rxcfg, GET_MACREG(rxcfg) | BMAC_RXCFG_ENAB) 420 421#define DISABLE_RXMAC(erip) \ 422 PUT_MACREG(rxcfg, GET_MACREG(rxcfg) & ~BMAC_RXCFG_ENAB) 423 424#define DISABLE_TXMAC(erip) \ 425 PUT_MACREG(txcfg, GET_MACREG(txcfg) & ~BMAC_TXCFG_ENAB) 426 427#define ENABLE_MAC(erip) \ 428 ENABLE_RXMAC(erip); \ 429 ENABLE_TXMAC(erip) 430 431#define DISABLE_MAC(erip) \ 432 DISABLE_RXMAC(erip); \ 433 DISABLE_TXMAC(erip) 434 435#define ENABLE_TXDMA(erip) \ 436 PUT_ETXREG(config, GET_ETXREG(config) | GET_CONFIG_TXDMA_EN) 437 438/* TODO : MBE : GER? */ 439#define ENABLE_RXDMA(erip) \ 440 PUT_ERXREG(config, GET_ERXREG(config) | GET_CONFIG_RXDMA_EN) 441 442 443/* 444 * Ether-type is specifically big-endian, but data region is unknown endian 445 * Ether-type lives at offset 12 from the start of the packet. 446 */ 447 448#define get_ether_type(ptr) \ 449 (((((uint8_t *)ptr)[12] << 8) | (((uint8_t *)ptr)[13]))) 450 451#endif /* _KERNEL */ 452 453#ifdef __cplusplus 454} 455#endif 456 457#endif /* _SYS_ERI_COMMON_H */ 458