1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25#ifndef _SYS_CONTROLREGS_H 26#define _SYS_CONTROLREGS_H 27 28#ifndef _ASM 29#include <sys/types.h> 30#endif 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36/* 37 * This file describes the x86 architecture control registers which 38 * are part of the privileged architecture. 39 * 40 * Many of these definitions are shared between IA-32-style and 41 * AMD64-style processors. 42 */ 43 44/* CR0 Register */ 45 46#define CR0_PG 0x80000000 /* paging enabled */ 47#define CR0_CD 0x40000000 /* cache disable */ 48#define CR0_NW 0x20000000 /* not writethrough */ 49#define CR0_AM 0x00040000 /* alignment mask */ 50#define CR0_WP 0x00010000 /* write protect */ 51#define CR0_NE 0x00000020 /* numeric error */ 52#define CR0_ET 0x00000010 /* extension type */ 53#define CR0_TS 0x00000008 /* task switch */ 54#define CR0_EM 0x00000004 /* emulation */ 55#define CR0_MP 0x00000002 /* monitor coprocessor */ 56#define CR0_PE 0x00000001 /* protection enabled */ 57 58/* XX64 eliminate these compatibility defines */ 59 60#define CR0_CE CR0_CD 61#define CR0_WT CR0_NW 62 63#define FMT_CR0 \ 64 "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe" 65 66/* 67 * Set the FPU-related control bits to explain to the processor that 68 * we're managing FPU state: 69 * - set monitor coprocessor (allow TS bit to control FPU) 70 * - set numeric exception (disable IGNNE# mechanism) 71 * - set task switch (#nm on first fp instruction) 72 * - clear emulate math bit (cause we're not emulating!) 73 */ 74#define CR0_ENABLE_FPU_FLAGS(cr) \ 75 (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM) 76 77/* 78 * Set the FPU-related control bits to explain to the processor that 79 * we're -not- managing FPU state: 80 * - set emulate (all fp instructions cause #nm) 81 * - clear monitor coprocessor (so fwait/wait doesn't #nm) 82 */ 83#define CR0_DISABLE_FPU_FLAGS(cr) \ 84 (((cr) | CR0_EM) & (uint32_t)~CR0_MP) 85 86/* CR3 Register */ 87 88#define CR3_PCD 0x00000010 /* cache disable */ 89#define CR3_PWT 0x00000008 /* write through */ 90 91#define FMT_CR3 "\20\5pcd\4pwt" 92 93/* CR4 Register */ 94 95#define CR4_VME 0x0001 /* virtual-8086 mode extensions */ 96#define CR4_PVI 0x0002 /* protected-mode virtual interrupts */ 97#define CR4_TSD 0x0004 /* time stamp disable */ 98#define CR4_DE 0x0008 /* debugging extensions */ 99#define CR4_PSE 0x0010 /* page size extensions */ 100#define CR4_PAE 0x0020 /* physical address extension */ 101#define CR4_MCE 0x0040 /* machine check enable */ 102#define CR4_PGE 0x0080 /* page global enable */ 103#define CR4_PCE 0x0100 /* perf-monitoring counter enable */ 104#define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */ 105#define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */ 106 /* 0x0800 reserved */ 107 /* 0x1000 reserved */ 108#define CR4_VMXE 0x2000 109#define CR4_SMXE 0x4000 110#define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */ 111 112#define FMT_CR4 \ 113 "\20\23osxsav\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge" \ 114 "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" 115 116/* 117 * Enable the SSE-related control bits to explain to the processor that 118 * we're managing XMM state and exceptions 119 */ 120#define CR4_ENABLE_SSE_FLAGS(cr) \ 121 ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT) 122 123/* 124 * Disable the SSE-related control bits to explain to the processor 125 * that we're NOT managing XMM state 126 */ 127#define CR4_DISABLE_SSE_FLAGS(cr) \ 128 ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT)) 129 130/* Intel's SYSENTER configuration registers */ 131 132#define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */ 133#define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ 134#define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ 135 136/* Intel's microcode registers */ 137#define MSR_INTC_UCODE_WRITE 0x79 /* microcode write */ 138#define MSR_INTC_UCODE_REV 0x8b /* microcode revision */ 139#define INTC_UCODE_REV_SHIFT 32 /* Bits 63:32 */ 140 141/* Intel's platform identification */ 142#define MSR_INTC_PLATFORM_ID 0x17 143#define INTC_PLATFORM_ID_SHIFT 50 /* Bit 52:50 */ 144#define INTC_PLATFORM_ID_MASK 0x7 145 146/* AMD's EFER register */ 147 148#define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ 149 150#define AMD_EFER_FFXSR 0x4000 /* fast fxsave/fxrstor */ 151#define AMD_EFER_SVME 0x1000 /* svm enable */ 152#define AMD_EFER_NXE 0x0800 /* no-execute enable */ 153#define AMD_EFER_LMA 0x0400 /* long mode active (read-only) */ 154#define AMD_EFER_LME 0x0100 /* long mode enable */ 155#define AMD_EFER_SCE 0x0001 /* system call extensions */ 156 157#define FMT_AMD_EFER \ 158 "\20\17ffxsr\15svme\14nxe\13lma\11lme\1sce" 159 160/* AMD's SYSCFG register */ 161 162#define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */ 163 164#define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */ 165#define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */ 166#define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */ 167#define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */ 168 169#define FMT_AMD_SYSCFG \ 170 "\20\26tom2\25mvdm\24mfdm\23mfde" 171 172/* AMD's syscall/sysret MSRs */ 173 174#define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */ 175#define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */ 176#define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */ 177#define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */ 178 179/* AMD's FS.base and GS.base MSRs */ 180 181#define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */ 182#define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ 183#define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */ 184#define MSR_AMD_TSCAUX 0xc0000103 /* %ecx value on rdtscp insn */ 185 186/* AMD's configuration MSRs, weakly documented in the revision guide */ 187 188#define MSR_AMD_DC_CFG 0xc0011022 189 190#define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3) 191#define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10) 192 193/* AMD's HWCR MSR */ 194 195#define MSR_AMD_HWCR 0xc0010015 196 197#define AMD_HWCR_TLBCACHEDIS (UINT64_C(1) << 3) 198#define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */ 199#define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */ 200 201/* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */ 202 203#define MSR_AMD_NB_CFG 0xc001001f 204 205#define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20) 206#define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32) 207 208#define MSR_AMD_BU_CFG 0xc0011023 209 210#define AMD_BU_CFG_E298 (UINT64_C(1) << 1) 211 212/* AMD's osvw MSRs */ 213#define MSR_AMD_OSVW_ID_LEN 0xc0010140 214#define MSR_AMD_OSVW_STATUS 0xc0010141 215 216 217#define OSVW_ID_LEN_MASK 0xffffULL 218#define OSVW_ID_CNT_PER_MSR 64 219 220/* 221 * Enable PCI Extended Configuration Space (ECS) on Greyhound 222 */ 223#define AMD_GH_NB_CFG_EN_ECS (UINT64_C(1) << 46) 224 225/* AMD microcode patch loader */ 226#define MSR_AMD_PATCHLEVEL 0x8b 227#define MSR_AMD_PATCHLOADER 0xc0010020 228 229#ifdef __cplusplus 230} 231#endif 232 233#endif /* !_SYS_CONTROLREGS_H */ 234