1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#ifndef _NB_LOG_H
28#define	_NB_LOG_H
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34#include <sys/cpu_module.h>
35#include "nb5000.h"
36
37#define	NB_MAX_ERRORS	4
38
39/* North Bridge front side bus error registers */
40
41typedef struct nb_fsb_regs {
42	uint8_t	fsb;		/* cpu slot */
43	uint8_t ferr_fat_fsb;
44	uint8_t nerr_fat_fsb;
45	uint8_t ferr_nf_fsb;
46	uint8_t nerr_nf_fsb;
47	uint64_t nrecfsb_addr;
48	uint32_t nrecfsb;
49	uint32_t recfsb;
50} nb_fsb_regs_t;
51
52/* PCI express ESI (South Bridge) error registers */
53
54typedef struct nb_pex_regs {
55	uint8_t pex;		/* pci express slot */
56	uint32_t pex_fat_ferr;
57	uint32_t pex_fat_nerr;
58	uint32_t pex_nf_corr_ferr;
59	uint32_t pex_nf_corr_nerr;
60	uint32_t uncerrsev;		/* uncorrectable error severity */
61	uint32_t rperrsts;		/* root error status */
62	uint32_t rperrsid;		/* error source identification */
63	uint32_t uncerrsts;		/* uncorrectable error status */
64	uint32_t aerrcapctrl;	/* advanced error capabilities and control */
65	uint32_t corerrsts;	/* correctable error status */
66	uint16_t pexdevsts;	/* pci express device status */
67} nb_pex_regs_t;
68
69/* North Bridge memory controller hub internal error registers */
70
71typedef struct nb_int {
72	uint16_t ferr_fat_int;	/* first fatal error */
73	uint16_t ferr_nf_int;	/* first non-fatal error */
74	uint16_t nerr_fat_int;	/* next fatal error */
75	uint16_t nerr_nf_int;	/* next non-fatal error */
76	uint32_t nrecint;	/* non recoverable error log */
77	uint32_t recint;	/* recoverable error log */
78	uint64_t nrecsf;	/* non recoverable control information */
79	uint64_t recsf;		/* recoverable control information */
80} nb_int_t;
81
82/* memory errors */
83
84typedef struct nb_fat_fbd {
85	uint32_t ferr_fat_fbd;	/* fb-dimm first fatal error */
86	uint32_t nerr_fat_fbd;	/* fb-dimm next fatal error */
87	uint32_t nrecmema;	/* non recoverable memory error log */
88	uint32_t nrecmemb;	/* non recoverable memory error log */
89	uint32_t nrecfglog;	/* non recoverable dimm configuration */
90	uint32_t nrecfbda;	/* non recoverable dimm log A */
91	uint32_t nrecfbdb;	/* non recoverable dimm log B */
92	uint32_t nrecfbdc;	/* non recoverable dimm log C */
93	uint32_t nrecfbdd;	/* non recoverable dimm log D */
94	uint32_t nrecfbde;	/* non recoverable dimm log E */
95	uint32_t nrecfbdf;	/* non recoverable dimm log F */
96	uint32_t spcpc;		/* spare copy control */
97	uint8_t spcps;		/* spare copy status */
98	uint32_t uerrcnt;	/* uncorrectable error count */
99	uint32_t uerrcnt_last;	/* saved copy of uncorrectable error count */
100	uint32_t badrama;	/* bad dram marker A */
101	uint16_t badramb;	/* bad dram marker B */
102	uint32_t badcnt;	/* bad dram counter */
103} nb_fat_fbd_t;
104
105typedef struct nb_nf_fbd {
106	uint32_t ferr_nf_fbd;	/* fb-dimm first non-fatal error */
107	uint32_t nerr_nf_fbd;	/* fb-dimm next non-fatal error */
108	uint32_t redmemb;	/* recoverable dimm data error log */
109	uint32_t recmema;	/* recoverable memory error log A */
110	uint32_t recmemb;	/* recoverable memory error log B */
111	uint32_t recfglog;	/* recoverable dimm configuration */
112	uint32_t recfbda;	/* recoverable dimm log A */
113	uint32_t recfbdb;	/* recoverable dimm log B */
114	uint32_t recfbdc;	/* recoverable dimm log C */
115	uint32_t recfbdd;	/* recoverable dimm log D */
116	uint32_t recfbde;	/* recoverable dimm log E */
117	uint32_t recfbdf;	/* recoverable dimm log F */
118	uint32_t spcpc;		/* spare copy control */
119	uint8_t spcps;		/* spare copy status */
120	uint32_t cerrcnta;	/* correctable error count A */
121	uint32_t cerrcntb;	/* correctable error count B */
122	uint32_t cerrcntc;	/* correctable error count C */
123	uint32_t cerrcntd;	/* correctable error count D */
124	uint32_t cerrcnta_last;	/* saved copy of correctable error count A */
125	uint32_t cerrcntb_last;	/* saved copy of correctable error count B */
126	uint32_t cerrcntc_last;	/* saved copy of correctable error count C */
127	uint32_t cerrcntd_last;	/* saved copy of correctable error count D */
128	uint32_t badrama;	/* bad dram marker A */
129	uint16_t badramb;	/* bad dram marker B */
130	uint32_t badcnt;	/* bad dram counter */
131} nb_nf_fbd_t;
132
133typedef struct nb_nf_mem {
134				/* Memory registers */
135	uint32_t ferr_nf_mem;	/* MC first non-fatal error */
136	uint32_t nerr_nf_mem;	/* MC next non-fatal error */
137	uint32_t nrecmema;	/* non-recoverable memory error log A */
138	uint32_t nrecmemb;	/* non-recoverable memory error log B */
139	uint32_t redmema;	/* recoverable memory data error log A */
140	uint32_t redmemb;	/* recoverable memory data error log B */
141	uint32_t recmema;	/* recoverable memory error log A */
142	uint32_t recmemb;	/* recoverable memory error log B */
143
144				/* Spare rank */
145	uint32_t spcpc;		/* spare copy control */
146	uint8_t spcps;		/* spare copy status */
147
148				/* RAS */
149	uint32_t cerrcnt;	/* correctable error count A */
150	uint32_t cerrcnt_ext;	/* correctable error count B */
151	uint32_t cerrcnt_last;	/* correctable error count A */
152	uint32_t cerrcnt_ext_last;	/* correctable error count B */
153	uint32_t badram;	/* bad dram marker */
154	uint32_t badcnt;	/* bad dram counter */
155	uint32_t validlog;	/* valid log markers */
156} nb_nf_mem_t;
157
158typedef struct nb_dma {
159	uint16_t pcists;
160	uint16_t pexdevsts;
161} nb_dma_t;
162
163typedef struct nb_thr {
164	uint8_t ferr_fat_thr;
165	uint8_t ferr_nf_thr;
166	uint8_t nerr_fat_thr;
167	uint8_t nerr_nf_thr;
168	uint8_t ctsts;
169	uint16_t thrtsts;
170} nb_thr_t;
171
172typedef struct nb_regs {
173	int flag;
174	uint32_t chipset;
175	uint64_t ferr;
176	uint32_t nerr;
177	union {
178		nb_fsb_regs_t fsb_regs;
179		nb_pex_regs_t pex_regs;
180		nb_int_t int_regs;
181		nb_fat_fbd_t fat_fbd_regs;
182		nb_nf_fbd_t nf_fbd_regs;
183		nb_nf_mem_t nf_mem_regs;
184		nb_dma_t dma_regs;
185		nb_thr_t thr_regs;
186	} nb;
187} nb_regs_t;
188
189#define	NB_REG_LOG_FREE		0
190#define	NB_REG_LOG_FSB		1
191#define	NB_REG_LOG_PEX		2
192#define	NB_REG_LOG_INT		3
193#define	NB_REG_LOG_FAT_FBD	4
194#define	NB_REG_LOG_NF_FBD	5
195#define	NB_REG_LOG_DMA		6
196#define	NB_REG_LOG_THR		7
197#define	NB_REG_LOG_NF_MEM	8
198
199typedef struct nb_logout {
200	uint64_t acl_timestamp;
201	char *type;
202	nb_regs_t nb_regs;
203} nb_logout_t;
204
205typedef struct nb_mem_scatchpad {
206	int intel_error_list;		/* error number in Chipset Error List */
207	int branch;
208	int channel;
209	int rank;
210	int dimm;
211	int bank;
212	int cas;
213	int ras;
214	uint64_t offset;
215	uint64_t pa;
216} nb_mem_scatchpad_t;
217
218typedef union nb_scatchpad {
219	nb_mem_scatchpad_t ms;
220	int intel_error_list;		/* error number in Chipset Error List */
221} nb_scatchpad_t;
222
223typedef struct nb_dimm {
224	uint64_t dimm_size;
225	uint8_t mtr_present;
226	uint8_t start_rank;		/* id of the 1st rank */
227	uint8_t nranks;			/* number of ranks */
228	uint8_t nbanks;
229	uint8_t ncolumn;
230	uint8_t nrow;
231	uint8_t width;
232	uint8_t manufacture_location;
233	uint8_t manufacture_week;
234	uint8_t manufacture_year;	/* years from 2000 */
235	uint16_t manufacture_id;
236	uint32_t serial_number;
237	char part_number[16];
238	char revision[2];
239	char label[64];
240} nb_dimm_t;
241
242typedef struct bank_select {
243	uint64_t base;
244	uint64_t limit;
245	uint8_t	way[2];
246} bank_select_t;
247
248typedef struct rank_select {
249	uint64_t base;
250	uint64_t limit;
251	uint32_t hole_base;
252	uint32_t hole_size;
253	uint8_t	rank[4];
254	uint8_t interleave;
255	uint8_t branch_interleave;
256} rank_select_t;
257
258enum nb_memory_mode { NB_MEMORY_SINGLE_CHANNEL, NB_MEMORY_NORMAL,
259    NB_MEMORY_SPARE_RANK, NB_MEMORY_MIRROR };
260
261extern int nb_5000_memory_controller;
262extern int nb_number_memory_controllers;
263extern int nb_channels_per_branch;
264extern int nb_dimms_per_channel;
265
266extern nb_dimm_t **nb_dimms;
267extern uint32_t nb_chipset;
268
269extern int nb_init(void);
270extern int nb_dev_init(void);
271extern void nb_dev_reinit(void);
272extern void nb_unload(void);
273extern void nb_dev_unload(void);
274extern uint32_t top_of_low_memory;
275extern bank_select_t nb_banks[NB_MAX_MEM_BRANCH_SELECT];
276extern rank_select_t nb_ranks[NB_5000_MAX_MEM_CONTROLLERS]
277	[NB_MAX_MEM_RANK_SELECT];
278extern uint8_t spare_rank[NB_5000_MAX_MEM_CONTROLLERS];
279extern enum nb_memory_mode nb_mode;
280extern int nb_rank2dimm(int, int);
281
282extern int inb_mc_register(cmi_hdl_t, void *, void *, void *);
283extern void nb_scrubber_enable(void);
284extern void nb_error_trap(cmi_hdl_t, boolean_t, boolean_t);
285
286extern void nb_pci_cfg_setup(dev_info_t *);
287extern void nb_pci_cfg_free(void);
288
289extern void *ras_regs;
290
291extern uint8_t nb_pci_getb(int, int, int, int, int *);
292extern uint16_t nb_pci_getw(int, int, int, int, int *);
293extern uint32_t nb_pci_getl(int, int, int, int, int *);
294extern void nb_pci_putb(int, int, int, int, uint8_t);
295extern void nb_pci_putw(int, int, int, int, uint16_t);
296extern void nb_pci_putl(int, int, int, int, uint32_t);
297
298extern void nb_fsb_mask_mc(int, uint16_t);
299extern void nb_fbd_mask_mc(uint32_t);
300extern void nb_mem_mask_mc(uint32_t);
301extern void nb_int_mask_mc(uint32_t);
302extern void nb_thr_mask_mc(uint16_t);
303extern void nb_mask_mc_reset(void);
304
305extern int nb_mask_mc_set;
306
307extern errorq_t *nb_queue;
308extern kmutex_t nb_mutex;
309
310extern void nb_drain(void *, const void *, const errorq_elem_t *);
311extern void nb_used_spare_rank(int, int);
312
313extern uint_t nb_config_gen;
314
315#ifdef __cplusplus
316}
317#endif
318
319#endif /* _NB_LOG_H */
320