1/* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5/* 6 * radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 7 * 8 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 9 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 10 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 11 * All rights reserved. 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice (including the next 21 * paragraph) shall be included in all copies or substantial portions of the 22 * Software. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 26 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 27 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 28 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 29 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 30 * DEALINGS IN THE SOFTWARE. 31 * 32 * Authors: 33 * Kevin E. Martin <martin@valinux.com> 34 * Gareth Hughes <gareth@valinux.com> 35 * Keith Whitwell <keith@tungstengraphics.com> 36 */ 37 38#pragma ident "%Z%%M% %I% %E% SMI" 39 40#ifndef __RADEON_DRM_H__ 41#define __RADEON_DRM_H__ 42 43/* 44 * WARNING: If you change any of these defines, make sure to change the 45 * defines in the X server file (radeon_sarea.h) 46 */ 47#ifndef __RADEON_SAREA_DEFINES__ 48#define __RADEON_SAREA_DEFINES__ 49 50/* 51 * Old style state flags, required for sarea interface (1.1 and 1.2 52 * clears) and 1.2 drm_vertex2 ioctl. 53 */ 54#define RADEON_UPLOAD_CONTEXT 0x00000001 55#define RADEON_UPLOAD_VERTFMT 0x00000002 56#define RADEON_UPLOAD_LINE 0x00000004 57#define RADEON_UPLOAD_BUMPMAP 0x00000008 58#define RADEON_UPLOAD_MASKS 0x00000010 59#define RADEON_UPLOAD_VIEWPORT 0x00000020 60#define RADEON_UPLOAD_SETUP 0x00000040 61#define RADEON_UPLOAD_TCL 0x00000080 62#define RADEON_UPLOAD_MISC 0x00000100 63#define RADEON_UPLOAD_TEX0 0x00000200 64#define RADEON_UPLOAD_TEX1 0x00000400 65#define RADEON_UPLOAD_TEX2 0x00000800 66#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 67#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 68#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 69#define RADEON_UPLOAD_CLIPRECTS 0x00008000 70 /* handled client-side */ 71#define RADEON_REQUIRE_QUIESCENCE 0x00010000 72#define RADEON_UPLOAD_ZBIAS 0x00020000 73 /* version 1.2 and newer */ 74#define RADEON_UPLOAD_ALL 0x003effff 75#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 76 77/* 78 * New style per-packet identifiers for use in cmd_buffer ioctl with 79 * the RADEON_EMIT_PACKET command. Comments relate new packets to old 80 * state bits and the packet size: 81 */ 82#define RADEON_EMIT_PP_MISC 0 /* context/7 */ 83#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 84#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 85#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 86#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 87#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 88#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 89#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 90#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 91#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 92#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 93#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 94#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 95#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 96#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 97#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 98#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 99#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 100#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 101#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 102#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 103#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 104#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 105#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 106#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 107#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 108#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 109#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 110#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 111#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 112#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 113#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 114#define R200_EMIT_VAP_CTL 32 /* vap/1 */ 115#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 116#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 117#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 118#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 119#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 120#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 121#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 122#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 123#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 124#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 125#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 126#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 127#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 128#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 129#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 130#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 131#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 132#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 133#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 134#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 135#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 136#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 137#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 138#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 139#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 140#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 141#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 142#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 143#define R200_EMIT_PP_CUBIC_FACES_0 61 144#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 145#define R200_EMIT_PP_CUBIC_FACES_1 63 146#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 147#define R200_EMIT_PP_CUBIC_FACES_2 65 148#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 149#define R200_EMIT_PP_CUBIC_FACES_3 67 150#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 151#define R200_EMIT_PP_CUBIC_FACES_4 69 152#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 153#define R200_EMIT_PP_CUBIC_FACES_5 71 154#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 155#define RADEON_EMIT_PP_TEX_SIZE_0 73 156#define RADEON_EMIT_PP_TEX_SIZE_1 74 157#define RADEON_EMIT_PP_TEX_SIZE_2 75 158#define R200_EMIT_RB3D_BLENDCOLOR 76 159#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 160#define RADEON_EMIT_PP_CUBIC_FACES_0 78 161#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 162#define RADEON_EMIT_PP_CUBIC_FACES_1 80 163#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 164#define RADEON_EMIT_PP_CUBIC_FACES_2 82 165#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 166#define R200_EMIT_PP_TRI_PERF_CNTL 84 167#define R200_EMIT_PP_AFS_0 85 168#define R200_EMIT_PP_AFS_1 86 169#define R200_EMIT_ATF_TFACTOR 87 170#define R200_EMIT_PP_TXCTLALL_0 88 171#define R200_EMIT_PP_TXCTLALL_1 89 172#define R200_EMIT_PP_TXCTLALL_2 90 173#define R200_EMIT_PP_TXCTLALL_3 91 174#define R200_EMIT_PP_TXCTLALL_4 92 175#define R200_EMIT_PP_TXCTLALL_5 93 176#define R200_EMIT_VAP_PVS_CNTL 94 177#define RADEON_MAX_STATE_PACKETS 95 178 179/* 180 * Commands understood by cmd_buffer ioctl. More can be added but 181 * obviously these can't be removed or changed: 182 */ 183#define RADEON_CMD_PACKET 1 184 /* emit one of the register packets above */ 185#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 186#define RADEON_CMD_VECTORS 3 /* emit vector data */ 187#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 188#define RADEON_CMD_PACKET3 5 /* emit hw packet */ 189#define RADEON_CMD_PACKET3_CLIP 6 190 /* emit hw packet wrapped in cliprects */ 191#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 192 193/* 194 * emit hw wait commands -- note: 195 * doesn't make the cpu wait, just 196 * the graphics hardware 197 */ 198#define RADEON_CMD_WAIT 8 199 200#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 201typedef union { 202 int i; 203 struct { 204 unsigned char cmd_type, pad0, pad1, pad2; 205 } header; 206 struct { 207 unsigned char cmd_type, packet_id, pad0, pad1; 208 } packet; 209 struct { 210 unsigned char cmd_type, offset, stride, count; 211 } scalars; 212 struct { 213 unsigned char cmd_type, offset, stride, count; 214 } vectors; 215 struct { 216 unsigned char cmd_type, addr_lo, addr_hi, count; 217 } veclinear; 218 struct { 219 unsigned char cmd_type, buf_idx, pad0, pad1; 220 } dma; 221 struct { 222 unsigned char cmd_type, flags, pad0, pad1; 223 } wait; 224} drm_radeon_cmd_header_t; 225 226#define RADEON_WAIT_2D 0x1 227#define RADEON_WAIT_3D 0x2 228 229/* Allowed parameters for R300_CMD_PACKET3 */ 230#define R300_CMD_PACKET3_CLEAR 0 231#define R300_CMD_PACKET3_RAW 1 232 233/* 234 * Commands understood by cmd_buffer ioctl for R300. 235 * The interface has not been stabilized, so some of these may be removed 236 * and eventually reordered before stabilization. 237 */ 238#define R300_CMD_PACKET0 1 239#define R300_CMD_VPU 2 /* emit vertex program upload */ 240#define R300_CMD_PACKET3 3 /* emit a packet3 */ 241 242/* emit sequence ending 3d rendering */ 243#define R300_CMD_END3D 4 244 245#define R300_CMD_CP_DELAY 5 246#define R300_CMD_DMA_DISCARD 6 247#define R300_CMD_WAIT 7 248#define R300_WAIT_2D 0x1 249#define R300_WAIT_3D 0x2 250#define R300_WAIT_2D_CLEAN 0x3 251#define R300_WAIT_3D_CLEAN 0x4 252#define R300_CMD_SCRATCH 8 253/* 254 * sys/user.h defines u 255 */ 256typedef union { 257 unsigned int u; 258 struct { 259 unsigned char cmd_type, pad0, pad1, pad2; 260 } header; 261 struct { 262 unsigned char cmd_type, count, reglo, reghi; 263 } packet0; 264 struct { 265 unsigned char cmd_type, count, adrlo, adrhi; 266 } vpu; 267 struct { 268 unsigned char cmd_type, packet, pad0, pad1; 269 } packet3; 270 struct { 271 unsigned char cmd_type, packet; 272 unsigned short count; /* amount of packet2 to emit */ 273 } delay; 274 struct { 275 unsigned char cmd_type, buf_idx, pad0, pad1; 276 } dma; 277 struct { 278 unsigned char cmd_type, flags, pad0, pad1; 279 } wait; 280 struct { 281 unsigned char cmd_type, reg, n_bufs, flags; 282 } scratch; 283} drm_r300_cmd_header_t; 284 285#define RADEON_FRONT 0x1 286#define RADEON_BACK 0x2 287#define RADEON_DEPTH 0x4 288#define RADEON_STENCIL 0x8 289#define RADEON_CLEAR_FASTZ 0x80000000 290#define RADEON_USE_HIERZ 0x40000000 291#define RADEON_USE_COMP_ZBUF 0x20000000 292 293/* Primitive types */ 294#define RADEON_POINTS 0x1 295#define RADEON_LINES 0x2 296#define RADEON_LINE_STRIP 0x3 297#define RADEON_TRIANGLES 0x4 298#define RADEON_TRIANGLE_FAN 0x5 299#define RADEON_TRIANGLE_STRIP 0x6 300 301/* Vertex/indirect buffer size */ 302#define RADEON_BUFFER_SIZE 65536 303 304/* Byte offsets for indirect buffer data */ 305#define RADEON_INDEX_PRIM_OFFSET 20 306 307#define RADEON_SCRATCH_REG_OFFSET 32 308 309#define RADEON_NR_SAREA_CLIPRECTS 12 310 311/* 312 * There are 2 heaps (local/GART). Each region within a heap is a 313 * minimum of 64k, and there are at most 64 of them per heap. 314 */ 315#define RADEON_LOCAL_TEX_HEAP 0 316#define RADEON_GART_TEX_HEAP 1 317#define RADEON_NR_TEX_HEAPS 2 318#define RADEON_NR_TEX_REGIONS 64 319#define RADEON_LOG_TEX_GRANULARITY 16 320 321#define RADEON_MAX_TEXTURE_LEVELS 12 322#define RADEON_MAX_TEXTURE_UNITS 3 323 324#define RADEON_MAX_SURFACES 8 325 326/* 327 * Blits have strict offset rules. All blit offset must be aligned on 328 * a 1K-byte boundary. 329 */ 330#define RADEON_OFFSET_SHIFT 10 331#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 332#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 333 334#endif /* __RADEON_SAREA_DEFINES__ */ 335 336typedef struct { 337 unsigned int red; 338 unsigned int green; 339 unsigned int blue; 340 unsigned int alpha; 341} radeon_color_regs_t; 342 343typedef struct { 344 /* Context state */ 345 unsigned int pp_misc; /* 0x1c14 */ 346 unsigned int pp_fog_color; 347 unsigned int re_solid_color; 348 unsigned int rb3d_blendcntl; 349 unsigned int rb3d_depthoffset; 350 unsigned int rb3d_depthpitch; 351 unsigned int rb3d_zstencilcntl; 352 353 unsigned int pp_cntl; /* 0x1c38 */ 354 unsigned int rb3d_cntl; 355 unsigned int rb3d_coloroffset; 356 unsigned int re_width_height; 357 unsigned int rb3d_colorpitch; 358 unsigned int se_cntl; 359 360 /* Vertex format state */ 361 unsigned int se_coord_fmt; /* 0x1c50 */ 362 363 /* Line state */ 364 unsigned int re_line_pattern; /* 0x1cd0 */ 365 unsigned int re_line_state; 366 367 unsigned int se_line_width; /* 0x1db8 */ 368 369 /* Bumpmap state */ 370 unsigned int pp_lum_matrix; /* 0x1d00 */ 371 372 unsigned int pp_rot_matrix_0; /* 0x1d58 */ 373 unsigned int pp_rot_matrix_1; 374 375 /* Mask state */ 376 unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 377 unsigned int rb3d_ropcntl; 378 unsigned int rb3d_planemask; 379 380 /* Viewport state */ 381 unsigned int se_vport_xscale; /* 0x1d98 */ 382 unsigned int se_vport_xoffset; 383 unsigned int se_vport_yscale; 384 unsigned int se_vport_yoffset; 385 unsigned int se_vport_zscale; 386 unsigned int se_vport_zoffset; 387 388 /* Setup state */ 389 unsigned int se_cntl_status; /* 0x2140 */ 390 391 /* Misc state */ 392 unsigned int re_top_left; /* 0x26c0 */ 393 unsigned int re_misc; 394} drm_radeon_context_regs_t; 395 396typedef struct { 397 /* Zbias state */ 398 unsigned int se_zbias_factor; /* 0x1dac */ 399 unsigned int se_zbias_constant; 400} drm_radeon_context2_regs_t; 401 402/* Setup registers for each texture unit */ 403typedef struct { 404 unsigned int pp_txfilter; 405 unsigned int pp_txformat; 406 unsigned int pp_txoffset; 407 unsigned int pp_txcblend; 408 unsigned int pp_txablend; 409 unsigned int pp_tfactor; 410 unsigned int pp_border_color; 411} drm_radeon_texture_regs_t; 412 413typedef struct { 414 unsigned int start; 415 unsigned int finish; 416 unsigned int prim:8; 417 unsigned int stateidx:8; 418 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 419 unsigned int vc_format; /* vertex format */ 420} drm_radeon_prim_t; 421 422typedef struct { 423 drm_radeon_context_regs_t context; 424 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 425 drm_radeon_context2_regs_t context2; 426 unsigned int dirty; 427} drm_radeon_state_t; 428 429typedef struct { 430 /* 431 * The channel for communication of state information to the 432 * kernel on firing a vertex buffer with either of the 433 * obsoleted vertex/index ioctls. 434 */ 435 drm_radeon_context_regs_t context_state; 436 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 437 unsigned int dirty; 438 unsigned int vertsize; 439 unsigned int vc_format; 440 441 /* The current cliprects, or a subset thereof. */ 442 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS]; 443 unsigned int nbox; 444 445 /* Counters for client-side throttling of rendering clients. */ 446 unsigned int last_frame; 447 unsigned int last_dispatch; 448 unsigned int last_clear; 449 450 drm_tex_region_t 451 tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1]; 452 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 453 int ctx_owner; 454 int pfState; /* number of 3d windows (0,1,2ormore) */ 455 int pfCurrentPage; /* which buffer is being displayed? */ 456 int crtc2_base; /* CRTC2 frame offset */ 457 int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 458} drm_radeon_sarea_t; 459 460/* 461 * WARNING: If you change any of these defines, make sure to change the 462 * defines in the Xserver file (xf86drmRadeon.h) 463 * 464 * KW: actually it's illegal to change any of this (backwards compatibility). 465 */ 466 467/* 468 * Radeon specific ioctls 469 * The device specific ioctl range is 0x40 to 0x79. 470 */ 471#define DRM_RADEON_CP_INIT 0x00 472#define DRM_RADEON_CP_START 0x01 473#define DRM_RADEON_CP_STOP 0x02 474#define DRM_RADEON_CP_RESET 0x03 475#define DRM_RADEON_CP_IDLE 0x04 476#define DRM_RADEON_RESET 0x05 477#define DRM_RADEON_FULLSCREEN 0x06 478#define DRM_RADEON_SWAP 0x07 479#define DRM_RADEON_CLEAR 0x08 480#define DRM_RADEON_VERTEX 0x09 481#define DRM_RADEON_INDICES 0x0A 482#define DRM_RADEON_NOT_USED 483#define DRM_RADEON_STIPPLE 0x0C 484#define DRM_RADEON_INDIRECT 0x0D 485#define DRM_RADEON_TEXTURE 0x0E 486#define DRM_RADEON_VERTEX2 0x0F 487#define DRM_RADEON_CMDBUF 0x10 488#define DRM_RADEON_GETPARAM 0x11 489#define DRM_RADEON_FLIP 0x12 490#define DRM_RADEON_ALLOC 0x13 491#define DRM_RADEON_FREE 0x14 492#define DRM_RADEON_INIT_HEAP 0x15 493#define DRM_RADEON_IRQ_EMIT 0x16 494#define DRM_RADEON_IRQ_WAIT 0x17 495#define DRM_RADEON_CP_RESUME 0x18 496#define DRM_RADEON_SETPARAM 0x19 497#define DRM_RADEON_SURF_ALLOC 0x1a 498#define DRM_RADEON_SURF_FREE 0x1b 499 500#define DRM_IOCTL_RADEON_CP_INIT \ 501 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 502#define DRM_IOCTL_RADEON_CP_START \ 503 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START) 504#define DRM_IOCTL_RADEON_CP_STOP \ 505 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 506#define DRM_IOCTL_RADEON_CP_RESET \ 507 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 508#define DRM_IOCTL_RADEON_CP_IDLE \ 509 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 510#define DRM_IOCTL_RADEON_RESET \ 511 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET) 512#define DRM_IOCTL_RADEON_FULLSCREEN \ 513 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, \ 514 drm_radeon_fullscreen_t) 515#define DRM_IOCTL_RADEON_SWAP \ 516 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP) 517#define DRM_IOCTL_RADEON_CLEAR \ 518 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 519#define DRM_IOCTL_RADEON_VERTEX \ 520 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 521#define DRM_IOCTL_RADEON_INDICES \ 522 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 523#define DRM_IOCTL_RADEON_STIPPLE \ 524 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 525#define DRM_IOCTL_RADEON_INDIRECT \ 526 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 527#define DRM_IOCTL_RADEON_TEXTURE \ 528 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 529#define DRM_IOCTL_RADEON_VERTEX2 \ 530 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 531#define DRM_IOCTL_RADEON_CMDBUF \ 532 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 533#define DRM_IOCTL_RADEON_GETPARAM \ 534 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 535#define DRM_IOCTL_RADEON_FLIP \ 536 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP) 537#define DRM_IOCTL_RADEON_ALLOC \ 538 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 539#define DRM_IOCTL_RADEON_FREE \ 540 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 541#define DRM_IOCTL_RADEON_INIT_HEAP \ 542 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, \ 543 drm_radeon_mem_init_heap_t) 544#define DRM_IOCTL_RADEON_IRQ_EMIT \ 545 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 546#define DRM_IOCTL_RADEON_IRQ_WAIT \ 547 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 548#define DRM_IOCTL_RADEON_CP_RESUME \ 549 DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 550#define DRM_IOCTL_RADEON_SETPARAM \ 551 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 552#define DRM_IOCTL_RADEON_SURF_ALLOC \ 553 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, \ 554 drm_radeon_surface_alloc_t) 555#define DRM_IOCTL_RADEON_SURF_FREE \ 556 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, \ 557 drm_radeon_surface_free_t) 558 559typedef struct drm_radeon_init { 560 enum { 561 RADEON_INIT_CP = 0x01, 562 RADEON_CLEANUP_CP = 0x02, 563 RADEON_INIT_R200_CP = 0x03, 564 RADEON_INIT_R300_CP = 0x04 565 } func; 566 unsigned long sarea_priv_offset; 567 int is_pci; /* for overriding only */ 568 int cp_mode; 569 int gart_size; 570 int ring_size; 571 int usec_timeout; 572 573 unsigned int fb_bpp; 574 unsigned int front_offset, front_pitch; 575 unsigned int back_offset, back_pitch; 576 unsigned int depth_bpp; 577 unsigned int depth_offset, depth_pitch; 578 579 unsigned long fb_offset DEPRECATED; /* deprecated */ 580 unsigned long mmio_offset DEPRECATED; /* deprecated */ 581 unsigned long ring_offset; 582 unsigned long ring_rptr_offset; 583 unsigned long buffers_offset; 584 unsigned long gart_textures_offset; 585} drm_radeon_init_t; 586 587typedef struct drm_radeon_cp_stop { 588 int flush; 589 int idle; 590} drm_radeon_cp_stop_t; 591 592typedef struct drm_radeon_fullscreen { 593 enum { 594 RADEON_INIT_FULLSCREEN = 0x01, 595 RADEON_CLEANUP_FULLSCREEN = 0x02 596 } func; 597} drm_radeon_fullscreen_t; 598 599#define CLEAR_X1 0 600#define CLEAR_Y1 1 601#define CLEAR_X2 2 602#define CLEAR_Y2 3 603#define CLEAR_DEPTH 4 604 605typedef union drm_radeon_clear_rect { 606 float f[5]; 607 unsigned int ui[5]; 608} drm_radeon_clear_rect_t; 609 610typedef struct drm_radeon_clear { 611 unsigned int flags; 612 unsigned int clear_color; 613 unsigned int clear_depth; 614 unsigned int color_mask; 615 unsigned int depth_mask; /* misnamed field: should be stencil */ 616 drm_radeon_clear_rect_t __user *depth_boxes; 617} drm_radeon_clear_t; 618 619typedef struct drm_radeon_vertex { 620 int prim; 621 int idx; /* Index of vertex buffer */ 622 int count; /* Number of vertices in buffer */ 623 int discard; /* Client finished with buffer? */ 624} drm_radeon_vertex_t; 625 626typedef struct drm_radeon_indices { 627 int prim; 628 int idx; 629 int start; 630 int end; 631 int discard; /* Client finished with buffer? */ 632} drm_radeon_indices_t; 633 634/* 635 * v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 636 * - allows multiple primitives and state changes in a single ioctl 637 * - supports driver change to emit native primitives 638 */ 639typedef struct drm_radeon_vertex2 { 640 int idx; /* Index of vertex buffer */ 641 int discard; /* Client finished with buffer? */ 642 int nr_states; 643 drm_radeon_state_t __user *state; 644 int nr_prims; 645 drm_radeon_prim_t __user *prim; 646} drm_radeon_vertex2_t; 647 648/* 649 * v1.3 - obsoletes drm_radeon_vertex2 650 * - allows arbitarily large cliprect list 651 * - allows updating of tcl packet, vector and scalar state 652 * - allows memory-efficient description of state updates 653 * - allows state to be emitted without a primitive 654 * (for clears, ctx switches) 655 * - allows more than one dma buffer to be referenced per ioctl 656 * - supports tcl driver 657 * - may be extended in future versions with new cmd types, packets 658 */ 659typedef struct drm_radeon_cmd_buffer { 660 int bufsz; 661 char __user *buf; 662 int nbox; 663 drm_clip_rect_t __user *boxes; 664} drm_radeon_cmd_buffer_t; 665 666typedef struct drm_radeon_tex_image { 667 unsigned int x, y; /* Blit coordinates */ 668 unsigned int width, height; 669 const void __user *data; 670} drm_radeon_tex_image_t; 671 672typedef struct drm_radeon_texture { 673 unsigned int offset; 674 int pitch; 675 int format; 676 int width; /* Texture image coordinates */ 677 int height; 678 drm_radeon_tex_image_t __user *image; 679} drm_radeon_texture_t; 680 681typedef struct drm_radeon_stipple { 682 unsigned int __user *mask; 683} drm_radeon_stipple_t; 684 685typedef struct drm_radeon_indirect { 686 int idx; 687 int start; 688 int end; 689 int discard; 690} drm_radeon_indirect_t; 691 692/* enum for card type parameters */ 693#define RADEON_CARD_PCI 0 694#define RADEON_CARD_AGP 1 695#define RADEON_CARD_PCIE 2 696 697/* 698 * 1.3: An ioctl to get parameters that aren't available to the 3d 699 * client any other way. 700 */ 701 702/* card offset of 1st GART buffer */ 703#define RADEON_PARAM_GART_BUFFER_OFFSET 1 704 705#define RADEON_PARAM_LAST_FRAME 2 706#define RADEON_PARAM_LAST_DISPATCH 3 707#define RADEON_PARAM_LAST_CLEAR 4 708/* Added with DRM version 1.6. */ 709#define RADEON_PARAM_IRQ_NR 5 710#define RADEON_PARAM_GART_BASE 6 /* offset of GART base */ 711/* Added with DRM version 1.8. */ 712#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 713#define RADEON_PARAM_STATUS_HANDLE 8 714#define RADEON_PARAM_SAREA_HANDLE 9 715#define RADEON_PARAM_GART_TEX_HANDLE 10 716#define RADEON_PARAM_SCRATCH_OFFSET 11 717#define RADEON_PARAM_CARD_TYPE 12 718#define RADEON_PARAM_VBLANK_CRTC 13 719#define RADEON_PARAM_FB_LOCATION 14 720 721typedef struct drm_radeon_getparam { 722 int param; 723 void __user *value; 724} drm_radeon_getparam_t; 725 726/* 1.6: Set up a memory manager for regions of shared memory: */ 727#define RADEON_MEM_REGION_GART 1 728#define RADEON_MEM_REGION_FB 2 729 730typedef struct drm_radeon_mem_alloc { 731 int region; 732 int alignment; 733 int size; 734 int __user *region_offset; /* offset from start of fb or GART */ 735} drm_radeon_mem_alloc_t; 736 737typedef struct drm_radeon_mem_free { 738 int region; 739 int region_offset; 740} drm_radeon_mem_free_t; 741 742typedef struct drm_radeon_mem_init_heap { 743 int region; 744 int size; 745 int start; 746} drm_radeon_mem_init_heap_t; 747 748/* 1.6: Userspace can request & wait on irq's: */ 749typedef struct drm_radeon_irq_emit { 750 int __user *irq_seq; 751} drm_radeon_irq_emit_t; 752 753typedef struct drm_radeon_irq_wait { 754 int irq_seq; 755} drm_radeon_irq_wait_t; 756 757/* 758 * 1.10: Clients tell the DRM where they think the framebuffer is located in 759 * the card's address space, via a new generic ioctl to set parameters 760 */ 761 762typedef struct drm_radeon_setparam { 763 unsigned int param; 764 int64_t value; 765} drm_radeon_setparam_t; 766 767/* determined framebuffer location */ 768#define RADEON_SETPARAM_FB_LOCATION 1 769 770/* enable/disable color tiling */ 771#define RADEON_SETPARAM_SWITCH_TILING 2 772 773/* PCI Gart Location */ 774#define RADEON_SETPARAM_PCIGART_LOCATION 3 775 776/* Use new memory map */ 777#define RADEON_SETPARAM_NEW_MEMMAP 4 778 779/* PCI GART Table Size */ 780#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 781 782/* VBLANK CRTC */ 783#define RADEON_SETPARAM_VBLANK_CRTC 6 784 785 786/* 1.14: Clients can allocate/free a surface */ 787typedef struct drm_radeon_surface_alloc { 788 unsigned int address; 789 unsigned int size; 790 unsigned int flags; 791} drm_radeon_surface_alloc_t; 792 793typedef struct drm_radeon_surface_free { 794 unsigned int address; 795} drm_radeon_surface_free_t; 796 797#define DRM_RADEON_VBLANK_CRTC1 1 798#define DRM_RADEON_VBLANK_CRTC2 2 799 800#endif /* __RADEON_DRM_H__ */ 801