1/* BEGIN CSTYLED */ 2 3/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 4 */ 5/* 6 * 7 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 8 * Copyright (c) 2009, Intel Corporation. 9 * All Rights Reserved. 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the 13 * "Software"), to deal in the Software without restriction, including 14 * without limitation the rights to use, copy, modify, merge, publish, 15 * distribute, sub license, and/or sell copies of the Software, and to 16 * permit persons to whom the Software is furnished to do so, subject to 17 * the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the 20 * next paragraph) shall be included in all copies or substantial portions 21 * of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 24 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 26 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 27 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 30 * 31 */ 32 33/* 34 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 35 * Use is subject to license terms. 36 */ 37 38#ifndef _I915_DRV_H 39#define _I915_DRV_H 40 41/* General customization: 42 */ 43 44#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 45 46#define DRIVER_NAME "i915" 47#define DRIVER_DESC "Intel Graphics" 48#define DRIVER_DATE "20080730" 49 50#if defined(__SVR4) && defined(__sun) 51#define spinlock_t kmutex_t 52#endif 53 54#define I915_NUM_PIPE 2 55 56#define I915_NUM_PIPE 2 57 58/* Interface history: 59 * 60 * 1.1: Original. 61 * 1.2: Add Power Management 62 * 1.3: Add vblank support 63 * 1.4: Fix cmdbuffer path, add heap destroy 64 * 1.5: Add vblank pipe configuration 65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 66 * - Support vertical blank on secondary display pipe 67 */ 68#define DRIVER_MAJOR 1 69#define DRIVER_MINOR 6 70#define DRIVER_PATCHLEVEL 0 71 72#if defined(__linux__) 73#define I915_HAVE_FENCE 74#define I915_HAVE_BUFFER 75#endif 76#define I915_HAVE_GEM 1 77 78typedef struct _drm_i915_ring_buffer { 79 int tail_mask; 80 unsigned long Size; 81 u8 *virtual_start; 82 int head; 83 int tail; 84 int space; 85 drm_local_map_t map; 86 struct drm_gem_object *ring_obj; 87} drm_i915_ring_buffer_t; 88 89struct mem_block { 90 struct mem_block *next; 91 struct mem_block *prev; 92 int start; 93 int size; 94 drm_file_t *filp; /* 0: free, -1: heap, other: real files */ 95}; 96 97typedef struct _drm_i915_vbl_swap { 98 struct list_head head; 99 drm_drawable_t drw_id; 100 unsigned int plane; 101 unsigned int sequence; 102 int flip; 103} drm_i915_vbl_swap_t; 104 105typedef struct s3_i915_private { 106 ddi_acc_handle_t saveHandle; 107 caddr_t saveAddr; 108 uint32_t pgtbl_ctl; 109 uint8_t saveLBB; 110 uint32_t saveDSPACNTR; 111 uint32_t saveDSPBCNTR; 112 uint32_t saveDSPARB; 113 uint32_t saveRENDERSTANDBY; 114 uint32_t saveHWS; 115 uint32_t savePIPEACONF; 116 uint32_t savePIPEBCONF; 117 uint32_t savePIPEASRC; 118 uint32_t savePIPEBSRC; 119 uint32_t saveFPA0; 120 uint32_t saveFPA1; 121 uint32_t saveDPLL_A; 122 uint32_t saveDPLL_A_MD; 123 uint32_t saveHTOTAL_A; 124 uint32_t saveHBLANK_A; 125 uint32_t saveHSYNC_A; 126 uint32_t saveVTOTAL_A; 127 uint32_t saveVBLANK_A; 128 uint32_t saveVSYNC_A; 129 uint32_t saveBCLRPAT_A; 130 uint32_t saveDSPASTRIDE; 131 uint32_t saveDSPASIZE; 132 uint32_t saveDSPAPOS; 133 uint32_t saveDSPABASE; 134 uint32_t saveDSPASURF; 135 uint32_t saveDSPATILEOFF; 136 uint32_t savePFIT_PGM_RATIOS; 137 uint32_t saveBLC_PWM_CTL; 138 uint32_t saveBLC_PWM_CTL2; 139 uint32_t saveFPB0; 140 uint32_t saveFPB1; 141 uint32_t saveDPLL_B; 142 uint32_t saveDPLL_B_MD; 143 uint32_t saveHTOTAL_B; 144 uint32_t saveHBLANK_B; 145 uint32_t saveHSYNC_B; 146 uint32_t saveVTOTAL_B; 147 uint32_t saveVBLANK_B; 148 uint32_t saveVSYNC_B; 149 uint32_t saveBCLRPAT_B; 150 uint32_t saveDSPBSTRIDE; 151 uint32_t saveDSPBSIZE; 152 uint32_t saveDSPBPOS; 153 uint32_t saveDSPBBASE; 154 uint32_t saveDSPBSURF; 155 uint32_t saveDSPBTILEOFF; 156 uint32_t saveVCLK_DIVISOR_VGA0; 157 uint32_t saveVCLK_DIVISOR_VGA1; 158 uint32_t saveVCLK_POST_DIV; 159 uint32_t saveVGACNTRL; 160 uint32_t saveADPA; 161 uint32_t saveLVDS; 162 uint32_t saveLVDSPP_ON; 163 uint32_t saveLVDSPP_OFF; 164 uint32_t saveDVOA; 165 uint32_t saveDVOB; 166 uint32_t saveDVOC; 167 uint32_t savePP_ON; 168 uint32_t savePP_OFF; 169 uint32_t savePP_CONTROL; 170 uint32_t savePP_CYCLE; 171 uint32_t savePFIT_CONTROL; 172 uint32_t save_palette_a[256]; 173 uint32_t save_palette_b[256]; 174 uint32_t saveFBC_CFB_BASE; 175 uint32_t saveFBC_LL_BASE; 176 uint32_t saveFBC_CONTROL; 177 uint32_t saveFBC_CONTROL2; 178 uint32_t saveIER; 179 uint32_t saveIIR; 180 uint32_t saveIMR; 181 uint32_t saveD_STATE; 182 uint32_t saveCG_2D_DIS; 183 uint32_t saveMI_ARB_STATE; 184 uint32_t savePIPEASTAT; 185 uint32_t savePIPEBSTAT; 186 uint32_t saveCACHE_MODE_0; 187 uint32_t saveSWF0[16]; 188 uint32_t saveSWF1[16]; 189 uint32_t saveSWF2[3]; 190 uint8_t saveMSR; 191 uint8_t saveSR[8]; 192 uint8_t saveGR[25]; 193 uint8_t saveAR_INDEX; 194 uint8_t saveAR[21]; 195 uint8_t saveDACMASK; 196 uint8_t saveDACDATA[256*3]; /* 256 3-byte colors */ 197 uint8_t saveCR[37]; 198} s3_i915_private_t; 199 200struct drm_i915_error_state { 201 u32 eir; 202 u32 pgtbl_er; 203 u32 pipeastat; 204 u32 pipebstat; 205 u32 ipeir; 206 u32 ipehr; 207 u32 instdone; 208 u32 acthd; 209 u32 instpm; 210 u32 instps; 211 u32 instdone1; 212 u32 seqno; 213 struct timeval time; 214}; 215 216typedef struct drm_i915_private { 217 struct drm_device *dev; 218 219 drm_local_map_t *sarea; 220 drm_local_map_t *mmio_map; 221 222 drm_i915_sarea_t *sarea_priv; 223 drm_i915_ring_buffer_t ring; 224 225 drm_dma_handle_t *status_page_dmah; 226 void *hw_status_page; 227 dma_addr_t dma_status_page; 228 uint32_t counter; 229 unsigned int status_gfx_addr; 230 drm_local_map_t hws_map; 231 struct drm_gem_object *hws_obj; 232 233 unsigned int cpp; 234 int back_offset; 235 int front_offset; 236 int current_page; 237 int page_flipping; 238 239 wait_queue_head_t irq_queue; 240 atomic_t irq_received; 241 /** Protects user_irq_refcount and irq_mask_reg */ 242 spinlock_t user_irq_lock; 243 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 244 int user_irq_refcount; 245 /** Cached value of IMR to avoid reads in updating the bitfield */ 246 int irq_mask_reg; 247 uint32_t pipestat[2]; 248 /** splitted irq regs for graphics and display engine on IGDNG, 249 irq_mask_reg is still used for display irq. */ 250 u32 gt_irq_mask_reg; 251 u32 gt_irq_enable_reg; 252 u32 de_irq_enable_reg; 253 254 int tex_lru_log_granularity; 255 int allow_batchbuffer; 256 struct mem_block *agp_heap; 257 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 258 int vblank_pipe; 259 260 spinlock_t error_lock; 261 struct drm_i915_error_state *first_error; 262 263 struct { 264 struct drm_mm gtt_space; 265 266 drm_local_map_t gtt_mapping; 267 /** 268 * List of objects currently involved in rendering from the 269 * ringbuffer. 270 * 271 * A reference is held on the buffer while on this list. 272 */ 273 struct list_head active_list; 274 275 /** 276 * List of objects which are not in the ringbuffer but which 277 * still have a write_domain which needs to be flushed before 278 * unbinding. 279 * 280 * A reference is held on the buffer while on this list. 281 */ 282 struct list_head flushing_list; 283 284 /** 285 * LRU list of objects which are not in the ringbuffer and 286 * are ready to unbind, but are still in the GTT. 287 * 288 * A reference is not held on the buffer while on this list, 289 * as merely being GTT-bound shouldn't prevent its being 290 * freed, and we'll pull it off the list in the free path. 291 */ 292 struct list_head inactive_list; 293 294 /** 295 * List of breadcrumbs associated with GPU requests currently 296 * outstanding. 297 */ 298 struct list_head request_list; 299 300 uint32_t next_gem_seqno; 301 302 /** 303 * Waiting sequence number, if any 304 */ 305 uint32_t waiting_gem_seqno; 306 307 /** 308 * Last seq seen at irq time 309 */ 310 uint32_t irq_gem_seqno; 311 312 /** 313 * Flag if the X Server, and thus DRM, is not currently in 314 * control of the device. 315 * 316 * This is set between LeaveVT and EnterVT. It needs to be 317 * replaced with a semaphore. It also needs to be 318 * transitioned away from for kernel modesetting. 319 */ 320 int suspended; 321 322 /** 323 * Flag if the hardware appears to be wedged. 324 * 325 * This is set when attempts to idle the device timeout. 326 * It prevents command submission from occuring and makes 327 * every pending request fail 328 */ 329 int wedged; 330 331 /** Bit 6 swizzling required for X tiling */ 332 uint32_t bit_6_swizzle_x; 333 /** Bit 6 swizzling required for Y tiling */ 334 uint32_t bit_6_swizzle_y; 335 } mm; 336 337} drm_i915_private_t; 338 339struct drm_track { 340 struct drm_track *next, *prev; 341 caddr_t contain_ptr; 342 struct drm_gem_object *obj; 343 uint32_t name; 344 uint64_t offset; 345 346}; 347 348/** driver private structure attached to each drm_gem_object */ 349struct drm_i915_gem_object { 350 /** This object's place on the active/flushing/inactive lists */ 351 struct list_head list; 352 353 struct drm_gem_object *obj; 354 355 /** Current space allocated to this object in the GTT, if any. */ 356 struct drm_mm_node *gtt_space; 357 358 359 /** 360 * This is set if the object is on the active or flushing lists 361 * (has pending rendering), and is not set if it's on inactive (ready 362 * to be unbound). 363 */ 364 int active; 365 366 /** 367 * This is set if the object has been written to since last bound 368 * to the GTT 369 */ 370 int dirty; 371 372 /** AGP memory structure for our GTT binding. */ 373 int agp_mem; 374 375 caddr_t *page_list; 376 377 pfn_t *pfnarray; 378 /** 379 * Current offset of the object in GTT space. 380 * 381 * This is the same as gtt_space->start 382 */ 383 uint32_t gtt_offset; 384 385 /** Boolean whether this object has a valid gtt offset. */ 386 int gtt_bound; 387 388 /** How many users have pinned this object in GTT space */ 389 int pin_count; 390 391 /** Breadcrumb of last rendering to the buffer. */ 392 uint32_t last_rendering_seqno; 393 394 /** Current tiling mode for the object. */ 395 uint32_t tiling_mode; 396 uint32_t stride; 397 /** 398 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 399 * GEM_DOMAIN_CPU is not in the object's read domain. 400 */ 401 uint8_t *page_cpu_valid; 402 /** User space pin count and filp owning the pin */ 403 uint32_t user_pin_count; 404 struct drm_file *pin_filp; 405 /** 406 * Used for checking the object doesn't appear more than once 407 * in an execbuffer object list. 408 */ 409 int in_execbuffer; 410}; 411 412/** 413 * Request queue structure. 414 * 415 * The request queue allows us to note sequence numbers that have been emitted 416 * and may be associated with active buffers to be retired. 417 * 418 * By keeping this list, we can avoid having to do questionable 419 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 420 * an emission time with seqnos for tracking how far ahead of the GPU we are. 421 */ 422struct drm_i915_gem_request { 423 struct list_head list; 424 425 /** GEM sequence number associated with this request. */ 426 uint32_t seqno; 427 428 /** Time at which this request was emitted, in jiffies. */ 429 unsigned long emitted_jiffies; 430 431 /** Cache domains that were flushed at the start of the request. */ 432 uint32_t flush_domains; 433 434}; 435 436struct drm_i915_file_private { 437 struct { 438 uint32_t last_gem_seqno; 439 uint32_t last_gem_throttle_seqno; 440 } mm; 441}; 442 443 444enum intel_chip_family { 445 CHIP_I8XX = 0x01, 446 CHIP_I9XX = 0x02, 447 CHIP_I915 = 0x04, 448 CHIP_I965 = 0x08, 449}; 450 451extern drm_ioctl_desc_t i915_ioctls[]; 452extern int i915_max_ioctl; 453extern void i915_save_display(struct drm_device *dev); 454extern void i915_restore_display(struct drm_device *dev); 455 456 /* i915_dma.c */ 457extern void i915_kernel_lost_context(drm_device_t * dev); 458extern int i915_driver_load(struct drm_device *, unsigned long flags); 459extern int i915_driver_unload(struct drm_device *dev); 460extern int i915_driver_open(drm_device_t * dev, drm_file_t *file_priv); 461extern void i915_driver_lastclose(drm_device_t * dev); 462extern void i915_driver_preclose(drm_device_t * dev, drm_file_t *filp); 463extern void i915_driver_postclose(drm_device_t * dev, 464 struct drm_file *file_priv); 465extern int i915_driver_device_is_agp(drm_device_t * dev); 466extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 467 unsigned long arg); 468extern int i915_emit_box(struct drm_device *dev, 469 struct drm_clip_rect __user *boxes, 470 int i, int DR1, int DR4); 471extern void i915_emit_breadcrumb(struct drm_device *dev); 472extern void i915_emit_mi_flush(drm_device_t *dev, uint32_t flush); 473extern void i915_handle_error(struct drm_device *dev); 474 475/* i915_irq.c */ 476extern int i915_irq_emit(DRM_IOCTL_ARGS); 477extern int i915_irq_wait(DRM_IOCTL_ARGS); 478 479extern int i915_enable_vblank(struct drm_device *dev, int crtc); 480extern void i915_disable_vblank(struct drm_device *dev, int crtc); 481extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 482extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 483extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 484extern int i915_driver_irq_preinstall(drm_device_t * dev); 485extern void i915_driver_irq_postinstall(drm_device_t * dev); 486extern void i915_driver_irq_uninstall(drm_device_t * dev); 487extern int i915_emit_irq(drm_device_t * dev); 488extern int i915_vblank_swap(DRM_IOCTL_ARGS); 489extern void i915_user_irq_on(drm_device_t * dev); 490extern void i915_user_irq_off(drm_device_t * dev); 491extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS); 492extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS); 493 494/* i915_mem.c */ 495extern int i915_mem_alloc(DRM_IOCTL_ARGS); 496extern int i915_mem_free(DRM_IOCTL_ARGS); 497extern int i915_mem_init_heap(DRM_IOCTL_ARGS); 498extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); 499extern void i915_mem_takedown(struct mem_block **heap); 500extern void i915_mem_release(drm_device_t * dev, 501 drm_file_t *filp, struct mem_block *heap); 502extern struct mem_block **get_heap(drm_i915_private_t *, int); 503extern struct mem_block *find_block_by_proc(struct mem_block *, drm_file_t *); 504extern void mark_block(drm_device_t *, struct mem_block *, int); 505extern void free_block(struct mem_block *); 506 507/* i915_gem.c */ 508int i915_gem_init_ioctl(DRM_IOCTL_ARGS); 509int i915_gem_create_ioctl(DRM_IOCTL_ARGS); 510int i915_gem_pread_ioctl(DRM_IOCTL_ARGS); 511int i915_gem_pwrite_ioctl(DRM_IOCTL_ARGS); 512int i915_gem_mmap_ioctl(DRM_IOCTL_ARGS); 513int i915_gem_set_domain_ioctl(DRM_IOCTL_ARGS); 514int i915_gem_sw_finish_ioctl(DRM_IOCTL_ARGS); 515int i915_gem_execbuffer(DRM_IOCTL_ARGS); 516int i915_gem_pin_ioctl(DRM_IOCTL_ARGS); 517int i915_gem_unpin_ioctl(DRM_IOCTL_ARGS); 518int i915_gem_busy_ioctl(DRM_IOCTL_ARGS); 519int i915_gem_throttle_ioctl(DRM_IOCTL_ARGS); 520int i915_gem_entervt_ioctl(DRM_IOCTL_ARGS); 521int i915_gem_leavevt_ioctl(DRM_IOCTL_ARGS); 522int i915_gem_set_tiling(DRM_IOCTL_ARGS); 523int i915_gem_get_tiling(DRM_IOCTL_ARGS); 524int i915_gem_get_aperture_ioctl(DRM_IOCTL_ARGS); 525void i915_gem_load(struct drm_device *dev); 526int i915_gem_init_object(struct drm_gem_object *obj); 527void i915_gem_free_object(struct drm_gem_object *obj); 528int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 529void i915_gem_object_unpin(struct drm_gem_object *obj); 530int i915_gem_object_unbind(struct drm_gem_object *obj, uint32_t type); 531void i915_gem_lastclose(struct drm_device *dev); 532uint32_t i915_get_gem_seqno(struct drm_device *dev); 533void i915_gem_retire_requests(struct drm_device *dev); 534void i915_gem_retire_work_handler(void *dev); 535void i915_gem_clflush_object(struct drm_gem_object *obj); 536int i915_gem_init_ringbuffer(struct drm_device *dev); 537 538/* i915_gem_tiling.c */ 539void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 540 541/* i915_gem_debug.c */ 542void i915_gem_command_decode(uint32_t *data, int count, 543 uint32_t hw_offset, struct drm_device *dev); 544/* i915_gem_regdump.c */ 545int i915_reg_dump_show(struct drm_device *dev, void *v); 546#ifdef I915_HAVE_FENCE 547/* i915_fence.c */ 548 549 550extern void i915_fence_handler(drm_device_t *dev); 551extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, 552 uint32_t flags, 553 uint32_t *sequence, 554 uint32_t *native_type); 555extern void i915_poke_flush(drm_device_t *dev, uint32_t class); 556extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); 557#endif 558 559#ifdef I915_HAVE_BUFFER 560/* i915_buffer.c */ 561extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); 562extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); 563extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); 564extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, 565 drm_mem_type_manager_t *man); 566extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); 567extern int i915_move(drm_buffer_object_t *bo, int evict, 568 int no_wait, drm_bo_mem_reg_t *new_mem); 569 570#endif 571 572#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 573#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 574#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 575#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 576#define S3_READ(reg) \ 577 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) 578#define S3_WRITE(reg, val) \ 579 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) = (val) 580 581#define I915_VERBOSE 0 582#define I915_RING_VALIDATE 0 583 584#if I915_RING_VALIDATE 585void i915_ring_validate(struct drm_device *dev, const char *func, int line); 586#define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__) 587#else 588#define I915_RING_DO_VALIDATE(dev) 589#endif 590 591#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 592 volatile unsigned char *virt; 593 594 595#define I915_RING_VALIDATE 0 596 597#if I915_RING_VALIDATE 598void i915_ring_validate(struct drm_device *dev, const char *func, int line); 599#define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__) 600#else 601#define I915_RING_DO_VALIDATE(dev) 602#endif 603 604#if I915_VERBOSE 605#define BEGIN_LP_RING(n) do { \ 606 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 607 DRM_DEBUG("dev_priv->ring.virtual_start (%lx)\n", (dev_priv->ring.virtual_start)); \ 608 I915_RING_DO_VALIDATE(dev); \ 609 if (dev_priv->ring.space < (n)*4) \ 610 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 611 outcount = 0; \ 612 outring = dev_priv->ring.tail; \ 613 ringmask = dev_priv->ring.tail_mask; \ 614 virt = dev_priv->ring.virtual_start; \ 615} while (*"\0") 616#else 617#define BEGIN_LP_RING(n) do { \ 618 I915_RING_DO_VALIDATE(dev); \ 619 if (dev_priv->ring.space < (n)*4) \ 620 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 621 outcount = 0; \ 622 outring = dev_priv->ring.tail; \ 623 ringmask = dev_priv->ring.tail_mask; \ 624 virt = dev_priv->ring.virtual_start; \ 625} while (*"\0") 626#endif 627 628#if I915_VERBOSE 629#define OUT_RING(n) do { \ 630 DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 631 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 632 outcount++; \ 633 outring += 4; \ 634 outring &= ringmask; \ 635} while (*"\0") 636#else 637#define OUT_RING(n) do { \ 638 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 639 outcount++; \ 640 outring += 4; \ 641 outring &= ringmask; \ 642} while (*"\0") 643#endif 644 645#if I915_VERBOSE 646#define ADVANCE_LP_RING() do { \ 647 DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 648 I915_RING_DO_VALIDATE(dev); \ 649 dev_priv->ring.tail = outring; \ 650 dev_priv->ring.space -= outcount * 4; \ 651 I915_WRITE(PRB0_TAIL, outring); \ 652} while (*"\0") 653#else 654#define ADVANCE_LP_RING() do { \ 655 I915_RING_DO_VALIDATE(dev); \ 656 dev_priv->ring.tail = outring; \ 657 dev_priv->ring.space -= outcount * 4; \ 658 I915_WRITE(PRB0_TAIL, outring); \ 659} while (*"\0") 660#endif 661 662extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); 663 664/* Extended config space */ 665#define LBB 0xf4 666#define GDRST 0xc0 667#define GDRST_FULL (0<<2) 668#define GDRST_RENDER (1<<2) 669#define GDRST_MEDIA (3<<2) 670 671/* VGA stuff */ 672 673#define VGA_ST01_MDA 0x3ba 674#define VGA_ST01_CGA 0x3da 675 676#define VGA_MSR_WRITE 0x3c2 677#define VGA_MSR_READ 0x3cc 678#define VGA_MSR_MEM_EN (1<<1) 679#define VGA_MSR_CGA_MODE (1<<0) 680 681#define VGA_SR_INDEX 0x3c4 682#define VGA_SR_DATA 0x3c5 683 684#define VGA_AR_INDEX 0x3c0 685#define VGA_AR_VID_EN (1<<5) 686#define VGA_AR_DATA_WRITE 0x3c0 687#define VGA_AR_DATA_READ 0x3c1 688 689#define VGA_GR_INDEX 0x3ce 690#define VGA_GR_DATA 0x3cf 691/* GR05 */ 692#define VGA_GR_MEM_READ_MODE_SHIFT 3 693#define VGA_GR_MEM_READ_MODE_PLANE 1 694/* GR06 */ 695#define VGA_GR_MEM_MODE_MASK 0xc 696#define VGA_GR_MEM_MODE_SHIFT 2 697#define VGA_GR_MEM_A0000_AFFFF 0 698#define VGA_GR_MEM_A0000_BFFFF 1 699#define VGA_GR_MEM_B0000_B7FFF 2 700#define VGA_GR_MEM_B0000_BFFFF 3 701 702#define VGA_DACMASK 0x3c6 703#define VGA_DACRX 0x3c7 704#define VGA_DACWX 0x3c8 705#define VGA_DACDATA 0x3c9 706 707#define VGA_CR_INDEX_MDA 0x3b4 708#define VGA_CR_DATA_MDA 0x3b5 709#define VGA_CR_INDEX_CGA 0x3d4 710#define VGA_CR_DATA_CGA 0x3d5 711 712 713#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 714#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 715#define CMD_REPORT_HEAD (7<<23) 716#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 717#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 718 719#define INST_PARSER_CLIENT 0x00000000 720#define INST_OP_FLUSH 0x02000000 721#define INST_FLUSH_MAP_CACHE 0x00000001 722 723#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 724#define MI_USER_INTERRUPT MI_INSTR(2, (0 << 29)) 725#define MI_FLUSH (0x04 << 23) 726#define MI_NO_WRITE_FLUSH (1 << 2) 727#define MI_READ_FLUSH (1 << 0) 728#define MI_EXE_FLUSH (1 << 1) 729#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 730#define MI_STORE_DWORD_INDEX_SHIFT 2 731 732#define BB1_START_ADDR_MASK (~0x7) 733#define BB1_PROTECTED (1<<0) 734#define BB1_UNPROTECTED (0<<0) 735#define BB2_END_ADDR_MASK (~0x7) 736 737#define I915REG_PGTBL_CTRL 0x2020 738#define IPEIR 0x02088 739#define HWSTAM 0x02098 740#define IIR 0x020a4 741#define IMR 0x020a8 742#define IER 0x020a0 743#define INSTPM 0x020c0 744#define ACTHD 0x020c8 745#define PIPEASTAT 0x70024 746#define PIPEBSTAT 0x71024 747#define ACTHD_I965 0x02074 748#define HWS_PGA 0x02080 749#define IPEIR_I965 0x02064 750#define IPEHR_I965 0x02068 751#define INSTDONE_I965 0x0206c 752#define INSTPS 0x02070 /* 965+ only */ 753#define INSTDONE1 0x0207c /* 965+ only */ 754#define IPEHR 0x0208c 755#define INSTDONE 0x02090 756#define EIR 0x020b0 757#define EMR 0x020b4 758#define ESR 0x020b8 759#define GM45_ERROR_PAGE_TABLE (1<<5) 760#define GM45_ERROR_MEM_PRIV (1<<4) 761#define I915_ERROR_PAGE_TABLE (1<<4) 762#define GM45_ERROR_CP_PRIV (1<<3) 763#define I915_ERROR_MEMORY_REFRESH (1<<1) 764#define I915_ERROR_INSTRUCTION (1<<0) 765 766#define PIPEA_FRMCOUNT_GM45 0x70040 767#define PIPEA_FLIPCOUNT_GM45 0x70044 768#define PIPEB_FRMCOUNT_GM45 0x71040 769#define PIPEB_FLIPCOUNT_GM45 0x71044 770 771#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 772#define I915_VBLANK_CLEAR (1UL<<1) 773 774#define SRX_INDEX 0x3c4 775#define SRX_DATA 0x3c5 776#define SR01 1 777#define SR01_SCREEN_OFF (1<<5) 778 779#define PPCR 0x61204 780#define PPCR_ON (1<<0) 781 782#define DVOB 0x61140 783#define DVOB_ON (1<<31) 784#define DVOC 0x61160 785#define DVOC_ON (1<<31) 786#define LVDS 0x61180 787#define LVDS_ON (1<<31) 788 789#define ADPA 0x61100 790#define ADPA_DPMS_MASK (~(3<<10)) 791#define ADPA_DPMS_ON (0<<10) 792#define ADPA_DPMS_SUSPEND (1<<10) 793#define ADPA_DPMS_STANDBY (2<<10) 794#define ADPA_DPMS_OFF (3<<10) 795 796#ifdef NOPID 797#undef NOPID 798#endif 799#define NOPID 0x2094 800#define LP_RING 0x2030 801#define HP_RING 0x2040 802#define TAIL_ADDR 0x001FFFF8 803#define HEAD_WRAP_COUNT 0xFFE00000 804#define HEAD_WRAP_ONE 0x00200000 805#define HEAD_ADDR 0x001FFFFC 806#define RING_START 0x08 807#define START_ADDR 0x0xFFFFF000 808#define RING_LEN 0x0C 809#define RING_NR_PAGES 0x001FF000 810#define RING_REPORT_MASK 0x00000006 811#define RING_REPORT_64K 0x00000002 812#define RING_REPORT_128K 0x00000004 813#define RING_NO_REPORT 0x00000000 814#define RING_VALID_MASK 0x00000001 815#define RING_VALID 0x00000001 816#define RING_INVALID 0x00000000 817#define PGTBL_ER 0x02024 818#define PRB0_TAIL 0x02030 819#define PRB0_HEAD 0x02034 820#define PRB0_START 0x02038 821#define PRB0_CTL 0x0203c 822#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 823#define SC_UPDATE_SCISSOR (0x1<<1) 824#define SC_ENABLE_MASK (0x1<<0) 825#define SC_ENABLE (0x1<<0) 826 827#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 828#define SCI_YMIN_MASK (0xffff<<16) 829#define SCI_XMIN_MASK (0xffff<<0) 830#define SCI_YMAX_MASK (0xffff<<16) 831#define SCI_XMAX_MASK (0xffff<<0) 832 833#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 834#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 835#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 836#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 837#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 838#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 839#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 840 841#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 842 843#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 844#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 845#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 846#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 847#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) 848#define XY_SRC_COPY_BLT_DST_TILED (1<<11) 849 850#define MI_BATCH_BUFFER ((0x30<<23)|1) 851#define MI_BATCH_BUFFER_START (0x31<<23) 852#define MI_BATCH_BUFFER_END (0xA<<23) 853#define MI_BATCH_NON_SECURE (1) 854 855#define MI_BATCH_NON_SECURE_I965 (1<<8) 856 857#define MI_WAIT_FOR_EVENT ((0x3<<23)) 858#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 859#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 860#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 861 862#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 863 864#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 865#define ASYNC_FLIP (1<<22) 866#define DISPLAY_PLANE_A (0<<20) 867#define DISPLAY_PLANE_B (1<<20) 868 869#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 870 871/** 872 * Reads a dword out of the status page, which is written to from the command 873 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 874 * MI_STORE_DATA_IMM. 875 * 876 * The following dwords have a reserved meaning: 877 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 878 * 0x04: ring 0 head pointer 879 * 0x05: ring 1 head pointer (915-class) 880 * 0x06: ring 2 head pointer (915-class) 881 * 0x10-0x1b: Context status DWords (GM45) 882 * 0x1f: Last written status offset. (GM45) 883 * 884 * The area from dword 0x20 to 0x3ff is available for driver usage. 885 */ 886#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 887#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 888#define I915_GEM_HWS_INDEX 0x20 889#define I915_BREADCRUMB_INDEX 0x21 890 891/* 892 * add here for S3 support 893 */ 894#define DPLL_A 0x06014 895#define DPLL_B 0x06018 896# define DPLL_VCO_ENABLE 0x80000000 /* (1 << 31) */ 897# define DPLL_DVO_HIGH_SPEED (1 << 30) 898# define DPLL_SYNCLOCK_ENABLE (1 << 29) 899# define DPLL_VGA_MODE_DIS (1 << 28) 900# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 901# define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 902# define DPLL_MODE_MASK (3 << 26) 903# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 904# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 905# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 906# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 907# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 908# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 909 910/** 911 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 912 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 913 */ 914# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 915/** 916 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 917 * this field (only one bit may be set). 918 */ 919# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 920# define DPLL_FPA01_P1_POST_DIV_SHIFT 16 921# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ 922# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 923# define PLL_REF_INPUT_DREFCLK (0 << 13) 924# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 925# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 926# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 927# define PLL_REF_INPUT_MASK (3 << 13) 928# define PLL_LOAD_PULSE_PHASE_SHIFT 9 929 930/* IGDNG */ 931#define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 932#define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 933#define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 934#define DPLL_FPA1_P1_POST_DIV_SHIFT 0 935#define DPLL_FPA1_P1_POST_DIV_MASK 0xff 936 937/* 938 * Parallel to Serial Load Pulse phase selection. 939 * Selects the phase for the 10X DPLL clock for the PCIe 940 * digital display port. The range is 4 to 13; 10 or more 941 * is just a flip delay. The default is 6 942 */ 943# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 944# define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 945 946/** 947 * SDVO multiplier for 945G/GM. Not used on 965. 948 * 949 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 950 */ 951# define SDVO_MULTIPLIER_MASK 0x000000ff 952# define SDVO_MULTIPLIER_SHIFT_HIRES 4 953# define SDVO_MULTIPLIER_SHIFT_VGA 0 954 955/** @defgroup DPLL_MD 956 * @{ 957 */ 958/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 959#define DPLL_A_MD 0x0601c 960/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 961#define DPLL_B_MD 0x06020 962/** 963 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 964 * 965 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 966 */ 967# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 968# define DPLL_MD_UDI_DIVIDER_SHIFT 24 969/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 970# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 971# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 972/** 973 * SDVO/UDI pixel multiplier. 974 * 975 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 976 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 977 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 978 * dummy bytes in the datastream at an increased clock rate, with both sides of 979 * the link knowing how many bytes are fill. 980 * 981 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 982 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 983 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 984 * through an SDVO command. 985 * 986 * This register field has values of multiplication factor minus 1, with 987 * a maximum multiplier of 5 for SDVO. 988 */ 989# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 990# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 991/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 992 * This best be set to the default value (3) or the CRT won't work. No, 993 * I don't entirely understand what this does... 994 */ 995# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 996# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 997/** @} */ 998 999#define DPLL_TEST 0x606c 1000# define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1001# define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1002# define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1003# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1004# define DPLLB_TEST_N_BYPASS (1 << 19) 1005# define DPLLB_TEST_M_BYPASS (1 << 18) 1006# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1007# define DPLLA_TEST_N_BYPASS (1 << 3) 1008# define DPLLA_TEST_M_BYPASS (1 << 2) 1009# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1010 1011/* 1012 * Palette registers 1013 */ 1014#define PALETTE_A 0x0a000 1015#define PALETTE_B 0x0a800 1016 1017/* MCH MMIO space */ 1018 1019/* 1020 * MCHBAR mirror. 1021 * 1022 * This mirrors the MCHBAR MMIO space whose location is determined by 1023 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1024 * every way. It is not accessible from the CP register read instructions. 1025 * 1026 */ 1027#define MCHBAR_MIRROR_BASE 0x10000 1028 1029/** 915-945 and GM965 MCH register controlling DRAM channel access */ 1030#define DCC 0x10200 1031#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1032#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1033#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1034#define DCC_ADDRESSING_MODE_MASK (3 << 0) 1035#define DCC_CHANNEL_XOR_DISABLE (1 << 10) 1036#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 1037 1038/** 965 MCH register controlling DRAM channel configuration */ 1039#define C0DRB3 0x10206 1040#define C1DRB3 0x10606 1041 1042/** GM965 GM45 render standby register */ 1043#define MCHBAR_RENDER_STANDBY 0x111B8 1044 1045#define FPA0 0x06040 1046#define FPA1 0x06044 1047#define FPB0 0x06048 1048#define FPB1 0x0604c 1049 1050#define D_STATE 0x6104 1051#define CG_2D_DIS 0x6200 1052#define CG_3D_DIS 0x6204 1053 1054#define MI_ARB_STATE 0x20e4 1055 1056/* 1057 * Cache mode 0 reg. 1058 * - Manipulating render cache behaviour is central 1059 * to the concept of zone rendering, tuning this reg can help avoid 1060 * unnecessary render cache reads and even writes (for z/stencil) 1061 * at beginning and end of scene. 1062 * 1063 * - To change a bit, write to this reg with a mask bit set and the 1064 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. 1065 */ 1066#define CACHE_MODE_0 0x2120 1067 1068/* I830 CRTC registers */ 1069#define HTOTAL_A 0x60000 1070#define HBLANK_A 0x60004 1071#define HSYNC_A 0x60008 1072#define VTOTAL_A 0x6000c 1073#define VBLANK_A 0x60010 1074#define VSYNC_A 0x60014 1075#define PIPEASRC 0x6001c 1076#define BCLRPAT_A 0x60020 1077#define VSYNCSHIFT_A 0x60028 1078 1079#define HTOTAL_B 0x61000 1080#define HBLANK_B 0x61004 1081#define HSYNC_B 0x61008 1082#define VTOTAL_B 0x6100c 1083#define VBLANK_B 0x61010 1084#define VSYNC_B 0x61014 1085#define PIPEBSRC 0x6101c 1086#define BCLRPAT_B 0x61020 1087#define VSYNCSHIFT_B 0x61028 1088 1089#define DSPACNTR 0x70180 1090#define DSPBCNTR 0x71180 1091#define DISPLAY_PLANE_ENABLE (1<<31) 1092#define DISPLAY_PLANE_DISABLE 0 1093#define DISPPLANE_GAMMA_ENABLE (1<<30) 1094#define DISPPLANE_GAMMA_DISABLE 0 1095#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 1096#define DISPPLANE_8BPP (0x2<<26) 1097#define DISPPLANE_15_16BPP (0x4<<26) 1098#define DISPPLANE_16BPP (0x5<<26) 1099#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 1100#define DISPPLANE_32BPP (0x7<<26) 1101#define DISPPLANE_STEREO_ENABLE (1<<25) 1102#define DISPPLANE_STEREO_DISABLE 0 1103#define DISPPLANE_SEL_PIPE_MASK (1<<24) 1104#define DISPPLANE_SEL_PIPE_A 0 1105#define DISPPLANE_SEL_PIPE_B (1<<24) 1106#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 1107#define DISPPLANE_SRC_KEY_DISABLE 0 1108#define DISPPLANE_LINE_DOUBLE (1<<20) 1109#define DISPPLANE_NO_LINE_DOUBLE 0 1110#define DISPPLANE_STEREO_POLARITY_FIRST 0 1111#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 1112/* plane B only */ 1113#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 1114#define DISPPLANE_ALPHA_TRANS_DISABLE 0 1115#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 1116#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 1117 1118#define DSPABASE 0x70184 1119#define DSPASTRIDE 0x70188 1120 1121#define DSPBBASE 0x71184 1122#define DSPBADDR DSPBBASE 1123#define DSPBSTRIDE 0x71188 1124 1125#define DSPAKEYVAL 0x70194 1126#define DSPAKEYMASK 0x70198 1127 1128#define DSPAPOS 0x7018C /* reserved */ 1129#define DSPASIZE 0x70190 1130#define DSPBPOS 0x7118C 1131#define DSPBSIZE 0x71190 1132 1133#define DSPASURF 0x7019C 1134#define DSPATILEOFF 0x701A4 1135 1136#define DSPBSURF 0x7119C 1137#define DSPBTILEOFF 0x711A4 1138 1139#define PIPEACONF 0x70008 1140#define PIPEACONF_ENABLE (1UL<<31) 1141#define PIPEACONF_DISABLE 0 1142#define PIPEACONF_DOUBLE_WIDE (1<<30) 1143#define I965_PIPECONF_ACTIVE (1<<30) 1144#define PIPEACONF_SINGLE_WIDE 0 1145#define PIPEACONF_PIPE_UNLOCKED 0 1146#define PIPEACONF_PIPE_LOCKED (1<<25) 1147#define PIPEACONF_PALETTE 0 1148#define PIPEACONF_GAMMA (1<<24) 1149#define PIPECONF_FORCE_BORDER (1<<25) 1150#define PIPECONF_PROGRESSIVE (0 << 21) 1151#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 1152#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 1153 1154#define PIPEBCONF 0x71008 1155#define PIPEBCONF_ENABLE (1UL<<31) 1156#define PIPEBCONF_DISABLE 0 1157#define PIPEBCONF_DOUBLE_WIDE (1<<30) 1158#define PIPEBCONF_DISABLE 0 1159#define PIPEBCONF_GAMMA (1<<24) 1160#define PIPEBCONF_PALETTE 0 1161 1162#define BLC_PWM_CTL 0x61254 1163#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 1164 1165#define BLC_PWM_CTL2 0x61250 1166 1167#define PFIT_CONTROL 0x61230 1168#define PFIT_PGM_RATIOS 0x61234 1169 1170/** 1171 * Indicates that all dependencies of the panel are on: 1172 * 1173 * - PLL enabled 1174 * - pipe enabled 1175 * - LVDS/DVOB/DVOC on 1176 */ 1177#define PP_READY (1 << 30) 1178#define PP_SEQUENCE_NONE (0 << 28) 1179#define PP_SEQUENCE_ON (1 << 28) 1180#define PP_SEQUENCE_OFF (2 << 28) 1181#define PP_SEQUENCE_MASK 0x30000000 1182#define PP_CONTROL 0x61204 1183#define POWER_TARGET_ON (1 << 0) 1184 1185#define LVDSPP_ON 0x61208 1186#define LVDSPP_OFF 0x6120c 1187#define PP_CYCLE 0x61210 1188 1189/* Framebuffer compression */ 1190#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 1191#define FBC_LL_BASE 0x03204 /* 4k page aligned */ 1192#define FBC_CONTROL 0x03208 1193 1194#define VGACNTRL 0x71400 1195 1196#define VCLK_DIVISOR_VGA0 0x6000 1197#define VCLK_DIVISOR_VGA1 0x6004 1198#define VCLK_POST_DIV 0x6010 1199 1200/* Framebuffer compression */ 1201#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 1202#define FBC_LL_BASE 0x03204 /* 4k page aligned */ 1203#define FBC_CONTROL 0x03208 1204#define FBC_CTL_EN (1<<31) 1205#define FBC_CTL_PERIODIC (1<<30) 1206#define FBC_CTL_INTERVAL_SHIFT (16) 1207#define FBC_CTL_UNCOMPRESSIBLE (1<<14) 1208#define FBC_CTL_STRIDE_SHIFT (5) 1209#define FBC_CTL_FENCENO (1<<0) 1210#define FBC_COMMAND 0x0320c 1211#define FBC_CMD_COMPRESS (1<<0) 1212#define FBC_STATUS 0x03210 1213#define FBC_STAT_COMPRESSING (1<<31) 1214#define FBC_STAT_COMPRESSED (1<<30) 1215#define FBC_STAT_MODIFIED (1<<29) 1216#define FBC_STAT_CURRENT_LINE (1<<0) 1217#define FBC_CONTROL2 0x03214 1218#define FBC_CTL_FENCE_DBL (0<<4) 1219#define FBC_CTL_IDLE_IMM (0<<2) 1220#define FBC_CTL_IDLE_FULL (1<<2) 1221#define FBC_CTL_IDLE_LINE (2<<2) 1222#define FBC_CTL_IDLE_DEBUG (3<<2) 1223#define FBC_CTL_CPU_FENCE (1<<1) 1224#define FBC_CTL_PLANEA (0<<0) 1225#define FBC_CTL_PLANEB (1<<0) 1226#define FBC_FENCE_OFF 0x0321b 1227 1228#define FBC_LL_SIZE (1536) 1229#define FBC_LL_PAD (32) 1230 1231#define DSPARB 0x70030 1232 1233#define PIPEAFRAMEHIGH 0x70040 1234#define PIPEBFRAMEHIGH 0x71040 1235#define PIPE_FRAME_HIGH_MASK 0x0000ffff 1236#define PIPE_FRAME_HIGH_SHIFT 0 1237#define PIPEAFRAMEPIXEL 0x70044 1238#define PIPEBFRAMEPIXEL 0x71044 1239 1240#define PIPE_FRAME_LOW_MASK 0xff000000 1241#define PIPE_FRAME_LOW_SHIFT 24 1242 1243/* Interrupt bits: 1244 */ 1245#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 1246#define I915_DISPLAY_PORT_INTERRUPT (1<<17) 1247#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 1248#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 1249#define I915_HWB_OOM_INTERRUPT (1<<13) /* binner out of memory */ 1250#define I915_SYNC_STATUS_INTERRUPT (1<<12) 1251#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 1252#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 1253#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 1254#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 1255#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 1256#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 1257#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 1258#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 1259#define I915_DEBUG_INTERRUPT (1<<2) 1260#define I915_USER_INTERRUPT (1<<1) 1261#define I915_ASLE_INTERRUPT (1<<0) 1262 1263#define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 1264#define I915_CRC_ERROR_ENABLE (1UL<<29) 1265#define I915_CRC_DONE_ENABLE (1UL<<28) 1266#define I915_GMBUS_EVENT_ENABLE (1UL<<27) 1267#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 1268#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 1269#define I915_DPST_EVENT_ENABLE (1UL<<23) 1270#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 1271#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 1272#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 1273#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 1274#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 1275#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 1276#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 1277#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 1278#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 1279#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 1280#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 1281#define I915_DPST_EVENT_STATUS (1UL<<7) 1282#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 1283#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 1284#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 1285#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1286#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 1287#define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 1288 1289/* GM45+ just has to be different */ 1290#define PIPEA_FRMCOUNT_GM45 0x70040 1291#define PIPEA_FLIPCOUNT_GM45 0x70044 1292#define PIPEB_FRMCOUNT_GM45 0x71040 1293#define PIPEB_FLIPCOUNT_GM45 0x71044 1294 1295/* 1296 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 1297 * of video memory available to the BIOS in SWF1. 1298 */ 1299 1300#define SWF0 0x71410 1301 1302/* 1303 * 855 scratch registers. 1304 */ 1305#define SWF10 0x70410 1306 1307#define SWF30 0x72414 1308 1309/* IGDNG */ 1310 1311#define CPU_VGACNTRL 0x41000 1312 1313#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 1314#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 1315#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 1316#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 1317#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 1318#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 1319#define DIGITAL_PORTA_NO_DETECT (0 << 0) 1320#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 1321#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 1322 1323/* refresh rate hardware control */ 1324#define RR_HW_CTL 0x45300 1325#define RR_HW_LOW_POWER_FRAMES_MASK 0xff 1326#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 1327 1328#define FDI_PLL_BIOS_0 0x46000 1329#define FDI_PLL_BIOS_1 0x46004 1330#define FDI_PLL_BIOS_2 0x46008 1331#define DISPLAY_PORT_PLL_BIOS_0 0x4600c 1332#define DISPLAY_PORT_PLL_BIOS_1 0x46010 1333#define DISPLAY_PORT_PLL_BIOS_2 0x46014 1334 1335#define FDI_PLL_FREQ_CTL 0x46030 1336#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 1337#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 1338#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 1339 1340 1341#define PIPEA_DATA_M1 0x60030 1342#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 1343#define TU_SIZE_MASK 0x7e000000 1344#define PIPEA_DATA_M1_OFFSET 0 1345#define PIPEA_DATA_N1 0x60034 1346#define PIPEA_DATA_N1_OFFSET 0 1347 1348#define PIPEA_DATA_M2 0x60038 1349#define PIPEA_DATA_M2_OFFSET 0 1350#define PIPEA_DATA_N2 0x6003c 1351#define PIPEA_DATA_N2_OFFSET 0 1352 1353#define PIPEA_LINK_M1 0x60040 1354#define PIPEA_LINK_M1_OFFSET 0 1355#define PIPEA_LINK_N1 0x60044 1356#define PIPEA_LINK_N1_OFFSET 0 1357 1358#define PIPEA_LINK_M2 0x60048 1359#define PIPEA_LINK_M2_OFFSET 0 1360#define PIPEA_LINK_N2 0x6004c 1361#define PIPEA_LINK_N2_OFFSET 0 1362 1363/* PIPEB timing regs are same start from 0x61000 */ 1364 1365#define PIPEB_DATA_M1 0x61030 1366#define PIPEB_DATA_M1_OFFSET 0 1367#define PIPEB_DATA_N1 0x61034 1368#define PIPEB_DATA_N1_OFFSET 0 1369 1370#define PIPEB_DATA_M2 0x61038 1371#define PIPEB_DATA_M2_OFFSET 0 1372#define PIPEB_DATA_N2 0x6103c 1373#define PIPEB_DATA_N2_OFFSET 0 1374 1375#define PIPEB_LINK_M1 0x61040 1376#define PIPEB_LINK_M1_OFFSET 0 1377#define PIPEB_LINK_N1 0x61044 1378#define PIPEB_LINK_N1_OFFSET 0 1379 1380#define PIPEB_LINK_M2 0x61048 1381#define PIPEB_LINK_M2_OFFSET 0 1382#define PIPEB_LINK_N2 0x6104c 1383#define PIPEB_LINK_N2_OFFSET 0 1384 1385/* CPU panel fitter */ 1386#define PFA_CTL_1 0x68080 1387#define PFB_CTL_1 0x68880 1388#define PF_ENABLE (1<<31) 1389 1390/* legacy palette */ 1391#define LGC_PALETTE_A 0x4a000 1392#define LGC_PALETTE_B 0x4a800 1393 1394/* interrupts */ 1395#define DE_MASTER_IRQ_CONTROL (0x80000000) 1396#define DE_SPRITEB_FLIP_DONE (1 << 29) 1397#define DE_SPRITEA_FLIP_DONE (1 << 28) 1398#define DE_PLANEB_FLIP_DONE (1 << 27) 1399#define DE_PLANEA_FLIP_DONE (1 << 26) 1400#define DE_PCU_EVENT (1 << 25) 1401#define DE_GTT_FAULT (1 << 24) 1402#define DE_POISON (1 << 23) 1403#define DE_PERFORM_COUNTER (1 << 22) 1404#define DE_PCH_EVENT (1 << 21) 1405#define DE_AUX_CHANNEL_A (1 << 20) 1406#define DE_DP_A_HOTPLUG (1 << 19) 1407#define DE_GSE (1 << 18) 1408#define DE_PIPEB_VBLANK (1 << 15) 1409#define DE_PIPEB_EVEN_FIELD (1 << 14) 1410#define DE_PIPEB_ODD_FIELD (1 << 13) 1411#define DE_PIPEB_LINE_COMPARE (1 << 12) 1412#define DE_PIPEB_VSYNC (1 << 11) 1413#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 1414#define DE_PIPEA_VBLANK (1 << 7) 1415#define DE_PIPEA_EVEN_FIELD (1 << 6) 1416#define DE_PIPEA_ODD_FIELD (1 << 5) 1417#define DE_PIPEA_LINE_COMPARE (1 << 4) 1418#define DE_PIPEA_VSYNC (1 << 3) 1419#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 1420 1421#define DEISR 0x44000 1422#define DEIMR 0x44004 1423#define DEIIR 0x44008 1424#define DEIER 0x4400c 1425 1426/* GT interrupt */ 1427#define GT_SYNC_STATUS (1 << 2) 1428#define GT_USER_INTERRUPT (1 << 0) 1429 1430#define GTISR 0x44010 1431#define GTIMR 0x44014 1432#define GTIIR 0x44018 1433#define GTIER 0x4401c 1434 1435/* PCH */ 1436 1437/* south display engine interrupt */ 1438#define SDE_CRT_HOTPLUG (1 << 11) 1439#define SDE_PORTD_HOTPLUG (1 << 10) 1440#define SDE_PORTC_HOTPLUG (1 << 9) 1441#define SDE_PORTB_HOTPLUG (1 << 8) 1442#define SDE_SDVOB_HOTPLUG (1 << 6) 1443 1444#define SDEISR 0xc4000 1445#define SDEIMR 0xc4004 1446#define SDEIIR 0xc4008 1447#define SDEIER 0xc400c 1448 1449/* digital port hotplug */ 1450#define PCH_PORT_HOTPLUG 0xc4030 1451#define PORTD_HOTPLUG_ENABLE (1 << 20) 1452#define PORTD_PULSE_DURATION_2ms (0) 1453#define PORTD_PULSE_DURATION_4_5ms (1 << 18) 1454#define PORTD_PULSE_DURATION_6ms (2 << 18) 1455#define PORTD_PULSE_DURATION_100ms (3 << 18) 1456#define PORTD_HOTPLUG_NO_DETECT (0) 1457#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 1458#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) 1459#define PORTC_HOTPLUG_ENABLE (1 << 12) 1460#define PORTC_PULSE_DURATION_2ms (0) 1461#define PORTC_PULSE_DURATION_4_5ms (1 << 10) 1462#define PORTC_PULSE_DURATION_6ms (2 << 10) 1463#define PORTC_PULSE_DURATION_100ms (3 << 10) 1464#define PORTC_HOTPLUG_NO_DETECT (0) 1465#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 1466#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) 1467#define PORTB_HOTPLUG_ENABLE (1 << 4) 1468#define PORTB_PULSE_DURATION_2ms (0) 1469#define PORTB_PULSE_DURATION_4_5ms (1 << 2) 1470#define PORTB_PULSE_DURATION_6ms (2 << 2) 1471#define PORTB_PULSE_DURATION_100ms (3 << 2) 1472#define PORTB_HOTPLUG_NO_DETECT (0) 1473#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 1474#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) 1475 1476#define PCH_GPIOA 0xc5010 1477#define PCH_GPIOB 0xc5014 1478#define PCH_GPIOC 0xc5018 1479#define PCH_GPIOD 0xc501c 1480#define PCH_GPIOE 0xc5020 1481#define PCH_GPIOF 0xc5024 1482 1483#define PCH_DPLL_A 0xc6014 1484#define PCH_DPLL_B 0xc6018 1485 1486#define PCH_FPA0 0xc6040 1487#define PCH_FPA1 0xc6044 1488#define PCH_FPB0 0xc6048 1489#define PCH_FPB1 0xc604c 1490 1491#define PCH_DPLL_TEST 0xc606c 1492 1493#define PCH_DREF_CONTROL 0xC6200 1494#define DREF_CONTROL_MASK 0x7fc3 1495#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 1496#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 1497#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 1498#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 1499#define DREF_SSC_SOURCE_DISABLE (0<<11) 1500#define DREF_SSC_SOURCE_ENABLE (2<<11) 1501#define DREF_SSC_SOURCE_MASK (2<<11) 1502#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 1503#define DREF_NONSPREAD_CK505_ENABLE (1<<9) 1504#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 1505#define DREF_NONSPREAD_SOURCE_MASK (2<<9) 1506#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 1507#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 1508#define DREF_SSC4_DOWNSPREAD (0<<6) 1509#define DREF_SSC4_CENTERSPREAD (1<<6) 1510#define DREF_SSC1_DISABLE (0<<1) 1511#define DREF_SSC1_ENABLE (1<<1) 1512#define DREF_SSC4_DISABLE (0) 1513#define DREF_SSC4_ENABLE (1) 1514 1515#define PCH_RAWCLK_FREQ 0xc6204 1516#define FDL_TP1_TIMER_SHIFT 12 1517#define FDL_TP1_TIMER_MASK (3<<12) 1518#define FDL_TP2_TIMER_SHIFT 10 1519#define FDL_TP2_TIMER_MASK (3<<10) 1520#define RAWCLK_FREQ_MASK 0x3ff 1521 1522#define PCH_DPLL_TMR_CFG 0xc6208 1523 1524#define PCH_SSC4_PARMS 0xc6210 1525#define PCH_SSC4_AUX_PARMS 0xc6214 1526 1527/* transcoder */ 1528 1529#define TRANS_HTOTAL_A 0xe0000 1530#define TRANS_HTOTAL_SHIFT 16 1531#define TRANS_HACTIVE_SHIFT 0 1532#define TRANS_HBLANK_A 0xe0004 1533#define TRANS_HBLANK_END_SHIFT 16 1534#define TRANS_HBLANK_START_SHIFT 0 1535#define TRANS_HSYNC_A 0xe0008 1536#define TRANS_HSYNC_END_SHIFT 16 1537#define TRANS_HSYNC_START_SHIFT 0 1538#define TRANS_VTOTAL_A 0xe000c 1539#define TRANS_VTOTAL_SHIFT 16 1540#define TRANS_VACTIVE_SHIFT 0 1541#define TRANS_VBLANK_A 0xe0010 1542#define TRANS_VBLANK_END_SHIFT 16 1543#define TRANS_VBLANK_START_SHIFT 0 1544#define TRANS_VSYNC_A 0xe0014 1545#define TRANS_VSYNC_END_SHIFT 16 1546#define TRANS_VSYNC_START_SHIFT 0 1547 1548#define TRANSA_DATA_M1 0xe0030 1549#define TRANSA_DATA_N1 0xe0034 1550#define TRANSA_DATA_M2 0xe0038 1551#define TRANSA_DATA_N2 0xe003c 1552#define TRANSA_DP_LINK_M1 0xe0040 1553#define TRANSA_DP_LINK_N1 0xe0044 1554#define TRANSA_DP_LINK_M2 0xe0048 1555#define TRANSA_DP_LINK_N2 0xe004c 1556 1557#define TRANS_HTOTAL_B 0xe1000 1558#define TRANS_HBLANK_B 0xe1004 1559#define TRANS_HSYNC_B 0xe1008 1560#define TRANS_VTOTAL_B 0xe100c 1561#define TRANS_VBLANK_B 0xe1010 1562#define TRANS_VSYNC_B 0xe1014 1563 1564#define TRANSB_DATA_M1 0xe1030 1565#define TRANSB_DATA_N1 0xe1034 1566#define TRANSB_DATA_M2 0xe1038 1567#define TRANSB_DATA_N2 0xe103c 1568#define TRANSB_DP_LINK_M1 0xe1040 1569#define TRANSB_DP_LINK_N1 0xe1044 1570#define TRANSB_DP_LINK_M2 0xe1048 1571#define TRANSB_DP_LINK_N2 0xe104c 1572 1573#define TRANSACONF 0xf0008 1574#define TRANSBCONF 0xf1008 1575#define TRANS_DISABLE (0<<31) 1576#define TRANS_ENABLE (1<<31) 1577#define TRANS_STATE_MASK (1<<30) 1578#define TRANS_STATE_DISABLE (0<<30) 1579#define TRANS_STATE_ENABLE (1<<30) 1580#define TRANS_FSYNC_DELAY_HB1 (0<<27) 1581#define TRANS_FSYNC_DELAY_HB2 (1<<27) 1582#define TRANS_FSYNC_DELAY_HB3 (2<<27) 1583#define TRANS_FSYNC_DELAY_HB4 (3<<27) 1584#define TRANS_DP_AUDIO_ONLY (1<<26) 1585#define TRANS_DP_VIDEO_AUDIO (0<<26) 1586#define TRANS_PROGRESSIVE (0<<21) 1587#define TRANS_8BPC (0<<5) 1588#define TRANS_10BPC (1<<5) 1589#define TRANS_6BPC (2<<5) 1590#define TRANS_12BPC (3<<5) 1591 1592#define FDI_RXA_CHICKEN 0xc200c 1593#define FDI_RXB_CHICKEN 0xc2010 1594#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1) 1595 1596/* CPU: FDI_TX */ 1597#define FDI_TXA_CTL 0x60100 1598#define FDI_TXB_CTL 0x61100 1599#define FDI_TX_DISABLE (0<<31) 1600#define FDI_TX_ENABLE (1<<31) 1601#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 1602#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 1603#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 1604#define FDI_LINK_TRAIN_NONE (3<<28) 1605#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 1606#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 1607#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 1608#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 1609#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 1610#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 1611#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 1612#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 1613#define FDI_DP_PORT_WIDTH_X1 (0<<19) 1614#define FDI_DP_PORT_WIDTH_X2 (1<<19) 1615#define FDI_DP_PORT_WIDTH_X3 (2<<19) 1616#define FDI_DP_PORT_WIDTH_X4 (3<<19) 1617#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 1618/* IGDNG: hardwired to 1 */ 1619#define FDI_TX_PLL_ENABLE (1<<14) 1620/* both Tx and Rx */ 1621#define FDI_SCRAMBLING_ENABLE (0<<7) 1622#define FDI_SCRAMBLING_DISABLE (1<<7) 1623 1624/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 1625#define FDI_RXA_CTL 0xf000c 1626#define FDI_RXB_CTL 0xf100c 1627#define FDI_RX_ENABLE (1<<31) 1628#define FDI_RX_DISABLE (0<<31) 1629/* train, dp width same as FDI_TX */ 1630#define FDI_DP_PORT_WIDTH_X8 (7<<19) 1631#define FDI_8BPC (0<<16) 1632#define FDI_10BPC (1<<16) 1633#define FDI_6BPC (2<<16) 1634#define FDI_12BPC (3<<16) 1635#define FDI_LINK_REVERSE_OVERWRITE (1<<15) 1636#define FDI_DMI_LINK_REVERSE_MASK (1<<14) 1637#define FDI_RX_PLL_ENABLE (1<<13) 1638#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 1639#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 1640#define FDI_FS_ERR_REPORT_ENABLE (1<<9) 1641#define FDI_FE_ERR_REPORT_ENABLE (1<<8) 1642#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 1643#define FDI_SEL_RAWCLK (0<<4) 1644#define FDI_SEL_PCDCLK (1<<4) 1645 1646#define FDI_RXA_MISC 0xf0010 1647#define FDI_RXB_MISC 0xf1010 1648#define FDI_RXA_TUSIZE1 0xf0030 1649#define FDI_RXA_TUSIZE2 0xf0038 1650#define FDI_RXB_TUSIZE1 0xf1030 1651#define FDI_RXB_TUSIZE2 0xf1038 1652 1653/* FDI_RX interrupt register format */ 1654#define FDI_RX_INTER_LANE_ALIGN (1<<10) 1655#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 1656#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 1657#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 1658#define FDI_RX_FS_CODE_ERR (1<<6) 1659#define FDI_RX_FE_CODE_ERR (1<<5) 1660#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 1661#define FDI_RX_HDCP_LINK_FAIL (1<<3) 1662#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 1663#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 1664#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 1665 1666#define FDI_RXA_IIR 0xf0014 1667#define FDI_RXA_IMR 0xf0018 1668#define FDI_RXB_IIR 0xf1014 1669#define FDI_RXB_IMR 0xf1018 1670 1671#define FDI_PLL_CTL_1 0xfe000 1672#define FDI_PLL_CTL_2 0xfe004 1673 1674/* CRT */ 1675#define PCH_ADPA 0xe1100 1676#define ADPA_TRANS_SELECT_MASK (1<<30) 1677#define ADPA_TRANS_A_SELECT 0 1678#define ADPA_TRANS_B_SELECT (1<<30) 1679#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 1680#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 1681#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 1682#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 1683#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 1684#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 1685#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 1686#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 1687#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 1688#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 1689#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 1690#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 1691#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 1692#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 1693#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 1694#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 1695#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 1696#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 1697#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 1698 1699/* or SDVOB */ 1700#define HDMIB 0xe1140 1701#define PORT_ENABLE (1 << 31) 1702#define TRANSCODER_A (0) 1703#define TRANSCODER_B (1 << 30) 1704#define COLOR_FORMAT_8bpc (0) 1705#define COLOR_FORMAT_12bpc (3 << 26) 1706#define SDVOB_HOTPLUG_ENABLE (1 << 23) 1707#define SDVO_ENCODING (0) 1708#define TMDS_ENCODING (2 << 10) 1709#define NULL_PACKET_VSYNC_ENABLE (1 << 9) 1710#define SDVOB_BORDER_ENABLE (1 << 7) 1711#define AUDIO_ENABLE (1 << 6) 1712#define VSYNC_ACTIVE_HIGH (1 << 4) 1713#define HSYNC_ACTIVE_HIGH (1 << 3) 1714#define PORT_DETECTED (1 << 2) 1715 1716#define HDMIC 0xe1150 1717#define HDMID 0xe1160 1718 1719#define PCH_LVDS 0xe1180 1720#define LVDS_DETECTED (1 << 1) 1721 1722#define BLC_PWM_CPU_CTL2 0x48250 1723#define PWM_ENABLE (1 << 31) 1724#define PWM_PIPE_A (0 << 29) 1725#define PWM_PIPE_B (1 << 29) 1726#define BLC_PWM_CPU_CTL 0x48254 1727 1728#define BLC_PWM_PCH_CTL1 0xc8250 1729#define PWM_PCH_ENABLE (1 << 31) 1730#define PWM_POLARITY_ACTIVE_LOW (1 << 29) 1731#define PWM_POLARITY_ACTIVE_HIGH (0 << 29) 1732#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28) 1733#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28) 1734 1735#define BLC_PWM_PCH_CTL2 0xc8254 1736 1737#define PCH_PP_STATUS 0xc7200 1738#define PCH_PP_CONTROL 0xc7204 1739#define EDP_FORCE_VDD (1 << 3) 1740#define EDP_BLC_ENABLE (1 << 2) 1741#define PANEL_POWER_RESET (1 << 1) 1742#define PANEL_POWER_OFF (0 << 0) 1743#define PANEL_POWER_ON (1 << 0) 1744#define PCH_PP_ON_DELAYS 0xc7208 1745#define EDP_PANEL (1 << 30) 1746#define PCH_PP_OFF_DELAYS 0xc720c 1747#define PCH_PP_DIVISOR 0xc7210 1748 1749#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 1750#define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 1751#define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 1752#define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 1753#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 1754#define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 1755#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 1756#define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 1757#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 1758#define PCI_DEVICE_ID_INTEL_82946_GZ 0x2972 1759#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 1760#define PCI_DEVICE_ID_INTEL_82Q963_IG 0x2992 1761#define PCI_DEVICE_ID_INTEL_82G965_IG 0x29a2 1762#define PCI_DEVICE_ID_INTEL_GM965_IG 0x2a02 1763#define PCI_DEVICE_ID_INTEL_GME965_IG 0x2a12 1764#define PCI_DEVICE_ID_INTEL_82G33_IG 0x29c2 1765#define PCI_DEVICE_ID_INTEL_82Q35_IG 0x29b2 1766#define PCI_DEVICE_ID_INTEL_82Q33_IG 0x29d2 1767#define PCI_DEVICE_ID_INTEL_CANTIGA_IG 0x2a42 1768#define PCI_DEVICE_ID_INTEL_EL_IG 0x2e02 1769#define PCI_DEVICE_ID_INTEL_82Q45_IG 0x2e12 1770#define PCI_DEVICE_ID_INTEL_82G45_IG 0x2e22 1771#define PCI_DEVICE_ID_INTEL_82G41_IG 0x2e32 1772#define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x42 1773#define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x46 1774#define PCI_DEVICE_ID_INTEL_82B43_IG 0x2e42 1775 1776 1777#define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC) 1778#define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG) 1779#define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 1780#define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 1781#define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG) 1782 1783#define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG) 1784#define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG) 1785#define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG) 1786#define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG || \ 1787 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GME_IG) 1788 1789#define IS_IGDNG_D(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_IGDNG_D_IG) 1790#define IS_IGDNG_M(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_IGDNG_M_IG) 1791#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev)) 1792 1793#define IS_I965G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82946_GZ || \ 1794 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G35_IG || \ 1795 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q963_IG || \ 1796 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G965_IG || \ 1797 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG || \ 1798 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GME965_IG || \ 1799 (dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG || \ 1800 (dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 1801 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 1802 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG || \ 1803 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82B43_IG || \ 1804 (dev)->pci_device == PCI_DEVICE_ID_INTEL_IGDNG_D_IG || \ 1805 (dev)->pci_device == PCI_DEVICE_ID_INTEL_IGDNG_M_IG || \ 1806 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G41_IG) 1807 1808#define IS_I965GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG) 1809 1810#define IS_GM45(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG) 1811 1812#define IS_G4X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 1813 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 1814 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG || \ 1815 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82B43_IG || \ 1816 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G41_IG) 1817 1818#define IS_G33(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82G33_IG || \ 1819 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q35_IG || \ 1820 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q33_IG) 1821 1822#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1823 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \ 1824 IS_IGDNG(dev)) 1825 1826#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1827 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ 1828 IS_IGDNG_M(dev)) 1829 1830#define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1831#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1832#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1833 1834#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \ 1835 IS_IGDNG(dev)) 1836/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1837 * rows, which changed the alignment requirements and fence programming. 1838 */ 1839#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 1840 IS_I915GM(dev))) 1841 1842#endif /* _I915_DRV_H */ 1843