ata_common.c revision 7656:2621e50fdf4a
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#include <sys/types.h> 28#include <sys/modctl.h> 29#include <sys/debug.h> 30#include <sys/promif.h> 31#include <sys/pci.h> 32#include <sys/errno.h> 33#include <sys/open.h> 34#include <sys/uio.h> 35#include <sys/cred.h> 36#include <sys/cpu.h> 37#include "ata_common.h" 38#include "ata_disk.h" 39#include "atapi.h" 40#include "ata_blacklist.h" 41#include "sil3xxx.h" 42 43/* 44 * Solaris Entry Points. 45 */ 46 47static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 48static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 49static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 50 void *a, void *v); 51static uint_t ata_intr(caddr_t arg); 52 53/* 54 * GHD Entry points 55 */ 56 57static int ata_get_status(void *hba_handle, void *intr_status); 58static void ata_process_intr(void *hba_handle, void *intr_status); 59static int ata_hba_start(void *handle, gcmd_t *gcmdp); 60static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 61static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 62 gtgt_t *gtgtp, gact_t action, int calltype); 63 64/* 65 * Local Function Prototypes 66 */ 67static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 68 uint_t flags, char *name, int defvalue); 69static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 70 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 71 int *DoneFlgp); 72static void ata_destroy_controller(dev_info_t *dip); 73static int ata_drive_type(uchar_t drvhd, 74 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 75 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 76 struct ata_id *ata_id_bufp); 77static ata_ctl_t *ata_init_controller(dev_info_t *dip); 78static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 79 uchar_t targ, uchar_t lun); 80static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 81 dev_info_t *tdip); 82static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 83static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 84static int ata_reset_bus(ata_ctl_t *ata_ctlp); 85static int ata_setup_ioaddr(dev_info_t *dip, 86 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 87 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 88 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 89static int ata_software_reset(ata_ctl_t *ata_ctlp); 90static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 91 ata_pkt_t *ata_pktp); 92static int ata_strncmp(char *p1, char *p2, int cnt); 93static void ata_uninit_drive(ata_drv_t *ata_drvp); 94 95static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 96static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 97static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 98static int ata_spec_init_controller(dev_info_t *dip); 99 100static void ata_init_pm(dev_info_t *); 101static int ata_suspend(dev_info_t *); 102static int ata_resume(dev_info_t *); 103static int ata_power(dev_info_t *, int, int); 104static int ata_change_power(dev_info_t *, uint8_t); 105static int ata_is_pci(dev_info_t *); 106static void ata_disable_DMA(ata_drv_t *ata_drvp); 107 108/* 109 * Local static data 110 */ 111static void *ata_state; 112 113static tmr_t ata_timer_conf; /* single timeout list for all instances */ 114static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 115 116int ata_hba_start_watchdog = 1000; 117int ata_process_intr_watchdog = 1000; 118int ata_reset_bus_watchdog = 1000; 119 120 121/* 122 * Use local or framework power management 123 */ 124 125#ifdef ATA_USE_AUTOPM 126#define ATA_BUSY_COMPONENT(d, c) ((void)pm_busy_component(d, c)) 127#define ATA_IDLE_COMPONENT(d, c) ((void)pm_idle_component(d, c)) 128#define ATA_RAISE_POWER(d, c, l) pm_raise_power(d, c, l) 129#define ATA_LOWER_POWER(d, c, l) pm_lower_power(d, c, l) 130#else 131#define ATA_BUSY_COMPONENT(d, c) 132#define ATA_IDLE_COMPONENT(d, c) 133#define ATA_RAISE_POWER(d, c, l) ata_power(d, c, l) 134#define ATA_LOWER_POWER(d, c, l) ata_power(d, c, l) 135#endif 136/* 137 * number of seconds to wait during various operations 138 */ 139int ata_flush_delay = 5 * 1000000; 140uint_t ata_set_feature_wait = 4 * 1000000; 141uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 142 143/* 144 * Change this for SFF-8070i support. Currently SFF-8070i is 145 * using a field in the IDENTIFY PACKET DEVICE response which 146 * already seems to be in use by some vendor's drives. I suspect 147 * SFF will either move their laslun field or provide a reliable 148 * way to validate it. 149 */ 150int ata_enable_atapi_luns = FALSE; 151 152/* 153 * set this to disable all DMA requests 154 */ 155int ata_dma_disabled = FALSE; 156 157/* 158 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 159 * "ata" or "atapi" property. 160 */ 161int ata_id_debug = FALSE; 162 163/* 164 * set this to TRUE to enable logging device-capability data 165 */ 166int ata_capability_data = FALSE; 167 168/* 169 * DMA selection message pointers 170 */ 171char *ata_cntrl_DMA_sel_msg; 172char *ata_dev_DMA_sel_msg; 173 174/* 175 * bus nexus operations 176 */ 177static struct bus_ops ata_bus_ops; 178static struct bus_ops *scsa_bus_ops_p; 179 180/* ARGSUSED */ 181static int 182ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 183{ 184 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 185 return (ENXIO); 186 187 return (0); 188} 189 190/* 191 * The purpose of this function is to pass the ioaddress of the controller 192 * to the caller, specifically used for upgrade from pre-pciide 193 * to pciide nodes 194 */ 195/* ARGSUSED */ 196static int 197ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 198{ 199 ata_ctl_t *ata_ctlp; 200 char buf[18]; 201 long len; 202 203 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 204 205 if (ata_ctlp == NULL) 206 return (ENXIO); 207 208 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 209 210 len = strlen(buf) - uio_p->uio_offset; 211 len = min(uio_p->uio_resid, len); 212 if (len <= 0) 213 return (0); 214 215 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 216 UIO_READ, uio_p)); 217} 218 219int 220ata_devo_reset( 221 dev_info_t *dip, 222 ddi_reset_cmd_t cmd) 223{ 224 ata_ctl_t *ata_ctlp; 225 ata_drv_t *ata_drvp; 226 int instance; 227 int i; 228 int rc; 229 int flush_okay; 230 231 if (cmd != DDI_RESET_FORCE) 232 return (0); 233 234 instance = ddi_get_instance(dip); 235 ata_ctlp = ddi_get_soft_state(ata_state, instance); 236 237 if (!ata_ctlp) 238 return (0); 239 240 /* 241 * reset ATA drives and flush the write cache of any drives 242 */ 243 flush_okay = TRUE; 244 for (i = 0; i < ATA_MAXTARG; i++) { 245 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 246 continue; 247 /* Don't revert to defaults for certain IBM drives */ 248 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 249 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 250 /* Enable revert to defaults when reset */ 251 (void) ata_set_feature(ata_ctlp, ata_drvp, 252 ATSF_ENA_REVPOD, 0); 253 } 254 255 /* 256 * skip flush cache if device type is cdrom 257 * 258 * notes: the structure definitions for ata_drvp->ad_id are 259 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 260 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 261 */ 262 if (!IS_CDROM(ata_drvp)) { 263 264 /* 265 * Try the ATA/ATAPI flush write cache command 266 */ 267 rc = ata_flush_cache(ata_ctlp, ata_drvp); 268 ADBG_WARN(("ata_flush_cache %s\n", 269 rc ? "okay" : "failed")); 270 271 if (!rc) 272 flush_okay = FALSE; 273 } 274 275 276 /* 277 * do something else if flush cache not supported 278 */ 279 } 280 281 /* 282 * just busy wait if any drive doesn't support FLUSH CACHE 283 */ 284 if (!flush_okay) 285 drv_usecwait(ata_flush_delay); 286 return (0); 287} 288 289/* 290 * quiesce(9E) entry point. 291 * 292 * This function is called when the system is single-threaded at high 293 * PIL with preemption disabled. Therefore, this function must not be 294 * blocked. 295 * 296 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 297 * DDI_FAILURE indicates an error condition and should almost never happen. 298 */ 299int 300ata_quiesce(dev_info_t *dip) 301{ 302#ifdef ATA_DEBUG 303 /* 304 * Turn off debugging 305 */ 306 ata_debug = 0; 307#endif 308 309 return (ata_devo_reset(dip, DDI_RESET_FORCE)); 310} 311 312 313static struct cb_ops ata_cb_ops = { 314 ata_open, /* open */ 315 nulldev, /* close */ 316 nodev, /* strategy */ 317 nodev, /* print */ 318 nodev, /* dump */ 319 ata_read, /* read */ 320 nodev, /* write */ 321 nodev, /* ioctl */ 322 nodev, /* devmap */ 323 nodev, /* mmap */ 324 nodev, /* segmap */ 325 nochpoll, /* chpoll */ 326 ddi_prop_op, /* prop_op */ 327 NULL, /* stream info */ 328 D_MP, /* driver compatibility flag */ 329 CB_REV, /* cb_ops revision */ 330 nodev, /* aread */ 331 nodev /* awrite */ 332}; 333 334static struct dev_ops ata_ops = { 335 DEVO_REV, /* devo_rev, */ 336 0, /* refcnt */ 337 ddi_getinfo_1to1, /* info */ 338 nulldev, /* identify */ 339 NULL, /* probe */ 340 ata_attach, /* attach */ 341 ata_detach, /* detach */ 342 ata_devo_reset, /* reset */ 343 &ata_cb_ops, /* driver operations */ 344 NULL, /* bus operations */ 345 ata_power, /* power */ 346 ata_quiesce /* quiesce */ 347}; 348 349/* driver loadable module wrapper */ 350static struct modldrv modldrv = { 351 &mod_driverops, /* Type of module. This one is a driver */ 352 "ATA AT-bus attachment disk controller Driver", /* module name */ 353 &ata_ops, /* driver ops */ 354}; 355 356static struct modlinkage modlinkage = { 357 MODREV_1, (void *)&modldrv, NULL 358}; 359 360#ifdef ATA_DEBUG 361int ata_debug_init = FALSE; 362int ata_debug_attach = FALSE; 363 364int ata_debug = ADBG_FLAG_ERROR 365 /* | ADBG_FLAG_ARQ */ 366 /* | ADBG_FLAG_INIT */ 367 /* | ADBG_FLAG_TRACE */ 368 /* | ADBG_FLAG_TRANSPORT */ 369 /* | ADBG_FLAG_WARN */ 370 ; 371#endif 372 373int 374_init(void) 375{ 376 int err; 377 378#ifdef ATA_DEBUG 379 if (ata_debug_init) 380 debug_enter("\nATA _INIT\n"); 381#endif 382 383 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 384 return (err); 385 386 if ((err = scsi_hba_init(&modlinkage)) != 0) { 387 ddi_soft_state_fini(&ata_state); 388 return (err); 389 } 390 391 /* save pointer to SCSA provided bus_ops struct */ 392 scsa_bus_ops_p = ata_ops.devo_bus_ops; 393 394 /* make a copy of SCSA bus_ops */ 395 ata_bus_ops = *(ata_ops.devo_bus_ops); 396 397 /* 398 * Modify our bus_ops to call our routines. Our implementation 399 * will determine if the device is ATA or ATAPI/SCSA and react 400 * accordingly. 401 */ 402 ata_bus_ops.bus_ctl = ata_bus_ctl; 403 404 /* patch our bus_ops into the dev_ops struct */ 405 ata_ops.devo_bus_ops = &ata_bus_ops; 406 407 if ((err = mod_install(&modlinkage)) != 0) { 408 scsi_hba_fini(&modlinkage); 409 ddi_soft_state_fini(&ata_state); 410 } 411 412 /* 413 * Initialize the per driver timer info. 414 */ 415 416 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 417 418 return (err); 419} 420 421int 422_fini(void) 423{ 424 int err; 425 426 if ((err = mod_remove(&modlinkage)) == 0) { 427 ghd_timer_fini(&ata_timer_conf); 428 scsi_hba_fini(&modlinkage); 429 ddi_soft_state_fini(&ata_state); 430 } 431 432 return (err); 433} 434 435int 436_info(struct modinfo *modinfop) 437{ 438 return (mod_info(&modlinkage, modinfop)); 439} 440 441 442/* 443 * 444 * driver attach entry point 445 * 446 */ 447 448static int 449ata_attach( 450 dev_info_t *dip, 451 ddi_attach_cmd_t cmd) 452{ 453 ata_ctl_t *ata_ctlp; 454 ata_drv_t *ata_drvp; 455 ata_drv_t *first_drvp = NULL; 456 uchar_t targ; 457 uchar_t lun; 458 uchar_t lastlun; 459 int atapi_count = 0; 460 int disk_count = 0; 461 462 ADBG_TRACE(("ata_attach entered\n")); 463#ifdef ATA_DEBUG 464 if (ata_debug_attach) 465 debug_enter("\nATA_ATTACH\n\n"); 466#endif 467 468 switch (cmd) { 469 case DDI_ATTACH: 470 break; 471 case DDI_RESUME: 472 return (ata_resume(dip)); 473 default: 474 return (DDI_FAILURE); 475 } 476 477 /* initialize controller */ 478 ata_ctlp = ata_init_controller(dip); 479 480 if (ata_ctlp == NULL) 481 goto errout; 482 483 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 484 485 /* initialize drives */ 486 487 for (targ = 0; targ < ATA_MAXTARG; targ++) { 488 489 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 490 if (ata_drvp == NULL) 491 continue; 492 493 if (first_drvp == NULL) 494 first_drvp = ata_drvp; 495 496 if (ATAPIDRV(ata_drvp)) { 497 atapi_count++; 498 lastlun = ata_drvp->ad_id.ai_lastlun; 499 } else { 500 disk_count++; 501 lastlun = 0; 502 } 503 504 /* 505 * LUN support is currently disabled. Check with SFF-8070i 506 * before enabling. 507 */ 508 if (!ata_enable_atapi_luns) 509 lastlun = 0; 510 511 /* Initialize higher LUNs, if there are any */ 512 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 513 if ((ata_drvp = 514 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 515 ata_show_transfer_mode(ata_ctlp, ata_drvp); 516 } 517 } 518 } 519 520 if ((atapi_count == 0) && (disk_count == 0)) { 521 ADBG_WARN(("ata_attach: no drives detected\n")); 522 goto errout1; 523 } 524 525 /* 526 * Always make certain that a valid drive is selected so 527 * that routines which poll the status register don't get 528 * confused by non-existent drives. 529 */ 530 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 531 first_drvp->ad_drive_bits); 532 ata_nsecwait(400); 533 534 /* 535 * make certain the drive selected 536 */ 537 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 538 0, ATS_BSY, 5000000)) { 539 ADBG_ERROR(("ata_attach: select failed\n")); 540 } 541 542 /* 543 * initialize atapi/ata_dsk modules if we have at least 544 * one drive of that type. 545 */ 546 547 if (atapi_count) { 548 if (!atapi_attach(ata_ctlp)) 549 goto errout1; 550 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 551 } 552 553 if (disk_count) { 554 if (!ata_disk_attach(ata_ctlp)) 555 goto errout1; 556 ata_ctlp->ac_flags |= AC_DISK_INIT; 557 } 558 559 /* 560 * make certain the interrupt and error latches are clear 561 */ 562 if (ata_ctlp->ac_pciide) { 563 564 int instance = ddi_get_instance(dip); 565 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 566 DDI_PSEUDO, 0) != DDI_SUCCESS) { 567 goto errout1; 568 } 569 570 (void) ata_pciide_status_clear(ata_ctlp); 571 572 } 573 574 /* 575 * enable the interrupt handler and drop the mutex 576 */ 577 ata_ctlp->ac_flags |= AC_ATTACHED; 578 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 579 580 ata_init_pm(dip); 581 582 ddi_report_dev(dip); 583 return (DDI_SUCCESS); 584 585errout1: 586 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 587errout: 588 (void) ata_detach(dip, DDI_DETACH); 589 return (DDI_FAILURE); 590} 591 592/* driver detach entry point */ 593 594static int 595ata_detach( 596 dev_info_t *dip, 597 ddi_detach_cmd_t cmd) 598{ 599 ata_ctl_t *ata_ctlp; 600 ata_drv_t *ata_drvp; 601 int instance; 602 int i; 603 int j; 604 605 ADBG_TRACE(("ata_detach entered\n")); 606 607 switch (cmd) { 608 case DDI_DETACH: 609 break; 610 case DDI_SUSPEND: 611 return (ata_suspend(dip)); 612 default: 613 return (DDI_FAILURE); 614 } 615 616 instance = ddi_get_instance(dip); 617 ata_ctlp = ddi_get_soft_state(ata_state, instance); 618 619 if (!ata_ctlp) 620 return (DDI_SUCCESS); 621 622 if (ata_ctlp->ac_pm_support) { 623 ATA_BUSY_COMPONENT(dip, 0); 624 if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) { 625 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != 626 DDI_SUCCESS) { 627 ATA_IDLE_COMPONENT(dip, 0); 628 return (DDI_FAILURE); 629 } 630 } 631 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 632 } 633 ata_ctlp->ac_flags &= ~AC_ATTACHED; 634 635 /* destroy ata module */ 636 if (ata_ctlp->ac_flags & AC_DISK_INIT) 637 ata_disk_detach(ata_ctlp); 638 639 /* destroy atapi module */ 640 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 641 atapi_detach(ata_ctlp); 642 643 ddi_remove_minor_node(dip, NULL); 644 645 /* destroy drives */ 646 for (i = 0; i < ATA_MAXTARG; i++) { 647 for (j = 0; j < ATA_MAXLUN; j++) { 648 ata_drvp = CTL2DRV(ata_ctlp, i, j); 649 if (ata_drvp != NULL) 650 ata_uninit_drive(ata_drvp); 651 } 652 } 653 654 if (ata_ctlp->ac_iohandle1) 655 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 656 if (ata_ctlp->ac_iohandle2) 657 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 658 if (ata_ctlp->ac_bmhandle) 659 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 660 661 /* destroy controller */ 662 ata_destroy_controller(dip); 663 664 ddi_prop_remove_all(dip); 665 666 return (DDI_SUCCESS); 667} 668 669/* 670 * Nexus driver bus_ctl entry point 671 */ 672/*ARGSUSED*/ 673static int 674ata_bus_ctl( 675 dev_info_t *d, 676 dev_info_t *r, 677 ddi_ctl_enum_t o, 678 void *a, 679 void *v) 680{ 681 dev_info_t *tdip; 682 int target_type; 683 int rc; 684 char *bufp; 685 686 ADBG_TRACE(("ata_bus_ctl entered\n")); 687 688 switch (o) { 689 690 case DDI_CTLOPS_SIDDEV: 691 return (DDI_FAILURE); 692 693 case DDI_CTLOPS_IOMIN: 694 695 /* 696 * Since we use PIO, we return a minimum I/O size of 697 * one byte. This will need to be updated when we 698 * implement DMA support 699 */ 700 701 *((int *)v) = 1; 702 return (DDI_SUCCESS); 703 704 case DDI_CTLOPS_DMAPMAPC: 705 case DDI_CTLOPS_REPORTINT: 706 case DDI_CTLOPS_REGSIZE: 707 case DDI_CTLOPS_NREGS: 708 case DDI_CTLOPS_SLAVEONLY: 709 case DDI_CTLOPS_AFFINITY: 710 case DDI_CTLOPS_POKE: 711 case DDI_CTLOPS_PEEK: 712 713 /* These ops shouldn't be called by a target driver */ 714 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 715 ddi_driver_name(d), ddi_get_instance(d), o, 716 ddi_driver_name(r), ddi_get_instance(r))); 717 718 return (DDI_FAILURE); 719 720 case DDI_CTLOPS_REPORTDEV: 721 case DDI_CTLOPS_INITCHILD: 722 case DDI_CTLOPS_UNINITCHILD: 723 724 /* these require special handling below */ 725 break; 726 727 default: 728 return (ddi_ctlops(d, r, o, a, v)); 729 } 730 731 /* get targets dip */ 732 733 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 734 tdip = (dev_info_t *)a; 735 else 736 tdip = r; 737 738 /* 739 * XXX - Get class of target 740 * Before the "class" entry in a conf file becomes 741 * a real property, we use an additional property 742 * tentatively called "class_prop". We will require that 743 * new classes (ie. direct) export "class_prop". 744 * SCSA target drivers will not have this property, so 745 * no property implies SCSA. 746 */ 747 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 748 "class", &bufp) == DDI_PROP_SUCCESS) || 749 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 750 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 751 if (strcmp(bufp, "dada") == 0) 752 target_type = ATA_DEV_DISK; 753 else if (strcmp(bufp, "scsi") == 0) 754 target_type = ATA_DEV_ATAPI; 755 else { 756 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 757 bufp)); 758 ddi_prop_free(bufp); 759 return (DDI_FAILURE); 760 } 761 ddi_prop_free(bufp); 762 } else { 763 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 764 } 765 766 if (o == DDI_CTLOPS_INITCHILD) { 767 int instance = ddi_get_instance(d); 768 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 769 ata_drv_t *ata_drvp; 770 int targ; 771 int lun; 772 int drive_type; 773 char *disk_prop; 774 char *class_prop; 775 776 if (ata_ctlp == NULL) { 777 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 778 return (DDI_FAILURE); 779 } 780 781 /* get (target,lun) of child device */ 782 783 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 784 "target", -1); 785 if (targ == -1) { 786 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 787 return (DDI_FAILURE); 788 } 789 790 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 791 "lun", 0); 792 793 if ((targ < 0) || (targ >= ATA_MAXTARG) || 794 (lun < 0) || (lun >= ATA_MAXLUN)) { 795 return (DDI_FAILURE); 796 } 797 798 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 799 800 if (ata_drvp == NULL) 801 return (DDI_FAILURE); /* no drive */ 802 803 /* get type of device */ 804 805 if (ATAPIDRV(ata_drvp)) 806 drive_type = ATA_DEV_ATAPI; 807 else 808 drive_type = ATA_DEV_DISK; 809 810 /* 811 * Check for special handling when child driver is 812 * cmdk (which morphs to the correct interface) 813 */ 814 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 815 816 if ((target_type == ATA_DEV_DISK) && 817 (target_type != drive_type)) 818 return (DDI_FAILURE); 819 820 target_type = drive_type; 821 822 if (drive_type == ATA_DEV_ATAPI) { 823 class_prop = "scsi"; 824 } else { 825 disk_prop = "dadk"; 826 class_prop = "dada"; 827 828 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 829 "disk", disk_prop) != DDI_PROP_SUCCESS) { 830 ADBG_WARN(("ata_bus_ctl: failed to " 831 "create disk prop\n")); 832 return (DDI_FAILURE); 833 } 834 } 835 836 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 837 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 838 ADBG_WARN(("ata_bus_ctl: failed to " 839 "create class prop\n")); 840 return (DDI_FAILURE); 841 } 842 } 843 844 /* Check that target class matches the device */ 845 846 if (target_type != drive_type) 847 return (DDI_FAILURE); 848 849 /* save pointer to drive struct for ata_disk_bus_ctl */ 850 ddi_set_driver_private(tdip, ata_drvp); 851 852 /* 853 * Determine whether to enable DMA support for this drive. This 854 * check is deferred to this point so that the various dma 855 * properties could reside on the devinfo node should finer 856 * grained dma control be required. 857 */ 858 if (ata_drvp->ad_pciide_dma == ATA_DMA_UNINITIALIZED) { 859 ata_drvp->ad_pciide_dma = 860 ata_init_drive_pcidma(ata_ctlp, ata_drvp, tdip); 861 ata_show_transfer_mode(ata_ctlp, ata_drvp); 862 } 863 } 864 865 if (target_type == ATA_DEV_ATAPI) { 866 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 867 } else { 868 rc = ata_disk_bus_ctl(d, r, o, a, v); 869 } 870 871 return (rc); 872} 873 874/* 875 * 876 * GHD ccc_hba_complete callback 877 * 878 */ 879 880/* ARGSUSED */ 881static void 882ata_hba_complete( 883 void *hba_handle, 884 gcmd_t *gcmdp, 885 int do_callback) 886{ 887 ata_drv_t *ata_drvp; 888 ata_pkt_t *ata_pktp; 889 890 ADBG_TRACE(("ata_hba_complete entered\n")); 891 892 ata_drvp = GCMD2DRV(gcmdp); 893 ata_pktp = GCMD2APKT(gcmdp); 894 if (ata_pktp->ap_complete) 895 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 896 do_callback); 897} 898 899/* GHD ccc_timeout_func callback */ 900 901/* ARGSUSED */ 902static int 903ata_timeout_func( 904 void *hba_handle, 905 gcmd_t *gcmdp, 906 gtgt_t *gtgtp, 907 gact_t action, 908 int calltype) 909{ 910 ata_ctl_t *ata_ctlp; 911 ata_pkt_t *ata_pktp; 912 ata_drv_t *ata_drvp; 913 914 ADBG_TRACE(("ata_timeout_func entered\n")); 915 916 ata_ctlp = (ata_ctl_t *)hba_handle; 917 918 if (gcmdp != NULL) 919 ata_pktp = GCMD2APKT(gcmdp); 920 else 921 ata_pktp = NULL; 922 923 switch (action) { 924 case GACTION_EARLY_ABORT: 925 /* abort before request was started */ 926 if (ata_pktp != NULL) { 927 ata_pktp->ap_flags |= AP_ABORT; 928 } 929 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 930 return (TRUE); 931 932 case GACTION_EARLY_TIMEOUT: 933 /* timeout before request was started */ 934 if (ata_pktp != NULL) { 935 ata_pktp->ap_flags |= AP_TIMEOUT; 936 } 937 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 938 return (TRUE); 939 940 case GACTION_RESET_TARGET: 941 /* 942 * Reset a device is not supported. Resetting a specific 943 * device can't be done at all to an ATA device and if 944 * you send a RESET to an ATAPI device you have to 945 * reset the whole bus to make certain both devices 946 * on the bus stay in sync regarding which device is 947 * the currently selected one. 948 */ 949 return (FALSE); 950 951 case GACTION_RESET_BUS: 952 /* 953 * Issue bus reset and reinitialize both drives. 954 * But only if this is a timed-out request. Target 955 * driver reset requests are ignored because ATA 956 * and ATAPI devices shouldn't be gratuitously reset. 957 * Also disable DMA if it is a CF device. 958 */ 959 if (gcmdp == NULL) 960 break; 961 ata_drvp = GCMD2DRV(gcmdp); 962 if (ata_drvp != NULL) 963 if (ata_drvp->ad_id.ai_config == ATA_ID_CF_TO_ATA) 964 ata_disable_DMA(ata_drvp); 965 return (ata_reset_bus(ata_ctlp)); 966 default: 967 break; 968 } 969 return (FALSE); 970} 971 972/* 973 * 974 * Initialize controller's soft-state structure 975 * 976 */ 977 978static ata_ctl_t * 979ata_init_controller( 980 dev_info_t *dip) 981{ 982 ata_ctl_t *ata_ctlp; 983 int instance; 984 caddr_t ioaddr1; 985 caddr_t ioaddr2; 986 987 ADBG_TRACE(("ata_init_controller entered\n")); 988 989 instance = ddi_get_instance(dip); 990 991 /* allocate controller structure */ 992 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 993 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 994 return (NULL); 995 } 996 997 ata_ctlp = ddi_get_soft_state(ata_state, instance); 998 999 if (ata_ctlp == NULL) { 1000 ADBG_WARN(("ata_init_controller: failed to find " 1001 "controller struct\n")); 1002 return (NULL); 1003 } 1004 1005 /* 1006 * initialize per-controller data 1007 */ 1008 ata_ctlp->ac_dip = dip; 1009 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 1010 1011 /* 1012 * map the device registers 1013 */ 1014 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 1015 &ata_ctlp->ac_iohandle2, &ioaddr2, 1016 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 1017 (void) ata_detach(dip, DDI_DETACH); 1018 return (NULL); 1019 } 1020 1021 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 1022 ioaddr1, ioaddr2)); 1023 1024 /* 1025 * Do ARQ setup 1026 */ 1027 atapi_init_arq(ata_ctlp); 1028 1029 /* 1030 * Do PCI-IDE setup 1031 */ 1032 ata_init_pciide(dip, ata_ctlp); 1033 1034 /* 1035 * port addresses associated with ioaddr1 1036 */ 1037 ata_ctlp->ac_ioaddr1 = ioaddr1; 1038 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1039 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1040 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1041 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1042 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1043 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1044 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1045 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1046 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1047 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1048 1049 /* 1050 * port addresses associated with ioaddr2 1051 */ 1052 ata_ctlp->ac_ioaddr2 = ioaddr2; 1053 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1054 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1055 1056 /* 1057 * If AC_BSY_WAIT needs to be set for laptops that do 1058 * suspend/resume but do not correctly wait for the busy bit to 1059 * drop after a resume. 1060 */ 1061 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1062 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1063 /* 1064 * get max transfer size, default to 256 sectors 1065 */ 1066 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1067 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1068 if (ata_ctlp->ac_max_transfer < 1) 1069 ata_ctlp->ac_max_transfer = 1; 1070 if (ata_ctlp->ac_max_transfer > 0x100) 1071 ata_ctlp->ac_max_transfer = 0x100; 1072 1073 /* 1074 * Get the standby timer value 1075 */ 1076 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1077 dip, DDI_PROP_DONTPASS, "standby", -1); 1078 1079 /* 1080 * If this is a /pci/pci-ide instance check to see if 1081 * it's supposed to be attached as an /isa/ata 1082 */ 1083 if (ata_ctlp->ac_pciide) { 1084 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1085 int addr1 = (intptr_t)ioaddr1; 1086 1087 1088 if (addr1 < 0 || addr1 > 0xffff) { 1089 (void) ata_detach(dip, DDI_DETACH); 1090 return (NULL); 1091 } 1092 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1093 addr1); 1094 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1095 DDI_PROP_DONTPASS, prop_buf)) { 1096 (void) ata_detach(dip, DDI_DETACH); 1097 return (NULL); 1098 } 1099 } 1100 1101 /* Init controller specific stuff */ 1102 (void) ata_spec_init_controller(dip); 1103 1104 /* 1105 * initialize GHD 1106 */ 1107 1108 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1109 1110 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1111 atapi_ccballoc, atapi_ccbfree, 1112 ata_pciide_dma_sg_func, ata_hba_start, 1113 ata_hba_complete, ata_intr, 1114 ata_get_status, ata_process_intr, ata_timeout_func, 1115 &ata_timer_conf, NULL)) { 1116 (void) ata_detach(dip, DDI_DETACH); 1117 return (NULL); 1118 } 1119 1120 ata_ctlp->ac_flags |= AC_GHD_INIT; 1121 return (ata_ctlp); 1122} 1123 1124/* destroy a controller */ 1125 1126static void 1127ata_destroy_controller( 1128 dev_info_t *dip) 1129{ 1130 ata_ctl_t *ata_ctlp; 1131 int instance; 1132 1133 ADBG_TRACE(("ata_destroy_controller entered\n")); 1134 1135 instance = ddi_get_instance(dip); 1136 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1137 1138 if (ata_ctlp == NULL) 1139 return; 1140 1141 /* destroy ghd */ 1142 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1143 ghd_unregister(&ata_ctlp->ac_ccc); 1144 1145 /* free the pciide buffer (if any) */ 1146 ata_pciide_free(ata_ctlp); 1147 1148 /* destroy controller struct */ 1149 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1150 ddi_soft_state_free(ata_state, instance); 1151 1152} 1153 1154 1155/* 1156 * 1157 * initialize a drive 1158 * 1159 */ 1160 1161static ata_drv_t * 1162ata_init_drive( 1163 ata_ctl_t *ata_ctlp, 1164 uchar_t targ, 1165 uchar_t lun) 1166{ 1167 static char nec_260[] = "NEC CD-ROM DRIVE"; 1168 ata_drv_t *ata_drvp; 1169 struct ata_id *aidp; 1170 char buf[80]; 1171 int drive_type; 1172 int i; 1173 int valid_version = 0; 1174 1175 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1176 targ, lun)); 1177 1178 /* check if device already exists */ 1179 1180 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1181 1182 if (ata_drvp != NULL) 1183 return (ata_drvp); 1184 1185 /* allocate new device structure */ 1186 1187 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1188 aidp = &ata_drvp->ad_id; 1189 1190 /* 1191 * set up drive struct 1192 */ 1193 ata_drvp->ad_ctlp = ata_ctlp; 1194 ata_drvp->ad_pciide_dma = ATA_DMA_UNINITIALIZED; 1195 ata_drvp->ad_targ = targ; 1196 ata_drvp->ad_drive_bits = 1197 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1198 /* 1199 * Add the LUN for SFF-8070i support 1200 */ 1201 ata_drvp->ad_lun = lun; 1202 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1203 1204 /* 1205 * get drive type, side effect is to collect 1206 * IDENTIFY DRIVE data 1207 */ 1208 1209 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1210 ata_ctlp->ac_iohandle1, 1211 ata_ctlp->ac_ioaddr1, 1212 ata_ctlp->ac_iohandle2, 1213 ata_ctlp->ac_ioaddr2, 1214 aidp); 1215 1216 switch (drive_type) { 1217 case ATA_DEV_NONE: 1218 /* no drive found */ 1219 goto errout; 1220 case ATA_DEV_ATAPI: 1221 ata_drvp->ad_flags |= AD_ATAPI; 1222 break; 1223 case ATA_DEV_DISK: 1224 ata_drvp->ad_flags |= AD_DISK; 1225 break; 1226 } 1227 1228 /* 1229 * swap bytes of all text fields 1230 */ 1231 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1232 swab(aidp->ai_drvser, aidp->ai_drvser, 1233 sizeof (aidp->ai_drvser)); 1234 swab(aidp->ai_fw, aidp->ai_fw, 1235 sizeof (aidp->ai_fw)); 1236 swab(aidp->ai_model, aidp->ai_model, 1237 sizeof (aidp->ai_model)); 1238 } 1239 1240 /* 1241 * Check if this drive has the Single Sector bug 1242 */ 1243 1244 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1245 ata_drvp->ad_flags |= AD_1SECTOR; 1246 else 1247 ata_drvp->ad_flags &= ~AD_1SECTOR; 1248 1249 /* Check if this drive has the "revert to defaults" bug */ 1250 if (!ata_check_revert_to_defaults(ata_drvp)) 1251 ata_drvp->ad_flags |= AD_NORVRT; 1252 1253 /* Dump the drive info */ 1254 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1255 buf[sizeof (aidp->ai_model)-1] = '\0'; 1256 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1257 buf[i] = '\0'; 1258 1259 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1260 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1261 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1262 1263 ATAPRT(("?\tmodel %s\n", buf)); 1264 1265 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1266 for (i = 14; i >= 2; i--) { 1267 if (aidp->ai_majorversion & (1 << i)) { 1268 valid_version = i; 1269 break; 1270 } 1271 } 1272 ATAPRT(( 1273 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1274 valid_version, 1275 aidp->ai_majorversion, 1276 aidp->ai_minorversion)); 1277 } 1278 1279 if (ata_capability_data) { 1280 1281 ATAPRT(("?\t\tstat %x, err %x\n", 1282 ddi_get8(ata_ctlp->ac_iohandle2, 1283 ata_ctlp->ac_altstatus), 1284 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1285 1286 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1287 aidp->ai_config, 1288 aidp->ai_cap)); 1289 1290 /* 1291 * Be aware that ATA-6 and later drives may not provide valid 1292 * geometry information and other obsoleted info. 1293 * Select what is printed based on supported ATA model (skip 1294 * anything below ATA/ATAPI-3) 1295 */ 1296 1297 if (valid_version == 0 || aidp->ai_majorversion < 1298 ATAC_MAJVER_6) { 1299 /* 1300 * Supported version less then ATA-6 1301 */ 1302 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1303 aidp->ai_fixcyls, 1304 aidp->ai_heads, 1305 aidp->ai_sectors)); 1306 } 1307 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1308 aidp->ai_mult1, 1309 aidp->ai_mult2)); 1310 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1311 ATAPRT(( 1312 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1313 aidp->ai_piomode, 1314 aidp->ai_dmamode, 1315 aidp->ai_advpiomode)); 1316 } else { 1317 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1318 aidp->ai_advpiomode)); 1319 } 1320 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1321 aidp->ai_minpio, 1322 aidp->ai_minpioflow)); 1323 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1324 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1325 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1326 aidp->ai_dworddma, 1327 aidp->ai_ultradma)); 1328 } else { 1329 ATAPRT(("?\t\tdwdma 0x%x\n", 1330 aidp->ai_dworddma)); 1331 } 1332 } 1333 1334 if (ATAPIDRV(ata_drvp)) { 1335 if (!atapi_init_drive(ata_drvp)) 1336 goto errout; 1337 } else { 1338 if (!ata_disk_init_drive(ata_drvp)) 1339 goto errout; 1340 } 1341 1342 /* 1343 * store pointer in controller struct 1344 */ 1345 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1346 1347 /* 1348 * lock the drive's current settings in case I have to 1349 * reset the drive due to some sort of error 1350 */ 1351 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 1352 1353 return (ata_drvp); 1354 1355errout: 1356 ata_uninit_drive(ata_drvp); 1357 return (NULL); 1358} 1359 1360/* destroy a drive */ 1361 1362static void 1363ata_uninit_drive( 1364 ata_drv_t *ata_drvp) 1365{ 1366#if 0 1367 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1368#endif 1369 1370 ADBG_TRACE(("ata_uninit_drive entered\n")); 1371 1372#if 0 1373 /* 1374 * DON'T DO THIS. disabling interrupts floats the IRQ line 1375 * which generates spurious interrupts 1376 */ 1377 1378 /* 1379 * Select the correct drive 1380 */ 1381 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1382 ata_drvp->ad_drive_bits); 1383 ata_nsecwait(400); 1384 1385 /* 1386 * Disable interrupts from the drive 1387 */ 1388 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1389 (ATDC_D3 | ATDC_NIEN)); 1390#endif 1391 1392 /* interface specific clean-ups */ 1393 1394 if (ata_drvp->ad_flags & AD_ATAPI) 1395 atapi_uninit_drive(ata_drvp); 1396 else if (ata_drvp->ad_flags & AD_DISK) 1397 ata_disk_uninit_drive(ata_drvp); 1398 1399 /* free drive struct */ 1400 1401 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1402} 1403 1404 1405/* 1406 * ata_drive_type() 1407 * 1408 * The timeout values and exact sequence of checking is critical 1409 * especially for atapi device detection, and should not be changed lightly. 1410 * 1411 */ 1412static int 1413ata_drive_type( 1414 uchar_t drvhd, 1415 ddi_acc_handle_t io_hdl1, 1416 caddr_t ioaddr1, 1417 ddi_acc_handle_t io_hdl2, 1418 caddr_t ioaddr2, 1419 struct ata_id *ata_id_bufp) 1420{ 1421 uchar_t status; 1422 1423 ADBG_TRACE(("ata_drive_type entered\n")); 1424 1425 /* 1426 * select the appropriate drive and LUN 1427 */ 1428 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1429 ata_nsecwait(400); 1430 1431 /* 1432 * make certain the drive is selected, and wait for not busy 1433 */ 1434 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1435 5 * 1000000); 1436 1437 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1438 1439 if (status & ATS_BSY) { 1440 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1441 return (ATA_DEV_NONE); 1442 } 1443 1444 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1445 return (ATA_DEV_DISK); 1446 1447 /* 1448 * No disk, check for atapi unit. 1449 */ 1450 if (!atapi_signature(io_hdl1, ioaddr1)) { 1451#ifndef ATA_DISABLE_ATAPI_1_7 1452 /* 1453 * Check for old (but prevalent) atapi 1.7B 1454 * spec device, the only known example is the 1455 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1456 * compliant). This device has no signature 1457 * and requires conversion from hex to BCD 1458 * for some scsi audio commands. 1459 */ 1460 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1461 return (ATA_DEV_ATAPI); 1462 } 1463#endif 1464 return (ATA_DEV_NONE); 1465 } 1466 1467 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1468 return (ATA_DEV_ATAPI); 1469 } 1470 1471 return (ATA_DEV_NONE); 1472 1473} 1474 1475/* 1476 * nsec-granularity time delay function 1477 */ 1478void 1479ata_nsecwait(clock_t count) 1480{ 1481 extern int tsc_gethrtime_initted; 1482 1483 if (tsc_gethrtime_initted) { 1484 hrtime_t end = gethrtime() + count; 1485 1486 while (gethrtime() < end) { 1487 SMT_PAUSE(); 1488 } 1489 } else { 1490 drv_usecwait(1 + (count / 1000)); 1491 } 1492} 1493 1494 1495/* 1496 * Wait for a register of a controller to achieve a specific state. 1497 * To return normally, all the bits in the first sub-mask must be ON, 1498 * all the bits in the second sub-mask must be OFF. 1499 * If timeout_usec microseconds pass without the controller achieving 1500 * the desired bit configuration, we return TRUE, else FALSE. 1501 */ 1502 1503int ata_usec_delay = 10; 1504 1505int 1506ata_wait( 1507 ddi_acc_handle_t io_hdl, 1508 caddr_t ioaddr, 1509 uchar_t onbits, 1510 uchar_t offbits, 1511 uint_t timeout_usec) 1512{ 1513 ushort_t val; 1514 hrtime_t deadline = gethrtime() + 1515 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1516 1517 1518 do { 1519 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1520 if ((val & onbits) == onbits && (val & offbits) == 0) 1521 return (TRUE); 1522 drv_usecwait(ata_usec_delay); 1523 } while (gethrtime() < deadline); 1524 1525 return (FALSE); 1526} 1527 1528 1529/* 1530 * 1531 * This is a slightly more complicated version that checks 1532 * for error conditions and bails-out rather than looping 1533 * until the timeout expires 1534 */ 1535int 1536ata_wait3( 1537 ddi_acc_handle_t io_hdl, 1538 caddr_t ioaddr, 1539 uchar_t onbits1, 1540 uchar_t offbits1, 1541 uchar_t failure_onbits2, 1542 uchar_t failure_offbits2, 1543 uchar_t failure_onbits3, 1544 uchar_t failure_offbits3, 1545 uint_t timeout_usec) 1546{ 1547 ushort_t val; 1548 hrtime_t deadline = gethrtime() + 1549 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1550 1551 do { 1552 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1553 1554 /* 1555 * check for expected condition 1556 */ 1557 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1558 return (TRUE); 1559 1560 /* 1561 * check for error conditions 1562 */ 1563 if ((val & failure_onbits2) == failure_onbits2 && 1564 (val & failure_offbits2) == 0) { 1565 return (FALSE); 1566 } 1567 1568 if ((val & failure_onbits3) == failure_onbits3 && 1569 (val & failure_offbits3) == 0) { 1570 return (FALSE); 1571 } 1572 1573 drv_usecwait(ata_usec_delay); 1574 } while (gethrtime() < deadline); 1575 1576 return (FALSE); 1577} 1578 1579 1580/* 1581 * 1582 * low level routine for ata_disk_id() and atapi_id() 1583 * 1584 */ 1585 1586int 1587ata_id_common( 1588 uchar_t id_cmd, 1589 int expect_drdy, 1590 ddi_acc_handle_t io_hdl1, 1591 caddr_t ioaddr1, 1592 ddi_acc_handle_t io_hdl2, 1593 caddr_t ioaddr2, 1594 struct ata_id *aidp) 1595{ 1596 uchar_t status; 1597 1598 ADBG_TRACE(("ata_id_common entered\n")); 1599 1600 bzero(aidp, sizeof (struct ata_id)); 1601 1602 /* 1603 * clear the features register 1604 */ 1605 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1606 1607 /* 1608 * Disable interrupts from the device. When the ata 1609 * hardware is sharing its interrupt with another 1610 * device, the shared interrupt might have already been 1611 * unmasked in the interrupt controller and 1612 * triggering ata device interrupts will result in an 1613 * interrupt storm and a hung system. 1614 */ 1615 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1616 1617 /* 1618 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1619 */ 1620 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1621 1622 /* wait for the busy bit to settle */ 1623 ata_nsecwait(400); 1624 1625 /* 1626 * read alternate status and check for conditions which 1627 * may indicate the drive is not present, to prevent getting 1628 * stuck in ata_wait3() below. 1629 */ 1630 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1631 1632 /* 1633 * 0x0, 0x7f, or ATS_DF can happen when no drive is present 1634 */ 1635 if ((status == 0x0) || (status == 0x7f) || 1636 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) { 1637 /* invalid status, can't be an ATA or ATAPI device */ 1638 return (FALSE); 1639 } 1640 1641 /* 1642 * According to the ATA specification, some drives may have 1643 * to read the media to complete this command. We need to 1644 * make sure we give them enough time to respond. 1645 */ 1646 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1647 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1648 1649 /* 1650 * read the status byte and clear the pending interrupt 1651 */ 1652 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS); 1653 1654 /* 1655 * this happens if there's no drive present 1656 */ 1657 if (status == 0xff || status == 0x7f) { 1658 /* invalid status, can't be an ATA or ATAPI device */ 1659 return (FALSE); 1660 } 1661 1662 if (status & ATS_BSY) { 1663 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1664 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1665 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1666 return (FALSE); 1667 } 1668 1669 if (!(status & ATS_DRQ)) { 1670 if (status & (ATS_ERR | ATS_DF)) { 1671 return (FALSE); 1672 } 1673 /* 1674 * Give the drive another second to assert DRQ. Some older 1675 * drives de-assert BSY before asserting DRQ. 1676 */ 1677 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1678 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1679 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1680 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1681 return (FALSE); 1682 } 1683 } 1684 1685 /* 1686 * transfer the data 1687 */ 1688 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1689 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1690 1691 /* wait for the busy bit to settle */ 1692 ata_nsecwait(400); 1693 1694 1695 /* 1696 * Wait for the drive to recognize I've read all the data. 1697 * Some drives have been observed to take as much as 3msec to 1698 * deassert DRQ after reading the data; allow 10 msec just in case. 1699 * 1700 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1701 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1702 * safely ignore the DRDY bit since the ATAPI Packet command 1703 * actually doesn't require it to ever be asserted. 1704 * 1705 */ 1706 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1707 (ATS_BSY | ATS_DRQ), 1000000)) { 1708 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1709 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1710 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1711 return (FALSE); 1712 } 1713 1714 /* 1715 * Check to see if the command aborted. This happens if 1716 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1717 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1718 * (non-PACKET) device. 1719 */ 1720 if (status & (ATS_DF | ATS_ERR)) { 1721 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1722 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1723 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1724 return (FALSE); 1725 } 1726 return (TRUE); 1727} 1728 1729 1730/* 1731 * Low level routine to issue a non-data command and busy wait for 1732 * the completion status. 1733 */ 1734 1735int 1736ata_command( 1737 ata_ctl_t *ata_ctlp, 1738 ata_drv_t *ata_drvp, 1739 int expect_drdy, 1740 int silent, 1741 uint_t busy_wait, 1742 uchar_t cmd, 1743 uchar_t feature, 1744 uchar_t count, 1745 uchar_t sector, 1746 uchar_t head, 1747 uchar_t cyl_low, 1748 uchar_t cyl_hi) 1749{ 1750 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1751 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1752 uchar_t status; 1753 1754 /* select the drive */ 1755 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1756 ata_nsecwait(400); 1757 1758 /* make certain the drive selected */ 1759 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1760 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1761 ATS_BSY, busy_wait)) { 1762 ADBG_ERROR(("ata_command: select failed " 1763 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1764 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1765 expect_drdy, cmd, feature, count, 1766 sector, head, cyl_low, cyl_hi)); 1767 return (FALSE); 1768 } 1769 1770 /* 1771 * set all the regs 1772 */ 1773 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1774 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1775 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1776 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1777 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1778 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1779 1780 /* send the command */ 1781 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1782 1783 /* wait for the busy bit to settle */ 1784 ata_nsecwait(400); 1785 1786 /* wait for not busy */ 1787 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1788 ADBG_ERROR(("ata_command: BSY too long!" 1789 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1790 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1791 expect_drdy, cmd, feature, count, 1792 sector, head, cyl_low, cyl_hi)); 1793 return (FALSE); 1794 } 1795 1796 /* 1797 * wait for DRDY before continuing 1798 */ 1799 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1800 ATS_DRDY, ATS_BSY, /* okay */ 1801 ATS_ERR, ATS_BSY, /* cmd failed */ 1802 ATS_DF, ATS_BSY, /* drive failed */ 1803 busy_wait); 1804 1805 /* read status to clear IRQ, and check for error */ 1806 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1807 1808 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1809 return (TRUE); 1810 1811 if (!silent) { 1812 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1813 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1814 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1815 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1816 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1817 expect_drdy, cmd, feature, count, 1818 sector, head, cyl_low, cyl_hi)); 1819 } 1820 return (FALSE); 1821} 1822 1823 1824 1825/* 1826 * 1827 * Issue a SET FEATURES command 1828 * 1829 */ 1830 1831int 1832ata_set_feature( 1833 ata_ctl_t *ata_ctlp, 1834 ata_drv_t *ata_drvp, 1835 uchar_t feature, 1836 uchar_t value) 1837{ 1838 int rc; 1839 1840 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1841 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1842 /* feature, count, sector, head, cyl_low, cyl_hi */ 1843 1844 if (rc) { 1845 return (TRUE); 1846 } 1847 1848 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1849 return (FALSE); 1850} 1851 1852 1853 1854/* 1855 * 1856 * Issue a FLUSH CACHE command 1857 * 1858 */ 1859 1860static int 1861ata_flush_cache( 1862 ata_ctl_t *ata_ctlp, 1863 ata_drv_t *ata_drvp) 1864{ 1865 /* this command is optional so fail silently */ 1866 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1867 ata_flush_cache_wait, 1868 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1869} 1870 1871/* 1872 * ata_setup_ioaddr() 1873 * 1874 * Map the device registers and return the handles. 1875 * 1876 * If this is a ISA-ATA controller then only two handles are 1877 * initialized and returned. 1878 * 1879 * If this is a PCI-IDE controller than a third handle (for the 1880 * PCI-IDE Bus Mastering registers) is initialized and returned. 1881 * 1882 */ 1883 1884static int 1885ata_setup_ioaddr( 1886 dev_info_t *dip, 1887 ddi_acc_handle_t *handle1p, 1888 caddr_t *addr1p, 1889 ddi_acc_handle_t *handle2p, 1890 caddr_t *addr2p, 1891 ddi_acc_handle_t *bm_hdlp, 1892 caddr_t *bm_addrp) 1893{ 1894 ddi_device_acc_attr_t dev_attr; 1895 int rnumber; 1896 int rc; 1897 off_t regsize; 1898 1899 /* 1900 * Make certain the controller is enabled and its regs are map-able 1901 * 1902 */ 1903 rc = ddi_dev_regsize(dip, 0, ®size); 1904 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1905 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1906 rc, (long long)regsize)); 1907 return (FALSE); 1908 } 1909 1910 rc = ddi_dev_regsize(dip, 1, ®size); 1911 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1912 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1913 rc, (long long)regsize)); 1914 return (FALSE); 1915 } 1916 1917 /* 1918 * setup the device attribute structure for little-endian, 1919 * strict ordering access. 1920 */ 1921 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1922 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1923 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1924 1925 *handle1p = NULL; 1926 *handle2p = NULL; 1927 *bm_hdlp = NULL; 1928 1929 /* 1930 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1931 */ 1932 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1933 /* it's PNP-ISA, skip over the extra reg tuple */ 1934 rnumber = 1; 1935 goto not_pciide; 1936 } 1937 1938 /* else, it's ISA or PCI-IDE, check further */ 1939 rnumber = 0; 1940 1941 if (!ata_is_pci(dip)) { 1942 /* 1943 * If it's not a PCI-IDE, there are only two reg tuples 1944 * and the first one contains the I/O base (170 or 1f0) 1945 * rather than the controller instance number. 1946 */ 1947 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1948 goto not_pciide; 1949 } 1950 1951 1952 /* 1953 * Map the correct half of the PCI-IDE Bus Master registers. 1954 * There's a single BAR that maps these registers for both 1955 * controller's in a dual-controller chip and it's upto my 1956 * parent nexus, pciide, to adjust which (based on my instance 1957 * number) half this call maps. 1958 */ 1959 rc = ddi_dev_regsize(dip, 2, ®size); 1960 if (rc != DDI_SUCCESS || regsize < 8) { 1961 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1962 rc, (long long)regsize)); 1963 goto not_pciide; 1964 } 1965 1966 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1967 1968 if (rc != DDI_SUCCESS) { 1969 /* map failed, try to use in non-pci-ide mode */ 1970 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1971 rc)); 1972 *bm_hdlp = NULL; 1973 } 1974 1975not_pciide: 1976 /* 1977 * map the lower command block registers 1978 */ 1979 1980 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1981 handle1p); 1982 1983 if (rc != DDI_SUCCESS) { 1984 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1985 goto out1; 1986 } 1987 1988 /* 1989 * If the controller is being used in compatibility mode 1990 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1991 * will specify zeros for the I/O ports for the PCI 1992 * instance. 1993 */ 1994 if (*addr1p == 0) { 1995 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 1996 goto out2; 1997 } 1998 1999 /* 2000 * map the upper control block registers 2001 */ 2002 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 2003 handle2p); 2004 if (rc == DDI_SUCCESS) 2005 return (TRUE); 2006 2007 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 2008 2009out2: 2010 if (*handle1p != NULL) { 2011 ddi_regs_map_free(handle1p); 2012 *handle1p = NULL; 2013 } 2014 2015out1: 2016 if (*bm_hdlp != NULL) { 2017 ddi_regs_map_free(bm_hdlp); 2018 *bm_hdlp = NULL; 2019 } 2020 return (FALSE); 2021 2022} 2023 2024/* 2025 * 2026 * Currently, the only supported controllers are ones which 2027 * support the SFF-8038 Bus Mastering spec. 2028 * 2029 * Check the parent node's IEEE 1275 class-code property to 2030 * determine if it's an PCI-IDE instance which supports SFF-8038 2031 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 2032 * that doesn't do Bus Mastering. In that case, my interrupt handler 2033 * only uses the interrupt latch bit in PCI-IDE status register. 2034 * The assumption is that the programming interface byte of the 2035 * class-code property reflects the bus master DMA capability of 2036 * the controller. 2037 * 2038 * Whether the drive support supports the DMA option still needs 2039 * to be checked later. Each individual request also has to be 2040 * checked for alignment and size to decide whether to use the 2041 * DMA transfer mode. 2042 */ 2043 2044static void 2045ata_init_pciide( 2046 dev_info_t *dip, 2047 ata_ctl_t *ata_ctlp) 2048{ 2049 uint_t class_code; 2050 uchar_t status; 2051 2052 ata_cntrl_DMA_sel_msg = NULL; 2053 2054 if (ata_ctlp->ac_bmhandle == NULL) { 2055 ata_ctlp->ac_pciide = FALSE; 2056 ata_ctlp->ac_pciide_bm = FALSE; 2057 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2058 return; 2059 } 2060 2061 /* 2062 * check if it's a known bogus PCI-IDE chip 2063 */ 2064 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2065 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2066 ata_ctlp->ac_pciide = FALSE; 2067 ata_ctlp->ac_pciide_bm = FALSE; 2068 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2069 return; 2070 } 2071 ata_ctlp->ac_pciide = TRUE; 2072 2073 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2074 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2075 } 2076 2077 /* 2078 * check for a PCI-IDE chip with a broken DMA engine 2079 */ 2080 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2081 ata_ctlp->ac_pciide_bm = FALSE; 2082 ata_cntrl_DMA_sel_msg = 2083 "cntrl blacklisted/DMA engine broken"; 2084 return; 2085 } 2086 2087 /* 2088 * Check the Programming Interface register to determine 2089 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2090 * devices don't support Bus Mastering or DMA. 2091 * Since we are dealing with pre-qualified pci-ide controller, 2092 * check programming interface byte only. 2093 */ 2094 2095 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2096 DDI_PROP_DONTPASS, "class-code", 0); 2097 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2098 ata_ctlp->ac_pciide_bm = FALSE; 2099 ata_cntrl_DMA_sel_msg = 2100 "cntrl not Bus Master DMA capable"; 2101 return; 2102 } 2103 2104 /* 2105 * Avoid doing DMA on "simplex" chips which share hardware 2106 * between channels 2107 */ 2108 status = ddi_get8(ata_ctlp->ac_bmhandle, 2109 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2110 /* 2111 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2112 * In such a mode, the simplex bit is asserted, but in fact testing 2113 * on such a motherboard has shown that the devices are not simplex 2114 * -- DMA can be used on both channels concurrently with no special 2115 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2116 * flag set to indicate that the value of the simplex bit can be 2117 * ignored. 2118 */ 2119 2120 if (status & PCIIDE_BMISX_SIMPLEX) { 2121 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2122 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2123 2124 } else { 2125 2126 int simplex_dma_channel, *rp, proplen, channel; 2127 int dma_on = FALSE; 2128 2129 /* 2130 * By default,use DMA on channel 0 and PIO on channel 2131 * 1. This can be switched by setting 2132 * ata-simplex-dma-channel to: 2133 * 0 DMA on channel 0 (default without this 2134 * property) 2135 * 1 DMA on channel 1 2136 * any other value: DMA off on both channels. 2137 */ 2138 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2139 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2140 2141 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2142 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2143 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2144 2145 channel = *rp; 2146 ddi_prop_free(rp); 2147 2148 if (simplex_dma_channel == channel) { 2149 cmn_err(CE_CONT, "?ata: simplex " 2150 "controller. DMA on channel" 2151 " %d PIO on channel %d", 2152 channel, channel ? 0:1); 2153 dma_on = TRUE; 2154 } else { 2155 ata_cntrl_DMA_sel_msg = 2156 "simplex controller"; 2157 } 2158 } 2159 2160 if (dma_on == FALSE) { 2161 ata_ctlp->ac_pciide_bm = FALSE; 2162 2163 return; 2164 } 2165 } 2166 } 2167 2168 /* 2169 * It's a compatible PCI-IDE Bus Mastering controller, 2170 * allocate and map the DMA Scatter/Gather list (PRDE table). 2171 */ 2172 if (ata_pciide_alloc(dip, ata_ctlp)) 2173 ata_ctlp->ac_pciide_bm = TRUE; 2174 else { 2175 ata_ctlp->ac_pciide_bm = FALSE; 2176 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2177 } 2178} 2179 2180/* 2181 * 2182 * Determine whether to enable DMA support for this drive. 2183 * The controller and the drive both have to support DMA. 2184 * The controller's capabilities were already checked in 2185 * ata_init_pciide(), now just check the drive's capabilities. 2186 * 2187 */ 2188 2189static int 2190ata_init_drive_pcidma( 2191 ata_ctl_t *ata_ctlp, 2192 ata_drv_t *ata_drvp, 2193 dev_info_t *tdip) 2194{ 2195 boolean_t dma; 2196 boolean_t cd_dma; 2197 boolean_t disk_dma; 2198 boolean_t atapi_dma; 2199 int ata_options; 2200 2201 ata_dev_DMA_sel_msg = NULL; 2202 2203 if (ata_ctlp->ac_pciide_bm != TRUE) { 2204 ata_dev_DMA_sel_msg = 2205 "controller is not Bus Master capable"; 2206 2207 return (ATA_DMA_OFF); 2208 } 2209 2210 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2211 0, "ata-options", 0); 2212 2213 if (!(ata_options & ATA_OPTIONS_DMA)) { 2214 /* 2215 * Either the ata-options property was not found or 2216 * DMA is not enabled by this property 2217 */ 2218 ata_dev_DMA_sel_msg = 2219 "disabled by \"ata-options\" property"; 2220 2221 return (ATA_DMA_OFF); 2222 } 2223 2224 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2225 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2226 2227 return (ATA_DMA_OFF); 2228 } 2229 2230 /* 2231 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2232 * optional on ATA-2 (or older) drives. 2233 * 2234 * On ATA-2 drives the ai_majorversion word will probably 2235 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2236 * the capabilities word instead. The order of these tests 2237 * is important since an ATA-3 drive doesn't have to set 2238 * the DMA bit in the capabilities word. 2239 * 2240 */ 2241 2242 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2243 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2244 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2245 ata_dev_DMA_sel_msg = "device not DMA capable"; 2246 2247 return (ATA_DMA_OFF); 2248 } 2249 2250 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2251 0, "ata-dma-enabled", TRUE); 2252 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2253 0, "ata-disk-dma-enabled", TRUE); 2254 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2255 0, "atapi-cd-dma-enabled", FALSE); 2256 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2257 0, "atapi-other-dma-enabled", TRUE); 2258 2259 if (dma == FALSE) { 2260 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2261 "DMA disabled by \"ata-dma-enabled\" property"); 2262 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2263 2264 return (ATA_DMA_OFF); 2265 } 2266 2267 if (IS_CDROM(ata_drvp) == TRUE) { 2268 if (cd_dma == FALSE) { 2269 ata_dev_DMA_sel_msg = 2270 "disabled. Control with \"atapi-cd-dma-enabled\"" 2271 " property"; 2272 2273 return (ATA_DMA_OFF); 2274 } 2275 2276 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2277 if (disk_dma == FALSE) { 2278 ata_dev_DMA_sel_msg = 2279 "disabled by \"ata-disk-dma-enabled\" property"; 2280 2281 return (ATA_DMA_OFF); 2282 } 2283 2284 } else if (atapi_dma == FALSE) { 2285 ata_dev_DMA_sel_msg = 2286 "disabled by \"atapi-other-dma-enabled\" property"; 2287 2288 return (ATA_DMA_OFF); 2289 } 2290 2291 return (ATA_DMA_ON); 2292} 2293 2294 2295 2296/* 2297 * this compare routine squeezes out extra blanks and 2298 * returns TRUE if p1 matches the leftmost substring of p2 2299 */ 2300 2301static int 2302ata_strncmp( 2303 char *p1, 2304 char *p2, 2305 int cnt) 2306{ 2307 2308 for (;;) { 2309 /* 2310 * skip over any extra blanks in both strings 2311 */ 2312 while (*p1 != '\0' && *p1 == ' ') 2313 p1++; 2314 2315 while (cnt != 0 && *p2 == ' ') { 2316 p2++; 2317 cnt--; 2318 } 2319 2320 /* 2321 * compare the two strings 2322 */ 2323 2324 if (cnt == 0 || *p1 != *p2) 2325 break; 2326 2327 while (cnt > 0 && *p1 == *p2) { 2328 p1++; 2329 p2++; 2330 cnt--; 2331 } 2332 2333 } 2334 2335 /* return TRUE if both strings ended at same point */ 2336 return ((*p1 == '\0') ? TRUE : FALSE); 2337} 2338 2339/* 2340 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2341 * on the target's dev_info node. Currently, the sd target driver 2342 * is the only driver which refers to this property. 2343 * 2344 * If the flag ata_id_debug is set also create the 2345 * the "ata" or "atapi" property on the target's dev_info node 2346 * 2347 */ 2348 2349int 2350ata_prop_create( 2351 dev_info_t *tgt_dip, 2352 ata_drv_t *ata_drvp, 2353 char *name) 2354{ 2355 int rc; 2356 2357 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2358 2359 if (strcmp("atapi", name) == 0) { 2360 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2361 "variant", name); 2362 if (rc != DDI_PROP_SUCCESS) 2363 return (FALSE); 2364 } 2365 2366 if (!ata_id_debug) 2367 return (TRUE); 2368 2369 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2370 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2371 if (rc != DDI_PROP_SUCCESS) { 2372 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2373 } 2374 return (TRUE); 2375} 2376 2377 2378/* *********************************************************************** */ 2379/* *********************************************************************** */ 2380/* *********************************************************************** */ 2381 2382/* 2383 * This state machine doesn't implement the ATAPI Optional Overlap 2384 * feature. You need that feature to efficiently support ATAPI 2385 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2386 * for an example of how to add the necessary additional NextActions 2387 * and NextStates to this FSM and the atapi_fsm, in order to support 2388 * the Overlap Feature. 2389 */ 2390 2391 2392uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2393/* --------------------- next action --------------------- | - current - */ 2394/* start0 --- start1 ---- intr ------ fini --- reset --- */ 2395{ AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2396{ AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2397{ AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2398}; 2399 2400uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2401 2402/* --------------------- next state --------------------- | - current - */ 2403/* start0 --- start1 ---- intr ------ fini --- reset --- */ 2404{ AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2405{ AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2406{ AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2407}; 2408 2409 2410static int 2411ata_ctlr_fsm( 2412 uchar_t fsm_func, 2413 ata_ctl_t *ata_ctlp, 2414 ata_drv_t *ata_drvp, 2415 ata_pkt_t *ata_pktp, 2416 int *DoneFlgp) 2417{ 2418 uchar_t action; 2419 uchar_t current_state; 2420 uchar_t next_state; 2421 int rc; 2422 2423 current_state = ata_ctlp->ac_state; 2424 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2425 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2426 2427 /* 2428 * Set the controller's new state 2429 */ 2430 ata_ctlp->ac_state = next_state; 2431 switch (action) { 2432 2433 case AC_BUSY: 2434 return (ATA_FSM_RC_BUSY); 2435 2436 case AC_NADA: 2437 return (ATA_FSM_RC_OKAY); 2438 2439 case AC_START: 2440 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2441 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2442 2443 ata_ctlp->ac_active_pktp = ata_pktp; 2444 ata_ctlp->ac_active_drvp = ata_drvp; 2445 2446 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2447 2448 if (rc == ATA_FSM_RC_BUSY) { 2449 /* the request didn't start, GHD will requeue it */ 2450 ata_ctlp->ac_state = AS_IDLE; 2451 ata_ctlp->ac_active_pktp = NULL; 2452 ata_ctlp->ac_active_drvp = NULL; 2453 } 2454 return (rc); 2455 2456 case AC_INTR: 2457 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2458 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2459 2460 ata_drvp = ata_ctlp->ac_active_drvp; 2461 ata_pktp = ata_ctlp->ac_active_pktp; 2462 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2463 2464 case AC_RESET_A: /* Reset, controller active */ 2465 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2466 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2467 2468 /* clean up the active request */ 2469 ata_pktp = ata_ctlp->ac_active_pktp; 2470 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2471 2472 /* halt the DMA engine */ 2473 if (ata_pktp->ap_pciide_dma) { 2474 ata_pciide_dma_stop(ata_ctlp); 2475 (void) ata_pciide_status_clear(ata_ctlp); 2476 } 2477 2478 /* Do a Software Reset to unwedge the bus */ 2479 if (!ata_software_reset(ata_ctlp)) { 2480 return (ATA_FSM_RC_BUSY); 2481 } 2482 2483 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2484 atapi_fsm_reset(ata_ctlp); 2485 return (ATA_FSM_RC_FINI); 2486 2487 case AC_RESET_I: /* Reset, controller idle */ 2488 /* Do a Software Reset to unwedge the bus */ 2489 if (!ata_software_reset(ata_ctlp)) { 2490 return (ATA_FSM_RC_BUSY); 2491 } 2492 2493 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2494 atapi_fsm_reset(ata_ctlp); 2495 return (ATA_FSM_RC_OKAY); 2496 2497 case AC_FINI: 2498 break; 2499 } 2500 2501 /* 2502 * AC_FINI, check ARQ needs to be started or finished 2503 */ 2504 2505 ASSERT(action == AC_FINI); 2506 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2507 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2508 2509 /* 2510 * The active request is done now. 2511 * Disconnect the request from the controller and 2512 * add it to the done queue. 2513 */ 2514 ata_drvp = ata_ctlp->ac_active_drvp; 2515 ata_pktp = ata_ctlp->ac_active_pktp; 2516 2517 /* 2518 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2519 */ 2520 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2521 ata_pkt_t *arq_pktp; 2522 2523 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2524 2525 arq_pktp = ata_pktp; 2526 ata_pktp = ata_ctlp->ac_fault_pktp; 2527 ata_ctlp->ac_fault_pktp = NULL; 2528 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2529 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2530 else 2531 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2532 goto all_done; 2533 } 2534 2535 2536#define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2537 2538 /* 2539 * Start ARQ pkt if necessary 2540 */ 2541 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2542 (ata_pktp->ap_status & ATS_ERR)) { 2543 2544 /* set controller state back to active */ 2545 ata_ctlp->ac_state = current_state; 2546 2547 /* try to start the ARQ pkt */ 2548 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2549 2550 if (rc == ATA_FSM_RC_BUSY) { 2551 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2552 /* let the target driver handle the problem */ 2553 ata_ctlp->ac_state = AS_IDLE; 2554 ata_ctlp->ac_active_pktp = NULL; 2555 ata_ctlp->ac_active_drvp = NULL; 2556 ata_ctlp->ac_fault_pktp = NULL; 2557 goto all_done; 2558 } 2559 2560 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2561 return (rc); 2562 } 2563 2564 /* 2565 * Normal completion, no error status, and not an ARQ pkt, 2566 * just fall through. 2567 */ 2568 2569all_done: 2570 2571 /* 2572 * wrap everything up and tie a ribbon around it 2573 */ 2574 ata_ctlp->ac_active_pktp = NULL; 2575 ata_ctlp->ac_active_drvp = NULL; 2576 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2577 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2578 if (DoneFlgp) 2579 *DoneFlgp = TRUE; 2580 } 2581 2582 return (ATA_FSM_RC_OKAY); 2583} 2584 2585 2586static int 2587ata_start_arq( 2588 ata_ctl_t *ata_ctlp, 2589 ata_drv_t *ata_drvp, 2590 ata_pkt_t *ata_pktp) 2591{ 2592 ata_pkt_t *arq_pktp; 2593 int bytes; 2594 uint_t senselen; 2595 2596 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2597 2598 /* 2599 * Determine just the size of the Request Sense Data buffer within 2600 * the scsi_arq_status structure. 2601 */ 2602#define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2603 - sizeof (struct scsi_extended_sense)) 2604 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2605 ASSERT(senselen > 0); 2606 2607 2608 /* save ptr to original pkt */ 2609 ata_ctlp->ac_fault_pktp = ata_pktp; 2610 2611 /* switch the controller's active pkt to the ARQ pkt */ 2612 arq_pktp = ata_ctlp->ac_arq_pktp; 2613 ata_ctlp->ac_active_pktp = arq_pktp; 2614 2615 /* finish initializing the ARQ CDB */ 2616 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2617 ata_ctlp->ac_arq_cdb[4] = senselen; 2618 2619 /* finish initializing the ARQ pkt */ 2620 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2621 2622 arq_pktp->ap_resid = senselen; 2623 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2624 arq_pktp->ap_cdb_pad = 2625 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2626 2627 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2628 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2629 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2630 2631 /* 2632 * This packet is shared by all drives on this controller 2633 * therefore we need to init the drive number on every ARQ. 2634 */ 2635 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2636 2637 /* start it up */ 2638 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2639} 2640 2641/* 2642 * 2643 * reset the bus 2644 * 2645 */ 2646 2647static int 2648ata_reset_bus( 2649 ata_ctl_t *ata_ctlp) 2650{ 2651 int watchdog; 2652 uchar_t drive; 2653 int rc = FALSE; 2654 uchar_t fsm_func; 2655 int DoneFlg = FALSE; 2656 2657 /* 2658 * Do a Software Reset to unwedge the bus, and send 2659 * ATAPI DEVICE RESET to each ATAPI drive. 2660 */ 2661 fsm_func = ATA_FSM_RESET; 2662 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2663 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2664 &DoneFlg)) { 2665 case ATA_FSM_RC_OKAY: 2666 rc = TRUE; 2667 goto fsm_done; 2668 2669 case ATA_FSM_RC_BUSY: 2670 return (FALSE); 2671 2672 case ATA_FSM_RC_INTR: 2673 fsm_func = ATA_FSM_INTR; 2674 rc = TRUE; 2675 continue; 2676 2677 case ATA_FSM_RC_FINI: 2678 fsm_func = ATA_FSM_FINI; 2679 rc = TRUE; 2680 continue; 2681 } 2682 } 2683 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2684 2685fsm_done: 2686 2687 /* 2688 * Reinitialize the ATA drives 2689 */ 2690 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2691 ata_drv_t *ata_drvp; 2692 2693 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2694 continue; 2695 2696 if (ATAPIDRV(ata_drvp)) 2697 continue; 2698 2699 /* 2700 * Reprogram the Read/Write Multiple block factor 2701 * and current geometry into the drive. 2702 */ 2703 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2704 rc = FALSE; 2705 } 2706 2707 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2708 /* has been already called. In this case ignore any errors and */ 2709 /* return TRUE to the caller, otherwise return the value of rc */ 2710 /* to the caller */ 2711 if (DoneFlg) 2712 return (TRUE); 2713 else 2714 return (rc); 2715} 2716 2717 2718/* 2719 * 2720 * Low level routine to toggle the Software Reset bit 2721 * 2722 */ 2723 2724static int 2725ata_software_reset( 2726 ata_ctl_t *ata_ctlp) 2727{ 2728 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2729 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2730 hrtime_t deadline; 2731 uint_t usecs_left; 2732 2733 ADBG_TRACE(("ata_reset_bus entered\n")); 2734 2735 /* disable interrupts and turn the software reset bit on */ 2736 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2737 2738 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2739 drv_usecwait(30000); 2740 2741 /* turn the software reset bit back off */ 2742 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2743 2744 /* 2745 * Wait for the controller to assert BUSY status. 2746 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2747 * spec says 400 nsecs, (and 2 msecs if device 2748 * was in sleep mode; but we don't put drives to sleep 2749 * so it probably doesn't matter). 2750 */ 2751 drv_usecwait(300000); 2752 2753 /* 2754 * If drive 0 exists the test for completion is simple 2755 */ 2756 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2757 2758 if (CTL2DRV(ata_ctlp, 0, 0)) { 2759 goto wait_for_not_busy; 2760 } 2761 2762 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2763 2764 /* 2765 * This must be a single device configuration, with drive 1 2766 * only. This complicates the test for completion because 2767 * issuing the software reset just caused drive 1 to 2768 * deselect. With drive 1 deselected, if I just read the 2769 * status register to test the BSY bit I get garbage, but 2770 * I can't re-select drive 1 until I'm certain the BSY bit 2771 * is de-asserted. Catch-22. 2772 * 2773 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2774 * this situation like this: 2775 */ 2776 2777 /* give up if the drive doesn't settle within 31 seconds */ 2778 while (gethrtime() < deadline) { 2779 /* 2780 * delay 10msec each time around the loop 2781 */ 2782 drv_usecwait(10000); 2783 2784 /* 2785 * try to select drive 1 2786 */ 2787 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2788 2789 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2790 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2791 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2792 continue; 2793 2794 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2795 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2796 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2797 continue; 2798 2799 goto wait_for_not_busy; 2800 } 2801 return (FALSE); 2802 2803wait_for_not_busy: 2804 2805 /* 2806 * Now wait up to 31 seconds for BUSY to clear. 2807 */ 2808 usecs_left = (deadline - gethrtime()) / 1000; 2809 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2810 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2811 2812 return (TRUE); 2813} 2814 2815/* 2816 * 2817 * DDI interrupt handler 2818 * 2819 */ 2820 2821static uint_t 2822ata_intr( 2823 caddr_t arg) 2824{ 2825 ata_ctl_t *ata_ctlp; 2826 int one_shot = 1; 2827 2828 ata_ctlp = (ata_ctl_t *)arg; 2829 2830 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2831} 2832 2833 2834/* 2835 * 2836 * GHD ccc_get_status callback 2837 * 2838 */ 2839 2840static int 2841ata_get_status( 2842 void *hba_handle, 2843 void *intr_status) 2844{ 2845 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2846 uchar_t status; 2847 2848 ADBG_TRACE(("ata_get_status entered\n")); 2849 2850 /* 2851 * ignore interrupts before ata_attach completes 2852 */ 2853 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2854 return (FALSE); 2855 2856 /* 2857 * can't be interrupt pending if nothing active 2858 */ 2859 switch (ata_ctlp->ac_state) { 2860 case AS_IDLE: 2861 return (FALSE); 2862 case AS_ACTIVE0: 2863 case AS_ACTIVE1: 2864 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2865 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2866 break; 2867 } 2868 2869 /* 2870 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2871 * interrupt status latch. But don't clear it yet. 2872 * 2873 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2874 * CMD chips with device id 0x646. Since the interrupt bit on 2875 * Bus master IDE register is not usable when in PIO mode, 2876 * this chip is treated as a legacy device for interrupt 2877 * indication. The following code for CMD 2878 * chips may need to be revisited when we enable support for dma. 2879 * 2880 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2881 * checked only if there was DMA used or BM intr is useable on PIO, 2882 * else treat it as before - as legacy device. 2883 */ 2884 2885 if ((ata_ctlp->ac_pciide) && 2886 ((ata_ctlp->ac_pciide_bm != FALSE) && 2887 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2888 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2889 2890 if (!ata_pciide_status_pending(ata_ctlp)) 2891 return (FALSE); 2892 } else { 2893 /* 2894 * Interrupts from legacy ATA/IDE controllers are 2895 * edge-triggered but the dumb legacy ATA/IDE controllers 2896 * and drives don't have an interrupt status bit. 2897 * 2898 * Use a one_shot variable to make sure we only return 2899 * one status per interrupt. 2900 */ 2901 if (intr_status != NULL) { 2902 int *one_shot = (int *)intr_status; 2903 2904 if (*one_shot == 1) 2905 *one_shot = 0; 2906 else 2907 return (FALSE); 2908 } 2909 } 2910 2911 /* check if device is still busy */ 2912 2913 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2914 if (status & ATS_BSY) 2915 return (FALSE); 2916 return (TRUE); 2917} 2918 2919 2920/* 2921 * 2922 * get the current status and clear the IRQ 2923 * 2924 */ 2925 2926int 2927ata_get_status_clear_intr( 2928 ata_ctl_t *ata_ctlp, 2929 ata_pkt_t *ata_pktp) 2930{ 2931 uchar_t status; 2932 2933 /* 2934 * Here's where we clear the PCI-IDE interrupt latch. If this 2935 * request used DMA mode then we also have to check and clear 2936 * the DMA error latch at the same time. 2937 */ 2938 2939 if (ata_pktp->ap_pciide_dma) { 2940 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2941 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2942 } else if ((ata_ctlp->ac_pciide) && 2943 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2944 /* 2945 * Some requests don't use DMA mode and therefore won't 2946 * set the DMA error latch, but we still have to clear 2947 * the interrupt latch. 2948 * Controllers with broken BM intr in PIO mode do not go 2949 * through this path. 2950 */ 2951 (void) ata_pciide_status_clear(ata_ctlp); 2952 } 2953 2954 /* 2955 * this clears the drive's interrupt 2956 */ 2957 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2958 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2959 return (status); 2960} 2961 2962 2963 2964/* 2965 * 2966 * GHD interrupt handler 2967 * 2968 */ 2969 2970/* ARGSUSED */ 2971static void 2972ata_process_intr( 2973 void *hba_handle, 2974 void *intr_status) 2975{ 2976 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2977 int watchdog; 2978 uchar_t fsm_func; 2979 int rc; 2980 2981 ADBG_TRACE(("ata_process_intr entered\n")); 2982 2983 /* 2984 * process the ATA or ATAPI interrupt 2985 */ 2986 2987 fsm_func = ATA_FSM_INTR; 2988 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 2989 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 2990 2991 switch (rc) { 2992 case ATA_FSM_RC_OKAY: 2993 return; 2994 2995 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 2996 return; 2997 2998 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 2999 fsm_func = ATA_FSM_INTR; 3000 break; 3001 3002 case ATA_FSM_RC_FINI: /* move a request to done Q */ 3003 fsm_func = ATA_FSM_FINI; 3004 break; 3005 } 3006 } 3007 ADBG_WARN(("ata_process_intr: watchdog\n")); 3008} 3009 3010 3011 3012/* 3013 * 3014 * GHD ccc_hba_start callback 3015 * 3016 */ 3017 3018static int 3019ata_hba_start( 3020 void *hba_handle, 3021 gcmd_t *gcmdp) 3022{ 3023 ata_ctl_t *ata_ctlp; 3024 ata_drv_t *ata_drvp; 3025 ata_pkt_t *ata_pktp; 3026 uchar_t fsm_func; 3027 int request_started; 3028 int watchdog; 3029 3030 ADBG_TRACE(("ata_hba_start entered\n")); 3031 3032 ata_ctlp = (ata_ctl_t *)hba_handle; 3033 3034 if (ata_ctlp->ac_active_drvp != NULL) { 3035 ADBG_WARN(("ata_hba_start drvp not null\n")); 3036 return (FALSE); 3037 } 3038 if (ata_ctlp->ac_active_pktp != NULL) { 3039 ADBG_WARN(("ata_hba_start pktp not null\n")); 3040 return (FALSE); 3041 } 3042 3043 ata_pktp = GCMD2APKT(gcmdp); 3044 ata_drvp = GCMD2DRV(gcmdp); 3045 3046 /* 3047 * which drive? 3048 */ 3049 if (ata_drvp->ad_targ == 0) 3050 fsm_func = ATA_FSM_START0; 3051 else 3052 fsm_func = ATA_FSM_START1; 3053 3054 /* 3055 * start the request 3056 */ 3057 request_started = FALSE; 3058 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3059 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3060 NULL)) { 3061 case ATA_FSM_RC_OKAY: 3062 request_started = TRUE; 3063 goto fsm_done; 3064 3065 case ATA_FSM_RC_BUSY: 3066 /* if first time, tell GHD to requeue the request */ 3067 goto fsm_done; 3068 3069 case ATA_FSM_RC_INTR: 3070 /* 3071 * The start function polled for the next 3072 * bus phase, now fake an interrupt to process 3073 * the next action. 3074 */ 3075 request_started = TRUE; 3076 fsm_func = ATA_FSM_INTR; 3077 ata_drvp = NULL; 3078 ata_pktp = NULL; 3079 break; 3080 3081 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3082 request_started = TRUE; 3083 fsm_func = ATA_FSM_FINI; 3084 ata_drvp = NULL; 3085 ata_pktp = NULL; 3086 break; 3087 } 3088 } 3089 ADBG_WARN(("ata_hba_start: watchdog\n")); 3090 3091fsm_done: 3092 return (request_started); 3093 3094} 3095 3096static int 3097ata_check_pciide_blacklist( 3098 dev_info_t *dip, 3099 uint_t flags) 3100{ 3101 ushort_t vendorid; 3102 ushort_t deviceid; 3103 pcibl_t *blp; 3104 int *propp; 3105 uint_t count; 3106 int rc; 3107 3108 3109 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3110 DDI_PROP_DONTPASS, "vendor-id", 0); 3111 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3112 DDI_PROP_DONTPASS, "device-id", 0); 3113 3114 /* 3115 * first check for a match in the "pci-ide-blacklist" property 3116 */ 3117 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3118 "pci-ide-blacklist", &propp, &count); 3119 3120 if (rc == DDI_PROP_SUCCESS) { 3121 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3122 blp = (pcibl_t *)propp; 3123 while (count--) { 3124 /* check for matching ID */ 3125 if ((vendorid & blp->b_vmask) 3126 != (blp->b_vendorid & blp->b_vmask)) { 3127 blp++; 3128 continue; 3129 } 3130 if ((deviceid & blp->b_dmask) 3131 != (blp->b_deviceid & blp->b_dmask)) { 3132 blp++; 3133 continue; 3134 } 3135 3136 /* got a match */ 3137 if (blp->b_flags & flags) { 3138 ddi_prop_free(propp); 3139 return (TRUE); 3140 } else { 3141 ddi_prop_free(propp); 3142 return (FALSE); 3143 } 3144 } 3145 ddi_prop_free(propp); 3146 } 3147 3148 /* 3149 * then check the built-in blacklist 3150 */ 3151 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3152 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3153 continue; 3154 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3155 continue; 3156 if (!(blp->b_flags & flags)) 3157 continue; 3158 return (TRUE); 3159 } 3160 return (FALSE); 3161} 3162 3163int 3164ata_check_drive_blacklist( 3165 struct ata_id *aidp, 3166 uint_t flags) 3167{ 3168 atabl_t *blp; 3169 3170 for (blp = ata_drive_blacklist; blp->b_model; blp++) { 3171 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3172 sizeof (aidp->ai_model))) 3173 continue; 3174 if (blp->b_flags & flags) 3175 return (TRUE); 3176 return (FALSE); 3177 } 3178 return (FALSE); 3179} 3180 3181/* 3182 * Queue a request to perform some sort of internally 3183 * generated command. When this request packet reaches 3184 * the front of the queue (*func)() is invoked. 3185 * 3186 */ 3187 3188int 3189ata_queue_cmd( 3190 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3191 void *arg, 3192 ata_ctl_t *ata_ctlp, 3193 ata_drv_t *ata_drvp, 3194 gtgt_t *gtgtp) 3195{ 3196 ata_pkt_t *ata_pktp; 3197 gcmd_t *gcmdp; 3198 int rc; 3199 3200 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3201 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3202 return (FALSE); 3203 } 3204 3205 3206 /* set the back ptr from the ata_pkt to the gcmd_t */ 3207 ata_pktp = GCMD2APKT(gcmdp); 3208 ata_pktp->ap_gcmdp = gcmdp; 3209 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3210 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3211 3212 /* 3213 * over-ride the default start function 3214 */ 3215 ata_pktp = GCMD2APKT(gcmdp); 3216 ata_pktp->ap_start = func; 3217 ata_pktp->ap_complete = NULL; 3218 ata_pktp->ap_v_addr = (caddr_t)arg; 3219 3220 /* 3221 * add it to the queue, when it gets to the front the 3222 * ap_start function is called. 3223 */ 3224 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3225 0, TRUE, NULL); 3226 3227 if (rc != TRAN_ACCEPT) { 3228 /* this should never, ever happen */ 3229 return (FALSE); 3230 } 3231 3232 if (ata_pktp->ap_flags & AP_ERROR) 3233 return (FALSE); 3234 return (TRUE); 3235} 3236 3237/* 3238 * Check if this drive has the "revert to defaults" bug 3239 * PSARC 2001/500 and 2001/xxx - check for the properties 3240 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3241 * examining the blacklist. 3242 * <diskmodel> is made from the model number reported by Identify Drive 3243 * with uppercase letters converted to lowercase and all characters 3244 * except letters, digits, ".", "_", and "-" deleted. 3245 * Return value: 3246 * TRUE: enable revert to defaults 3247 * FALSE: disable revert to defaults 3248 * 3249 * NOTE: revert to power on defaults that includes reverting to MDMA 3250 * mode is allowed by ATA-6 & ATA-7 specs. 3251 * Therefore drives exhibiting this behaviour are not violating the spec. 3252 * Furthermore, the spec explicitly says that after the soft reset 3253 * host should check the current setting of the device features. 3254 * Correctly working BIOS would therefore reprogram either the drive 3255 * and/or the host controller to match transfer modes. 3256 * Devices with ATA_BL_NORVRT flag will be removed from 3257 * the ata_blacklist. 3258 * The default behaviour will be - no revert to power-on defaults 3259 * for all devices. The property is retained in case the user 3260 * explicitly requests revert-to-defaults before reboot. 3261 */ 3262 3263#define ATA_REVERT_PROP_PREFIX "revert-" 3264#define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3265/* room for prefix + model number + terminating NUL character */ 3266#define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3267 sizeof (aidp->ai_model) + 1) 3268#define PROP_LEN_MAX (31) 3269 3270static int 3271ata_check_revert_to_defaults( 3272 ata_drv_t *ata_drvp) 3273{ 3274 struct ata_id *aidp = &ata_drvp->ad_id; 3275 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3276 char prop_buf[PROP_BUF_SIZE]; 3277 int i, j; 3278 int propval; 3279 3280 /* put prefix into the buffer */ 3281 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3282 j = strlen(prop_buf); 3283 3284 /* append the model number, leaving out invalid characters */ 3285 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3286 char c = aidp->ai_model[i]; 3287 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3288 c = c - 'A' + 'a'; 3289 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3290 c == '.' || c == '_' || c == '-') 3291 prop_buf[j++] = c; 3292 if (c == '\0') 3293 break; 3294 } 3295 3296 /* make sure there's a terminating NUL character */ 3297 if (j >= PROP_LEN_MAX) 3298 j = PROP_LEN_MAX; 3299 prop_buf[j] = '\0'; 3300 3301 /* look for a disk-specific "revert" property" */ 3302 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3303 DDI_PROP_DONTPASS, prop_buf, -1); 3304 if (propval == 0) 3305 return (FALSE); 3306 else if (propval != -1) 3307 return (TRUE); 3308 3309 /* look for a global "revert" property" */ 3310 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3311 0, ATA_REVERT_PROP_GLOBAL, -1); 3312 if (propval == 0) 3313 return (FALSE); 3314 else if (propval != -1) 3315 return (TRUE); 3316 3317 return (FALSE); 3318} 3319 3320void 3321ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3322{ 3323 int i; 3324 3325 if (ata_ctlp->ac_pciide_bm == FALSE || 3326 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3327 if (ata_cntrl_DMA_sel_msg) { 3328 ATAPRT(( 3329 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3330 } else if (ata_dev_DMA_sel_msg) { 3331 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3332 } 3333 ATAPRT(("?\tPIO mode %d selected\n", 3334 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3335 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3336 } else { 3337 /* Using DMA */ 3338 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3339 /* 3340 * Rely on the fact that either dwdma or udma is 3341 * selected, not both. 3342 */ 3343 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3344 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3345 ATAC_MDMA_2_SEL ? 2 : 3346 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3347 ATAC_MDMA_1_SEL ? 1 : 0)); 3348 } else { 3349 for (i = 0; i <= 6; i++) { 3350 if (ata_drvp->ad_id.ai_ultradma & 3351 (1 << (i + 8))) { 3352 ATAPRT(( 3353 "?\tUltraDMA mode %d selected\n", 3354 i)); 3355 break; 3356 } 3357 } 3358 } 3359 } 3360} 3361 3362/* 3363 * Controller-specific operation pointers. 3364 * Should be extended as needed - init only for now 3365 */ 3366struct ata_ctl_spec_ops { 3367 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3368}; 3369 3370 3371struct ata_ctl_spec { 3372 ushort_t cs_vendor_id; 3373 ushort_t cs_device_id; 3374 struct ata_ctl_spec_ops *cs_ops; 3375}; 3376 3377/* Sil3XXX-specific functions (init only for now) */ 3378struct ata_ctl_spec_ops sil3xxx_ops = { 3379 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3380}; 3381 3382 3383struct ata_ctl_spec ata_cntrls_spec[] = { 3384 {0x1095, 0x3114, &sil3xxx_ops}, 3385 {0x1095, 0x3512, &sil3xxx_ops}, 3386 {0x1095, 0x3112, &sil3xxx_ops}, 3387 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3388}; 3389 3390/* 3391 * Do controller specific initialization if necessary. 3392 * Pick-up controller specific functions. 3393 */ 3394 3395int 3396ata_spec_init_controller(dev_info_t *dip) 3397{ 3398 ushort_t vendor_id; 3399 ushort_t device_id; 3400 struct ata_ctl_spec *ctlsp; 3401 3402 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3403 DDI_PROP_DONTPASS, "vendor-id", 0); 3404 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3405 DDI_PROP_DONTPASS, "device-id", 0); 3406 3407 /* Locate controller specific ops, if they exist */ 3408 ctlsp = ata_cntrls_spec; 3409 while (ctlsp->cs_ops != NULL) { 3410 if (ctlsp->cs_vendor_id == vendor_id && 3411 ctlsp->cs_device_id == device_id) 3412 break; 3413 ctlsp++; 3414 } 3415 3416 if (ctlsp->cs_ops != NULL) { 3417 if (ctlsp->cs_ops->cs_init != NULL) { 3418 /* Initialize controller */ 3419 if ((*(ctlsp->cs_ops->cs_init)) 3420 (dip, vendor_id, device_id) != TRUE) { 3421 cmn_err(CE_WARN, 3422 "pci%4x,%4x cntrl specific " 3423 "initialization failed", 3424 vendor_id, device_id); 3425 return (FALSE); 3426 } 3427 } 3428 } 3429 return (TRUE); 3430} 3431 3432/* 3433 * this routine works like ddi_prop_get_int, except that it works on 3434 * a string property that contains ascii representations 3435 * of an integer. 3436 * If the property is not found, the default value is returned. 3437 */ 3438static int 3439ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3440 uint_t flags, char *name, int defvalue) 3441{ 3442 3443 char *bufp, *cp; 3444 int rc = defvalue; 3445 int proprc; 3446 3447 proprc = ddi_prop_lookup_string(match_dev, dip, 3448 flags, name, &bufp); 3449 3450 if (proprc == DDI_PROP_SUCCESS) { 3451 cp = bufp; 3452 rc = stoi(&cp); 3453 ddi_prop_free(bufp); 3454 } else { 3455 /* 3456 * see if property is encoded as an int instead of string. 3457 */ 3458 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3459 } 3460 3461 return (rc); 3462} 3463 3464/* 3465 * Initialize the power management components 3466 */ 3467static void 3468ata_init_pm(dev_info_t *dip) 3469{ 3470 char pmc_name[16]; 3471 char *pmc[] = { 3472 NULL, 3473 "0=Sleep (PCI D3 State)", 3474 "3=PowerOn (PCI D0 State)", 3475 NULL 3476 }; 3477 int instance; 3478 ata_ctl_t *ata_ctlp; 3479 3480 3481 instance = ddi_get_instance(dip); 3482 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3483 ata_ctlp->ac_pm_support = 0; 3484 3485 /* check PCI capabilities */ 3486 if (!ata_is_pci(dip)) 3487 return; 3488 3489 (void) sprintf(pmc_name, "NAME=ata%d", instance); 3490 pmc[0] = pmc_name; 3491 3492#ifdef ATA_USE_AUTOPM 3493 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3494 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 3495 return; 3496 } 3497#endif 3498 3499 ata_ctlp->ac_pm_support = 1; 3500 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3501 3502 ATA_BUSY_COMPONENT(dip, 0); 3503 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 3504 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 3505 } 3506 ATA_IDLE_COMPONENT(dip, 0); 3507} 3508 3509/* 3510 * resume the hard drive 3511 */ 3512static void 3513ata_resume_drive(ata_drv_t *ata_drvp) 3514{ 3515 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3516 int drive_type; 3517 struct ata_id id; 3518 3519 ADBG_TRACE(("ata_resume_drive entered\n")); 3520 3521 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 3522 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3523 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3524 &id); 3525 if (drive_type == ATA_DEV_NONE) 3526 return; 3527 3528 if (!ATAPIDRV(ata_drvp)) { 3529 /* Reset Ultra DMA mode */ 3530 (void) ata_set_dma_mode(ata_ctlp, ata_drvp); 3531 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 3532 return; 3533 } else { 3534 (void) atapi_init_drive(ata_drvp); 3535 } 3536 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 3537 3538} 3539 3540/* 3541 * resume routine, it will be run when get the command 3542 * DDI_RESUME at attach(9E) from system power management 3543 */ 3544static int 3545ata_resume(dev_info_t *dip) 3546{ 3547 int instance; 3548 ata_ctl_t *ata_ctlp; 3549 ddi_acc_handle_t io_hdl2; 3550 caddr_t ioaddr2; 3551 3552 instance = ddi_get_instance(dip); 3553 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3554 3555 if (!ata_ctlp->ac_pm_support) 3556 return (DDI_FAILURE); 3557 if (ata_ctlp->ac_pm_level == PM_LEVEL_D0) 3558 return (DDI_SUCCESS); 3559 3560 ATA_BUSY_COMPONENT(dip, 0); 3561 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE) 3562 return (DDI_FAILURE); 3563 ATA_IDLE_COMPONENT(dip, 0); 3564 3565 /* enable interrupts from the device */ 3566 io_hdl2 = ata_ctlp->ac_iohandle2; 3567 ioaddr2 = ata_ctlp->ac_ioaddr2; 3568 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 3569 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3570 3571 return (DDI_SUCCESS); 3572} 3573 3574/* 3575 * suspend routine, it will be run when get the command 3576 * DDI_SUSPEND at detach(9E) from system power management 3577 */ 3578static int 3579ata_suspend(dev_info_t *dip) 3580{ 3581 int instance; 3582 ata_ctl_t *ata_ctlp; 3583 ddi_acc_handle_t io_hdl2; 3584 3585 instance = ddi_get_instance(dip); 3586 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3587 3588 if (!ata_ctlp->ac_pm_support) 3589 return (DDI_FAILURE); 3590 if (ata_ctlp->ac_pm_level == PM_LEVEL_D3) 3591 return (DDI_SUCCESS); 3592 3593 /* disable interrupts and turn the software reset bit on */ 3594 io_hdl2 = ata_ctlp->ac_iohandle2; 3595 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 3596 3597 (void) ata_reset_bus(ata_ctlp); 3598 (void) ata_change_power(dip, ATC_SLEEP); 3599 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3600 return (DDI_SUCCESS); 3601} 3602 3603int ata_save_pci_config = 0; 3604/* 3605 * ata specific power management entry point, it was 3606 * used to change the power management component 3607 */ 3608static int 3609ata_power(dev_info_t *dip, int component, int level) 3610{ 3611 int instance; 3612 ata_ctl_t *ata_ctlp; 3613 uint8_t cmd; 3614 3615 ADBG_TRACE(("ata_power entered, component = %d, level = %d\n", 3616 component, level)); 3617 3618 instance = ddi_get_instance(dip); 3619 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3620 if (ata_ctlp == NULL || component != 0) 3621 return (DDI_FAILURE); 3622 3623 if (!ata_ctlp->ac_pm_support) 3624 return (DDI_FAILURE); 3625 3626 switch (level) { 3627 case PM_LEVEL_D0: 3628 if (ata_save_pci_config) 3629 (void) pci_restore_config_regs(dip); 3630 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3631 cmd = ATC_IDLE_IMMED; 3632 break; 3633 case PM_LEVEL_D3: 3634 if (ata_save_pci_config) 3635 (void) pci_save_config_regs(dip); 3636 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3637 cmd = ATC_SLEEP; 3638 break; 3639 default: 3640 return (DDI_FAILURE); 3641 } 3642 return (ata_change_power(dip, cmd)); 3643} 3644 3645/* 3646 * sent commands to ata controller to change the power level 3647 */ 3648static int 3649ata_change_power(dev_info_t *dip, uint8_t cmd) 3650{ 3651 int instance; 3652 ata_ctl_t *ata_ctlp; 3653 ata_drv_t *ata_drvp; 3654 uchar_t targ; 3655 struct ata_id id; 3656 uchar_t lun; 3657 uchar_t lastlun; 3658 3659 ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd)); 3660 3661 instance = ddi_get_instance(dip); 3662 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3663 /* 3664 * Issue command on each disk device on the bus. 3665 */ 3666 if (cmd == ATC_SLEEP) { 3667 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3668 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3669 if (ata_drvp == NULL) 3670 continue; 3671 if (ata_drive_type(ata_drvp->ad_drive_bits, 3672 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3673 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3674 &id) != ATA_DEV_DISK) 3675 continue; 3676 (void) ata_flush_cache(ata_ctlp, ata_drvp); 3677 if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 3678 5 * 1000000, cmd, 0, 0, 0, 0, 0, 0)) { 3679 cmn_err(CE_WARN, "!ata_controller - Can not " 3680 "put drive %d in to power mode %u", 3681 targ, cmd); 3682 (void) ata_devo_reset(dip, DDI_RESET_FORCE); 3683 return (DDI_FAILURE); 3684 } 3685 } 3686 return (DDI_SUCCESS); 3687 } 3688 3689 (void) ata_software_reset(ata_ctlp); 3690 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3691 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3692 if (ata_drvp == NULL) 3693 continue; 3694 ata_resume_drive(ata_drvp); 3695 3696 if (ATAPIDRV(ata_drvp)) 3697 lastlun = ata_drvp->ad_id.ai_lastlun; 3698 else 3699 lastlun = 0; 3700 if (!ata_enable_atapi_luns) 3701 lastlun = 0; 3702 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 3703 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 3704 if (ata_drvp != NULL) 3705 ata_resume_drive(ata_drvp); 3706 } 3707 } 3708 3709 return (DDI_SUCCESS); 3710} 3711 3712/* 3713 * return 1 when ata controller is a pci device, 3714 * otherwise return 0 3715 */ 3716static int 3717ata_is_pci(dev_info_t *dip) 3718{ 3719 int rc; 3720 char *bufp; 3721 int ispci; 3722 3723 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 3724 DDI_PROP_DONTPASS, "device_type", &bufp); 3725 3726 if (rc != DDI_PROP_SUCCESS) { 3727 ADBG_ERROR(("ata_is_pci !device_type\n")); 3728 return (0); 3729 } 3730 3731 ispci = (strcmp(bufp, "pci-ide") == 0); 3732 3733 ddi_prop_free(bufp); 3734 3735 return (ispci); 3736} 3737 3738/* 3739 * Disable DMA for this drive 3740 */ 3741static void 3742ata_disable_DMA(ata_drv_t *ata_drvp) 3743{ 3744 struct ata_id *aidp; 3745 char buf[sizeof (aidp->ai_model) +2]; 3746 int i; 3747 3748 if (ata_drvp == NULL) 3749 return; 3750 3751 if (ata_drvp->ad_pciide_dma == ATA_DMA_OFF) 3752 return; 3753 3754 ata_drvp->ad_pciide_dma = ATA_DMA_OFF; 3755 3756 /* Print the message */ 3757 buf[0] = '\0'; 3758 aidp = &ata_drvp->ad_id; 3759 if (aidp != NULL) { 3760 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 3761 buf[sizeof (aidp->ai_model) -1] = '\0'; 3762 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 3763 buf[i] = '\0'; 3764 } 3765 cmn_err(CE_CONT, 3766 "?DMA disabled on %s target=%d, lun=%d due to DMA errors,", 3767 buf, ata_drvp->ad_targ, ata_drvp->ad_lun); 3768 cmn_err(CE_CONT, "?most likely due to the CF-to-IDE adapter."); 3769} 3770 3771/* 3772 * Check and select DMA mode 3773 * 3774 * TRUE is returned when set feature is called successfully, 3775 * otherwise return FALSE 3776 */ 3777int 3778ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3779{ 3780 struct ata_id *aidp; 3781 int mode, rval = FALSE; 3782 uint8_t subcmd; 3783 3784 aidp = &ata_drvp->ad_id; 3785 3786 /* Return directly if DMA is not supported */ 3787 if (!(aidp->ai_cap & ATAC_DMA_SUPPORT)) 3788 return (rval); 3789 3790 /* First check Ultra DMA mode if no DMA is selected */ 3791 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3792 (aidp->ai_ultradma & ATAC_UDMA_SUP_MASK)) { 3793 for (mode = 6; mode >= 0; --mode) { 3794 if (aidp->ai_ultradma & (1 << mode)) 3795 break; 3796 } 3797 subcmd = ATF_XFRMOD_UDMA; 3798 3799 } else if (aidp->ai_dworddma & ATAC_MDMA_SUP_MASK) { 3800 /* Then check multi-word DMA mode */ 3801 for (mode = 2; mode >= 0; --mode) { 3802 if (aidp->ai_dworddma & (1 << mode)) 3803 break; 3804 } 3805 subcmd = ATF_XFRMOD_MDMA; 3806 3807 } else { 3808 return (rval); 3809 } 3810 3811 rval = ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3812 subcmd|mode); 3813 3814 return (rval); 3815} 3816