1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#include <sys/types.h> 28#include <sys/modctl.h> 29#include <sys/debug.h> 30#include <sys/promif.h> 31#include <sys/pci.h> 32#include <sys/errno.h> 33#include <sys/open.h> 34#include <sys/uio.h> 35#include <sys/cred.h> 36#include <sys/cpu.h> 37#include "ata_common.h" 38#include "ata_disk.h" 39#include "atapi.h" 40#include "ata_blacklist.h" 41#include "sil3xxx.h" 42 43/* 44 * Solaris Entry Points. 45 */ 46 47static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 48static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 49static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 50 void *a, void *v); 51static uint_t ata_intr(caddr_t arg); 52 53/* 54 * GHD Entry points 55 */ 56 57static int ata_get_status(void *hba_handle, void *intr_status); 58static void ata_process_intr(void *hba_handle, void *intr_status); 59static int ata_hba_start(void *handle, gcmd_t *gcmdp); 60static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 61static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 62 gtgt_t *gtgtp, gact_t action, int calltype); 63 64/* 65 * Local Function Prototypes 66 */ 67static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 68 uint_t flags, char *name, int defvalue); 69static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 70 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 71 int *DoneFlgp); 72static void ata_destroy_controller(dev_info_t *dip); 73static int ata_drive_type(uchar_t drvhd, 74 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 75 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 76 struct ata_id *ata_id_bufp); 77static ata_ctl_t *ata_init_controller(dev_info_t *dip); 78static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 79 uchar_t targ, uchar_t lun); 80static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 81 dev_info_t *tdip); 82static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 83static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 84static int ata_reset_bus(ata_ctl_t *ata_ctlp); 85static int ata_setup_ioaddr(dev_info_t *dip, 86 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 87 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 88 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 89static int ata_software_reset(ata_ctl_t *ata_ctlp); 90static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 91 ata_pkt_t *ata_pktp); 92static int ata_strncmp(char *p1, char *p2, int cnt); 93static void ata_uninit_drive(ata_drv_t *ata_drvp); 94 95static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 96static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 97static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 98static int ata_spec_init_controller(dev_info_t *dip); 99 100static void ata_init_pm(dev_info_t *); 101static int ata_suspend(dev_info_t *); 102static int ata_resume(dev_info_t *); 103static int ata_power(dev_info_t *, int, int); 104static int ata_change_power(dev_info_t *, uint8_t); 105static int ata_is_pci(dev_info_t *); 106static void ata_disable_DMA(ata_drv_t *ata_drvp); 107static int ata_check_dma_mode(ata_drv_t *ata_drvp); 108 109/* 110 * Local static data 111 */ 112static void *ata_state; 113 114static tmr_t ata_timer_conf; /* single timeout list for all instances */ 115static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 116 117int ata_hba_start_watchdog = 1000; 118int ata_process_intr_watchdog = 1000; 119int ata_reset_bus_watchdog = 1000; 120 121 122/* 123 * Use local or framework power management 124 */ 125 126#ifdef ATA_USE_AUTOPM 127#define ATA_BUSY_COMPONENT(d, c) ((void)pm_busy_component(d, c)) 128#define ATA_IDLE_COMPONENT(d, c) ((void)pm_idle_component(d, c)) 129#define ATA_RAISE_POWER(d, c, l) pm_raise_power(d, c, l) 130#define ATA_LOWER_POWER(d, c, l) pm_lower_power(d, c, l) 131#else 132#define ATA_BUSY_COMPONENT(d, c) 133#define ATA_IDLE_COMPONENT(d, c) 134#define ATA_RAISE_POWER(d, c, l) ata_power(d, c, l) 135#define ATA_LOWER_POWER(d, c, l) ata_power(d, c, l) 136#endif 137/* 138 * number of seconds to wait during various operations 139 */ 140int ata_flush_delay = 5 * 1000000; 141uint_t ata_set_feature_wait = 4 * 1000000; 142uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 143 144/* 145 * Change this for SFF-8070i support. Currently SFF-8070i is 146 * using a field in the IDENTIFY PACKET DEVICE response which 147 * already seems to be in use by some vendor's drives. I suspect 148 * SFF will either move their laslun field or provide a reliable 149 * way to validate it. 150 */ 151int ata_enable_atapi_luns = FALSE; 152 153/* 154 * set this to disable all DMA requests 155 */ 156int ata_dma_disabled = FALSE; 157 158/* 159 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 160 * "ata" or "atapi" property. 161 */ 162int ata_id_debug = FALSE; 163 164/* 165 * set this to TRUE to enable logging device-capability data 166 */ 167int ata_capability_data = FALSE; 168 169/* 170 * DMA selection message pointers 171 */ 172char *ata_cntrl_DMA_sel_msg; 173char *ata_dev_DMA_sel_msg; 174 175/* 176 * bus nexus operations 177 */ 178static struct bus_ops ata_bus_ops; 179static struct bus_ops *scsa_bus_ops_p; 180 181/* ARGSUSED */ 182static int 183ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 184{ 185 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 186 return (ENXIO); 187 188 return (0); 189} 190 191/* 192 * The purpose of this function is to pass the ioaddress of the controller 193 * to the caller, specifically used for upgrade from pre-pciide 194 * to pciide nodes 195 */ 196/* ARGSUSED */ 197static int 198ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 199{ 200 ata_ctl_t *ata_ctlp; 201 char buf[18]; 202 long len; 203 204 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 205 206 if (ata_ctlp == NULL) 207 return (ENXIO); 208 209 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 210 211 len = strlen(buf) - uio_p->uio_offset; 212 len = min(uio_p->uio_resid, len); 213 if (len <= 0) 214 return (0); 215 216 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 217 UIO_READ, uio_p)); 218} 219 220int 221ata_devo_reset( 222 dev_info_t *dip, 223 ddi_reset_cmd_t cmd) 224{ 225 ata_ctl_t *ata_ctlp; 226 ata_drv_t *ata_drvp; 227 int instance; 228 int i; 229 int rc; 230 int flush_okay; 231 232 if (cmd != DDI_RESET_FORCE) 233 return (0); 234 235 instance = ddi_get_instance(dip); 236 ata_ctlp = ddi_get_soft_state(ata_state, instance); 237 238 if (!ata_ctlp) 239 return (0); 240 241 /* 242 * reset ATA drives and flush the write cache of any drives 243 */ 244 flush_okay = TRUE; 245 for (i = 0; i < ATA_MAXTARG; i++) { 246 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 247 continue; 248 /* Don't revert to defaults for certain IBM drives */ 249 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 250 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 251 /* Enable revert to defaults when reset */ 252 (void) ata_set_feature(ata_ctlp, ata_drvp, 253 ATSF_ENA_REVPOD, 0); 254 } 255 256 /* 257 * skip flush cache if device type is cdrom 258 * 259 * notes: the structure definitions for ata_drvp->ad_id are 260 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 261 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 262 */ 263 if (!IS_CDROM(ata_drvp)) { 264 265 /* 266 * Try the ATA/ATAPI flush write cache command 267 */ 268 rc = ata_flush_cache(ata_ctlp, ata_drvp); 269 ADBG_WARN(("ata_flush_cache %s\n", 270 rc ? "okay" : "failed")); 271 272 if (!rc) 273 flush_okay = FALSE; 274 } 275 276 277 /* 278 * do something else if flush cache not supported 279 */ 280 } 281 282 /* 283 * just busy wait if any drive doesn't support FLUSH CACHE 284 */ 285 if (!flush_okay) 286 drv_usecwait(ata_flush_delay); 287 return (0); 288} 289 290/* 291 * quiesce(9E) entry point. 292 * 293 * This function is called when the system is single-threaded at high 294 * PIL with preemption disabled. Therefore, this function must not be 295 * blocked. 296 * 297 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 298 * DDI_FAILURE indicates an error condition and should almost never happen. 299 */ 300int 301ata_quiesce(dev_info_t *dip) 302{ 303#ifdef ATA_DEBUG 304 /* 305 * Turn off debugging 306 */ 307 ata_debug = 0; 308#endif 309 310 return (ata_devo_reset(dip, DDI_RESET_FORCE)); 311} 312 313 314static struct cb_ops ata_cb_ops = { 315 ata_open, /* open */ 316 nulldev, /* close */ 317 nodev, /* strategy */ 318 nodev, /* print */ 319 nodev, /* dump */ 320 ata_read, /* read */ 321 nodev, /* write */ 322 nodev, /* ioctl */ 323 nodev, /* devmap */ 324 nodev, /* mmap */ 325 nodev, /* segmap */ 326 nochpoll, /* chpoll */ 327 ddi_prop_op, /* prop_op */ 328 NULL, /* stream info */ 329 D_MP, /* driver compatibility flag */ 330 CB_REV, /* cb_ops revision */ 331 nodev, /* aread */ 332 nodev /* awrite */ 333}; 334 335static struct dev_ops ata_ops = { 336 DEVO_REV, /* devo_rev, */ 337 0, /* refcnt */ 338 ddi_getinfo_1to1, /* info */ 339 nulldev, /* identify */ 340 NULL, /* probe */ 341 ata_attach, /* attach */ 342 ata_detach, /* detach */ 343 ata_devo_reset, /* reset */ 344 &ata_cb_ops, /* driver operations */ 345 NULL, /* bus operations */ 346 ata_power, /* power */ 347 ata_quiesce /* quiesce */ 348}; 349 350/* driver loadable module wrapper */ 351static struct modldrv modldrv = { 352 &mod_driverops, /* Type of module. This one is a driver */ 353 "ATA AT-bus attachment disk controller Driver", /* module name */ 354 &ata_ops, /* driver ops */ 355}; 356 357static struct modlinkage modlinkage = { 358 MODREV_1, (void *)&modldrv, NULL 359}; 360 361#ifdef ATA_DEBUG 362int ata_debug_init = FALSE; 363int ata_debug_attach = FALSE; 364 365int ata_debug = ADBG_FLAG_ERROR 366 /* | ADBG_FLAG_ARQ */ 367 /* | ADBG_FLAG_INIT */ 368 /* | ADBG_FLAG_TRACE */ 369 /* | ADBG_FLAG_TRANSPORT */ 370 /* | ADBG_FLAG_WARN */ 371 ; 372#endif 373 374int 375_init(void) 376{ 377 int err; 378 379#ifdef ATA_DEBUG 380 if (ata_debug_init) 381 debug_enter("\nATA _INIT\n"); 382#endif 383 384 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 385 return (err); 386 387 if ((err = scsi_hba_init(&modlinkage)) != 0) { 388 ddi_soft_state_fini(&ata_state); 389 return (err); 390 } 391 392 /* save pointer to SCSA provided bus_ops struct */ 393 scsa_bus_ops_p = ata_ops.devo_bus_ops; 394 395 /* make a copy of SCSA bus_ops */ 396 ata_bus_ops = *(ata_ops.devo_bus_ops); 397 398 /* 399 * Modify our bus_ops to call our routines. Our implementation 400 * will determine if the device is ATA or ATAPI/SCSA and react 401 * accordingly. 402 */ 403 ata_bus_ops.bus_ctl = ata_bus_ctl; 404 405 /* patch our bus_ops into the dev_ops struct */ 406 ata_ops.devo_bus_ops = &ata_bus_ops; 407 408 if ((err = mod_install(&modlinkage)) != 0) { 409 scsi_hba_fini(&modlinkage); 410 ddi_soft_state_fini(&ata_state); 411 } 412 413 /* 414 * Initialize the per driver timer info. 415 */ 416 417 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 418 419 return (err); 420} 421 422int 423_fini(void) 424{ 425 int err; 426 427 if ((err = mod_remove(&modlinkage)) == 0) { 428 ghd_timer_fini(&ata_timer_conf); 429 scsi_hba_fini(&modlinkage); 430 ddi_soft_state_fini(&ata_state); 431 } 432 433 return (err); 434} 435 436int 437_info(struct modinfo *modinfop) 438{ 439 return (mod_info(&modlinkage, modinfop)); 440} 441 442 443/* 444 * 445 * driver attach entry point 446 * 447 */ 448 449static int 450ata_attach( 451 dev_info_t *dip, 452 ddi_attach_cmd_t cmd) 453{ 454 ata_ctl_t *ata_ctlp; 455 ata_drv_t *ata_drvp; 456 ata_drv_t *first_drvp = NULL; 457 uchar_t targ; 458 uchar_t lun; 459 uchar_t lastlun; 460 int atapi_count = 0; 461 int disk_count = 0; 462 463 ADBG_TRACE(("ata_attach entered\n")); 464#ifdef ATA_DEBUG 465 if (ata_debug_attach) 466 debug_enter("\nATA_ATTACH\n\n"); 467#endif 468 469 switch (cmd) { 470 case DDI_ATTACH: 471 break; 472 case DDI_RESUME: 473 return (ata_resume(dip)); 474 default: 475 return (DDI_FAILURE); 476 } 477 478 /* initialize controller */ 479 ata_ctlp = ata_init_controller(dip); 480 481 if (ata_ctlp == NULL) 482 goto errout; 483 484 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 485 486 /* initialize drives */ 487 488 for (targ = 0; targ < ATA_MAXTARG; targ++) { 489 490 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 491 if (ata_drvp == NULL) 492 continue; 493 494 if (first_drvp == NULL) 495 first_drvp = ata_drvp; 496 497 if (ATAPIDRV(ata_drvp)) { 498 atapi_count++; 499 lastlun = ata_drvp->ad_id.ai_lastlun; 500 } else { 501 disk_count++; 502 lastlun = 0; 503 } 504 505 /* 506 * LUN support is currently disabled. Check with SFF-8070i 507 * before enabling. 508 */ 509 if (!ata_enable_atapi_luns) 510 lastlun = 0; 511 512 /* Initialize higher LUNs, if there are any */ 513 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 514 if ((ata_drvp = 515 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 516 ata_show_transfer_mode(ata_ctlp, ata_drvp); 517 } 518 } 519 } 520 521 if ((atapi_count == 0) && (disk_count == 0)) { 522 ADBG_WARN(("ata_attach: no drives detected\n")); 523 goto errout1; 524 } 525 526 /* 527 * Always make certain that a valid drive is selected so 528 * that routines which poll the status register don't get 529 * confused by non-existent drives. 530 */ 531 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 532 first_drvp->ad_drive_bits); 533 ata_nsecwait(400); 534 535 /* 536 * make certain the drive selected 537 */ 538 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 539 0, ATS_BSY, 5000000)) { 540 ADBG_ERROR(("ata_attach: select failed\n")); 541 } 542 543 /* 544 * initialize atapi/ata_dsk modules if we have at least 545 * one drive of that type. 546 */ 547 548 if (atapi_count) { 549 if (!atapi_attach(ata_ctlp)) 550 goto errout1; 551 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 552 } 553 554 if (disk_count) { 555 if (!ata_disk_attach(ata_ctlp)) 556 goto errout1; 557 ata_ctlp->ac_flags |= AC_DISK_INIT; 558 } 559 560 /* 561 * make certain the interrupt and error latches are clear 562 */ 563 if (ata_ctlp->ac_pciide) { 564 565 int instance = ddi_get_instance(dip); 566 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 567 DDI_PSEUDO, 0) != DDI_SUCCESS) { 568 goto errout1; 569 } 570 571 (void) ata_pciide_status_clear(ata_ctlp); 572 573 } 574 575 /* 576 * enable the interrupt handler and drop the mutex 577 */ 578 ata_ctlp->ac_flags |= AC_ATTACHED; 579 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 580 581 ata_init_pm(dip); 582 583 ddi_report_dev(dip); 584 return (DDI_SUCCESS); 585 586errout1: 587 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 588errout: 589 (void) ata_detach(dip, DDI_DETACH); 590 return (DDI_FAILURE); 591} 592 593/* driver detach entry point */ 594 595static int 596ata_detach( 597 dev_info_t *dip, 598 ddi_detach_cmd_t cmd) 599{ 600 ata_ctl_t *ata_ctlp; 601 ata_drv_t *ata_drvp; 602 int instance; 603 int i; 604 int j; 605 606 ADBG_TRACE(("ata_detach entered\n")); 607 608 switch (cmd) { 609 case DDI_DETACH: 610 break; 611 case DDI_SUSPEND: 612 return (ata_suspend(dip)); 613 default: 614 return (DDI_FAILURE); 615 } 616 617 instance = ddi_get_instance(dip); 618 ata_ctlp = ddi_get_soft_state(ata_state, instance); 619 620 if (!ata_ctlp) 621 return (DDI_SUCCESS); 622 623 if (ata_ctlp->ac_pm_support) { 624 ATA_BUSY_COMPONENT(dip, 0); 625 if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) { 626 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != 627 DDI_SUCCESS) { 628 ATA_IDLE_COMPONENT(dip, 0); 629 return (DDI_FAILURE); 630 } 631 } 632 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 633 } 634 ata_ctlp->ac_flags &= ~AC_ATTACHED; 635 636 /* destroy ata module */ 637 if (ata_ctlp->ac_flags & AC_DISK_INIT) 638 ata_disk_detach(ata_ctlp); 639 640 /* destroy atapi module */ 641 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 642 atapi_detach(ata_ctlp); 643 644 ddi_remove_minor_node(dip, NULL); 645 646 /* destroy drives */ 647 for (i = 0; i < ATA_MAXTARG; i++) { 648 for (j = 0; j < ATA_MAXLUN; j++) { 649 ata_drvp = CTL2DRV(ata_ctlp, i, j); 650 if (ata_drvp != NULL) 651 ata_uninit_drive(ata_drvp); 652 } 653 } 654 655 if (ata_ctlp->ac_iohandle1) 656 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 657 if (ata_ctlp->ac_iohandle2) 658 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 659 if (ata_ctlp->ac_bmhandle) 660 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 661 662 /* destroy controller */ 663 ata_destroy_controller(dip); 664 665 ddi_prop_remove_all(dip); 666 667 return (DDI_SUCCESS); 668} 669 670/* 671 * Nexus driver bus_ctl entry point 672 */ 673/*ARGSUSED*/ 674static int 675ata_bus_ctl( 676 dev_info_t *d, 677 dev_info_t *r, 678 ddi_ctl_enum_t o, 679 void *a, 680 void *v) 681{ 682 dev_info_t *tdip; 683 int target_type; 684 int rc; 685 char *bufp; 686 687 ADBG_TRACE(("ata_bus_ctl entered\n")); 688 689 switch (o) { 690 691 case DDI_CTLOPS_SIDDEV: 692 return (DDI_FAILURE); 693 694 case DDI_CTLOPS_IOMIN: 695 696 /* 697 * Since we use PIO, we return a minimum I/O size of 698 * one byte. This will need to be updated when we 699 * implement DMA support 700 */ 701 702 *((int *)v) = 1; 703 return (DDI_SUCCESS); 704 705 case DDI_CTLOPS_DMAPMAPC: 706 case DDI_CTLOPS_REPORTINT: 707 case DDI_CTLOPS_REGSIZE: 708 case DDI_CTLOPS_NREGS: 709 case DDI_CTLOPS_SLAVEONLY: 710 case DDI_CTLOPS_AFFINITY: 711 case DDI_CTLOPS_POKE: 712 case DDI_CTLOPS_PEEK: 713 714 /* These ops shouldn't be called by a target driver */ 715 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 716 ddi_driver_name(d), ddi_get_instance(d), o, 717 ddi_driver_name(r), ddi_get_instance(r))); 718 719 return (DDI_FAILURE); 720 721 case DDI_CTLOPS_REPORTDEV: 722 case DDI_CTLOPS_INITCHILD: 723 case DDI_CTLOPS_UNINITCHILD: 724 725 /* these require special handling below */ 726 break; 727 728 default: 729 return (ddi_ctlops(d, r, o, a, v)); 730 } 731 732 /* get targets dip */ 733 734 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 735 tdip = (dev_info_t *)a; 736 else 737 tdip = r; 738 739 /* 740 * XXX - Get class of target 741 * Before the "class" entry in a conf file becomes 742 * a real property, we use an additional property 743 * tentatively called "class_prop". We will require that 744 * new classes (ie. direct) export "class_prop". 745 * SCSA target drivers will not have this property, so 746 * no property implies SCSA. 747 */ 748 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 749 "class", &bufp) == DDI_PROP_SUCCESS) || 750 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 751 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 752 if (strcmp(bufp, "dada") == 0) 753 target_type = ATA_DEV_DISK; 754 else if (strcmp(bufp, "scsi") == 0) 755 target_type = ATA_DEV_ATAPI; 756 else { 757 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 758 bufp)); 759 ddi_prop_free(bufp); 760 return (DDI_FAILURE); 761 } 762 ddi_prop_free(bufp); 763 } else { 764 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 765 } 766 767 if (o == DDI_CTLOPS_INITCHILD) { 768 int instance = ddi_get_instance(d); 769 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 770 ata_drv_t *ata_drvp; 771 int targ; 772 int lun; 773 int drive_type; 774 char *disk_prop; 775 char *class_prop; 776 777 if (ata_ctlp == NULL) { 778 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 779 return (DDI_FAILURE); 780 } 781 782 /* get (target,lun) of child device */ 783 784 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 785 "target", -1); 786 if (targ == -1) { 787 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 788 return (DDI_FAILURE); 789 } 790 791 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 792 "lun", 0); 793 794 if ((targ < 0) || (targ >= ATA_MAXTARG) || 795 (lun < 0) || (lun >= ATA_MAXLUN)) { 796 return (DDI_FAILURE); 797 } 798 799 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 800 801 if (ata_drvp == NULL) 802 return (DDI_FAILURE); /* no drive */ 803 804 /* get type of device */ 805 806 if (ATAPIDRV(ata_drvp)) 807 drive_type = ATA_DEV_ATAPI; 808 else 809 drive_type = ATA_DEV_DISK; 810 811 /* 812 * Check for special handling when child driver is 813 * cmdk (which morphs to the correct interface) 814 */ 815 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 816 817 if ((target_type == ATA_DEV_DISK) && 818 (target_type != drive_type)) 819 return (DDI_FAILURE); 820 821 target_type = drive_type; 822 823 if (drive_type == ATA_DEV_ATAPI) { 824 class_prop = "scsi"; 825 } else { 826 disk_prop = "dadk"; 827 class_prop = "dada"; 828 829 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 830 "disk", disk_prop) != DDI_PROP_SUCCESS) { 831 ADBG_WARN(("ata_bus_ctl: failed to " 832 "create disk prop\n")); 833 return (DDI_FAILURE); 834 } 835 } 836 837 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 838 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 839 ADBG_WARN(("ata_bus_ctl: failed to " 840 "create class prop\n")); 841 return (DDI_FAILURE); 842 } 843 } 844 845 /* Check that target class matches the device */ 846 847 if (target_type != drive_type) 848 return (DDI_FAILURE); 849 850 /* save pointer to drive struct for ata_disk_bus_ctl */ 851 ddi_set_driver_private(tdip, ata_drvp); 852 853 /* 854 * Determine whether to enable DMA support for this drive. This 855 * check is deferred to this point so that the various dma 856 * properties could reside on the devinfo node should finer 857 * grained dma control be required. 858 */ 859 if (ata_drvp->ad_pciide_dma == ATA_DMA_UNINITIALIZED) { 860 ata_drvp->ad_pciide_dma = 861 ata_init_drive_pcidma(ata_ctlp, ata_drvp, tdip); 862 ata_show_transfer_mode(ata_ctlp, ata_drvp); 863 } 864 } 865 866 if (target_type == ATA_DEV_ATAPI) { 867 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 868 } else { 869 rc = ata_disk_bus_ctl(d, r, o, a, v); 870 } 871 872 return (rc); 873} 874 875/* 876 * 877 * GHD ccc_hba_complete callback 878 * 879 */ 880 881/* ARGSUSED */ 882static void 883ata_hba_complete( 884 void *hba_handle, 885 gcmd_t *gcmdp, 886 int do_callback) 887{ 888 ata_drv_t *ata_drvp; 889 ata_pkt_t *ata_pktp; 890 891 ADBG_TRACE(("ata_hba_complete entered\n")); 892 893 ata_drvp = GCMD2DRV(gcmdp); 894 ata_pktp = GCMD2APKT(gcmdp); 895 if (ata_pktp->ap_complete) 896 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 897 do_callback); 898} 899 900/* GHD ccc_timeout_func callback */ 901 902/* ARGSUSED */ 903static int 904ata_timeout_func( 905 void *hba_handle, 906 gcmd_t *gcmdp, 907 gtgt_t *gtgtp, 908 gact_t action, 909 int calltype) 910{ 911 ata_ctl_t *ata_ctlp; 912 ata_pkt_t *ata_pktp; 913 ata_drv_t *ata_drvp; 914 915 ADBG_TRACE(("ata_timeout_func entered\n")); 916 917 ata_ctlp = (ata_ctl_t *)hba_handle; 918 919 if (gcmdp != NULL) 920 ata_pktp = GCMD2APKT(gcmdp); 921 else 922 ata_pktp = NULL; 923 924 switch (action) { 925 case GACTION_EARLY_ABORT: 926 /* abort before request was started */ 927 if (ata_pktp != NULL) { 928 ata_pktp->ap_flags |= AP_ABORT; 929 } 930 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 931 return (TRUE); 932 933 case GACTION_EARLY_TIMEOUT: 934 /* timeout before request was started */ 935 if (ata_pktp != NULL) { 936 ata_pktp->ap_flags |= AP_TIMEOUT; 937 } 938 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 939 return (TRUE); 940 941 case GACTION_RESET_TARGET: 942 /* 943 * Reset a device is not supported. Resetting a specific 944 * device can't be done at all to an ATA device and if 945 * you send a RESET to an ATAPI device you have to 946 * reset the whole bus to make certain both devices 947 * on the bus stay in sync regarding which device is 948 * the currently selected one. 949 */ 950 return (FALSE); 951 952 case GACTION_RESET_BUS: 953 /* 954 * Issue bus reset and reinitialize both drives. 955 * But only if this is a timed-out request. Target 956 * driver reset requests are ignored because ATA 957 * and ATAPI devices shouldn't be gratuitously reset. 958 * Also disable DMA if it is a CF device. 959 */ 960 if (gcmdp == NULL) 961 break; 962 ata_drvp = GCMD2DRV(gcmdp); 963 if (ata_drvp != NULL) 964 if (ata_drvp->ad_id.ai_config == ATA_ID_CF_TO_ATA) 965 ata_disable_DMA(ata_drvp); 966 return (ata_reset_bus(ata_ctlp)); 967 default: 968 break; 969 } 970 return (FALSE); 971} 972 973/* 974 * 975 * Initialize controller's soft-state structure 976 * 977 */ 978 979static ata_ctl_t * 980ata_init_controller( 981 dev_info_t *dip) 982{ 983 ata_ctl_t *ata_ctlp; 984 int instance; 985 caddr_t ioaddr1; 986 caddr_t ioaddr2; 987 988 ADBG_TRACE(("ata_init_controller entered\n")); 989 990 instance = ddi_get_instance(dip); 991 992 /* allocate controller structure */ 993 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 994 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 995 return (NULL); 996 } 997 998 ata_ctlp = ddi_get_soft_state(ata_state, instance); 999 1000 if (ata_ctlp == NULL) { 1001 ADBG_WARN(("ata_init_controller: failed to find " 1002 "controller struct\n")); 1003 return (NULL); 1004 } 1005 1006 /* 1007 * initialize per-controller data 1008 */ 1009 ata_ctlp->ac_dip = dip; 1010 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 1011 1012 /* 1013 * map the device registers 1014 */ 1015 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 1016 &ata_ctlp->ac_iohandle2, &ioaddr2, 1017 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 1018 (void) ata_detach(dip, DDI_DETACH); 1019 return (NULL); 1020 } 1021 1022 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 1023 ioaddr1, ioaddr2)); 1024 1025 /* 1026 * Do ARQ setup 1027 */ 1028 atapi_init_arq(ata_ctlp); 1029 1030 /* 1031 * Do PCI-IDE setup 1032 */ 1033 ata_init_pciide(dip, ata_ctlp); 1034 1035 /* 1036 * port addresses associated with ioaddr1 1037 */ 1038 ata_ctlp->ac_ioaddr1 = ioaddr1; 1039 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1040 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1041 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1042 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1043 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1044 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1045 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1046 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1047 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1048 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1049 1050 /* 1051 * port addresses associated with ioaddr2 1052 */ 1053 ata_ctlp->ac_ioaddr2 = ioaddr2; 1054 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1055 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1056 1057 /* 1058 * If AC_BSY_WAIT needs to be set for laptops that do 1059 * suspend/resume but do not correctly wait for the busy bit to 1060 * drop after a resume. 1061 */ 1062 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1063 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1064 /* 1065 * get max transfer size, default to 256 sectors 1066 */ 1067 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1068 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1069 if (ata_ctlp->ac_max_transfer < 1) 1070 ata_ctlp->ac_max_transfer = 1; 1071 if (ata_ctlp->ac_max_transfer > 0x100) 1072 ata_ctlp->ac_max_transfer = 0x100; 1073 1074 /* 1075 * Get the standby timer value 1076 */ 1077 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1078 dip, DDI_PROP_DONTPASS, "standby", -1); 1079 1080 /* 1081 * If this is a /pci/pci-ide instance check to see if 1082 * it's supposed to be attached as an /isa/ata 1083 */ 1084 if (ata_ctlp->ac_pciide) { 1085 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1086 int addr1 = (intptr_t)ioaddr1; 1087 1088 1089 if (addr1 < 0 || addr1 > 0xffff) { 1090 (void) ata_detach(dip, DDI_DETACH); 1091 return (NULL); 1092 } 1093 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1094 addr1); 1095 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1096 DDI_PROP_DONTPASS, prop_buf)) { 1097 (void) ata_detach(dip, DDI_DETACH); 1098 return (NULL); 1099 } 1100 } 1101 1102 /* Init controller specific stuff */ 1103 (void) ata_spec_init_controller(dip); 1104 1105 /* 1106 * initialize GHD 1107 */ 1108 1109 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1110 1111 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1112 atapi_ccballoc, atapi_ccbfree, 1113 ata_pciide_dma_sg_func, ata_hba_start, 1114 ata_hba_complete, ata_intr, 1115 ata_get_status, ata_process_intr, ata_timeout_func, 1116 &ata_timer_conf, NULL)) { 1117 (void) ata_detach(dip, DDI_DETACH); 1118 return (NULL); 1119 } 1120 1121 ata_ctlp->ac_flags |= AC_GHD_INIT; 1122 return (ata_ctlp); 1123} 1124 1125/* destroy a controller */ 1126 1127static void 1128ata_destroy_controller( 1129 dev_info_t *dip) 1130{ 1131 ata_ctl_t *ata_ctlp; 1132 int instance; 1133 1134 ADBG_TRACE(("ata_destroy_controller entered\n")); 1135 1136 instance = ddi_get_instance(dip); 1137 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1138 1139 if (ata_ctlp == NULL) 1140 return; 1141 1142 /* destroy ghd */ 1143 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1144 ghd_unregister(&ata_ctlp->ac_ccc); 1145 1146 /* free the pciide buffer (if any) */ 1147 ata_pciide_free(ata_ctlp); 1148 1149 /* destroy controller struct */ 1150 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1151 ddi_soft_state_free(ata_state, instance); 1152 1153} 1154 1155 1156/* 1157 * 1158 * initialize a drive 1159 * 1160 */ 1161 1162static ata_drv_t * 1163ata_init_drive( 1164 ata_ctl_t *ata_ctlp, 1165 uchar_t targ, 1166 uchar_t lun) 1167{ 1168 static char nec_260[] = "NEC CD-ROM DRIVE"; 1169 ata_drv_t *ata_drvp; 1170 struct ata_id *aidp; 1171 char buf[80]; 1172 int drive_type; 1173 int i; 1174 int valid_version = 0; 1175 1176 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1177 targ, lun)); 1178 1179 /* check if device already exists */ 1180 1181 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1182 1183 if (ata_drvp != NULL) 1184 return (ata_drvp); 1185 1186 /* allocate new device structure */ 1187 1188 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1189 aidp = &ata_drvp->ad_id; 1190 1191 /* 1192 * set up drive struct 1193 */ 1194 ata_drvp->ad_ctlp = ata_ctlp; 1195 ata_drvp->ad_pciide_dma = ATA_DMA_UNINITIALIZED; 1196 ata_drvp->ad_targ = targ; 1197 ata_drvp->ad_drive_bits = 1198 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1199 /* 1200 * Add the LUN for SFF-8070i support 1201 */ 1202 ata_drvp->ad_lun = lun; 1203 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1204 1205 /* 1206 * get drive type, side effect is to collect 1207 * IDENTIFY DRIVE data 1208 */ 1209 1210 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1211 ata_ctlp->ac_iohandle1, 1212 ata_ctlp->ac_ioaddr1, 1213 ata_ctlp->ac_iohandle2, 1214 ata_ctlp->ac_ioaddr2, 1215 aidp); 1216 1217 switch (drive_type) { 1218 case ATA_DEV_NONE: 1219 /* no drive found */ 1220 goto errout; 1221 case ATA_DEV_ATAPI: 1222 ata_drvp->ad_flags |= AD_ATAPI; 1223 break; 1224 case ATA_DEV_DISK: 1225 ata_drvp->ad_flags |= AD_DISK; 1226 break; 1227 } 1228 1229 /* 1230 * swap bytes of all text fields 1231 */ 1232 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1233 swab(aidp->ai_drvser, aidp->ai_drvser, 1234 sizeof (aidp->ai_drvser)); 1235 swab(aidp->ai_fw, aidp->ai_fw, 1236 sizeof (aidp->ai_fw)); 1237 swab(aidp->ai_model, aidp->ai_model, 1238 sizeof (aidp->ai_model)); 1239 } 1240 1241 /* 1242 * Check if this drive has the Single Sector bug 1243 */ 1244 1245 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1246 ata_drvp->ad_flags |= AD_1SECTOR; 1247 else 1248 ata_drvp->ad_flags &= ~AD_1SECTOR; 1249 1250 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_LBA48)) 1251 ata_drvp->ad_flags |= AD_BLLBA48; 1252 else 1253 ata_drvp->ad_flags &= ~AD_BLLBA48; 1254 1255 /* Check if this drive has the "revert to defaults" bug */ 1256 if (!ata_check_revert_to_defaults(ata_drvp)) 1257 ata_drvp->ad_flags |= AD_NORVRT; 1258 1259 /* Dump the drive info */ 1260 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1261 buf[sizeof (aidp->ai_model)-1] = '\0'; 1262 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1263 buf[i] = '\0'; 1264 1265 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1266 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1267 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1268 1269 ATAPRT(("?\tmodel %s\n", buf)); 1270 1271 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1272 for (i = 14; i >= 2; i--) { 1273 if (aidp->ai_majorversion & (1 << i)) { 1274 valid_version = i; 1275 break; 1276 } 1277 } 1278 ATAPRT(( 1279 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1280 valid_version, 1281 aidp->ai_majorversion, 1282 aidp->ai_minorversion)); 1283 } 1284 1285 if (ata_capability_data) { 1286 1287 ATAPRT(("?\t\tstat %x, err %x\n", 1288 ddi_get8(ata_ctlp->ac_iohandle2, 1289 ata_ctlp->ac_altstatus), 1290 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1291 1292 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1293 aidp->ai_config, 1294 aidp->ai_cap)); 1295 1296 /* 1297 * Be aware that ATA-6 and later drives may not provide valid 1298 * geometry information and other obsoleted info. 1299 * Select what is printed based on supported ATA model (skip 1300 * anything below ATA/ATAPI-3) 1301 */ 1302 1303 if (valid_version == 0 || aidp->ai_majorversion < 1304 ATAC_MAJVER_6) { 1305 /* 1306 * Supported version less then ATA-6 1307 */ 1308 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1309 aidp->ai_fixcyls, 1310 aidp->ai_heads, 1311 aidp->ai_sectors)); 1312 } 1313 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1314 aidp->ai_mult1, 1315 aidp->ai_mult2)); 1316 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1317 ATAPRT(( 1318 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1319 aidp->ai_piomode, 1320 aidp->ai_dmamode, 1321 aidp->ai_advpiomode)); 1322 } else { 1323 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1324 aidp->ai_advpiomode)); 1325 } 1326 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1327 aidp->ai_minpio, 1328 aidp->ai_minpioflow)); 1329 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1330 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1331 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1332 aidp->ai_dworddma, 1333 aidp->ai_ultradma)); 1334 } else { 1335 ATAPRT(("?\t\tdwdma 0x%x\n", 1336 aidp->ai_dworddma)); 1337 } 1338 } 1339 1340 if (ATAPIDRV(ata_drvp)) { 1341 if (!atapi_init_drive(ata_drvp)) 1342 goto errout; 1343 } else { 1344 if (!ata_disk_init_drive(ata_drvp)) 1345 goto errout; 1346 } 1347 1348 /* 1349 * store pointer in controller struct 1350 */ 1351 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1352 1353 /* 1354 * lock the drive's current settings in case I have to 1355 * reset the drive due to some sort of error 1356 */ 1357 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 1358 1359 return (ata_drvp); 1360 1361errout: 1362 ata_uninit_drive(ata_drvp); 1363 return (NULL); 1364} 1365 1366/* destroy a drive */ 1367 1368static void 1369ata_uninit_drive( 1370 ata_drv_t *ata_drvp) 1371{ 1372#if 0 1373 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1374#endif 1375 1376 ADBG_TRACE(("ata_uninit_drive entered\n")); 1377 1378#if 0 1379 /* 1380 * DON'T DO THIS. disabling interrupts floats the IRQ line 1381 * which generates spurious interrupts 1382 */ 1383 1384 /* 1385 * Select the correct drive 1386 */ 1387 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1388 ata_drvp->ad_drive_bits); 1389 ata_nsecwait(400); 1390 1391 /* 1392 * Disable interrupts from the drive 1393 */ 1394 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1395 (ATDC_D3 | ATDC_NIEN)); 1396#endif 1397 1398 /* interface specific clean-ups */ 1399 1400 if (ata_drvp->ad_flags & AD_ATAPI) 1401 atapi_uninit_drive(ata_drvp); 1402 else if (ata_drvp->ad_flags & AD_DISK) 1403 ata_disk_uninit_drive(ata_drvp); 1404 1405 /* free drive struct */ 1406 1407 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1408} 1409 1410 1411/* 1412 * ata_drive_type() 1413 * 1414 * The timeout values and exact sequence of checking is critical 1415 * especially for atapi device detection, and should not be changed lightly. 1416 * 1417 */ 1418static int 1419ata_drive_type( 1420 uchar_t drvhd, 1421 ddi_acc_handle_t io_hdl1, 1422 caddr_t ioaddr1, 1423 ddi_acc_handle_t io_hdl2, 1424 caddr_t ioaddr2, 1425 struct ata_id *ata_id_bufp) 1426{ 1427 uchar_t status; 1428 1429 ADBG_TRACE(("ata_drive_type entered\n")); 1430 1431 /* 1432 * select the appropriate drive and LUN 1433 */ 1434 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1435 ata_nsecwait(400); 1436 1437 /* 1438 * make certain the drive is selected, and wait for not busy 1439 */ 1440 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1441 5 * 1000000); 1442 1443 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1444 1445 if (status & ATS_BSY) { 1446 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1447 return (ATA_DEV_NONE); 1448 } 1449 1450 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1451 return (ATA_DEV_DISK); 1452 1453 /* 1454 * No disk, check for atapi unit. 1455 */ 1456 if (!atapi_signature(io_hdl1, ioaddr1)) { 1457#ifndef ATA_DISABLE_ATAPI_1_7 1458 /* 1459 * Check for old (but prevalent) atapi 1.7B 1460 * spec device, the only known example is the 1461 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1462 * compliant). This device has no signature 1463 * and requires conversion from hex to BCD 1464 * for some scsi audio commands. 1465 */ 1466 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1467 return (ATA_DEV_ATAPI); 1468 } 1469#endif 1470 return (ATA_DEV_NONE); 1471 } 1472 1473 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1474 return (ATA_DEV_ATAPI); 1475 } 1476 1477 return (ATA_DEV_NONE); 1478 1479} 1480 1481/* 1482 * nsec-granularity time delay function 1483 */ 1484void 1485ata_nsecwait(clock_t count) 1486{ 1487 extern int tsc_gethrtime_initted; 1488 1489 if (tsc_gethrtime_initted) { 1490 hrtime_t end = gethrtime() + count; 1491 1492 while (gethrtime() < end) { 1493 SMT_PAUSE(); 1494 } 1495 } else { 1496 drv_usecwait(1 + (count / 1000)); 1497 } 1498} 1499 1500 1501/* 1502 * Wait for a register of a controller to achieve a specific state. 1503 * To return normally, all the bits in the first sub-mask must be ON, 1504 * all the bits in the second sub-mask must be OFF. 1505 * If timeout_usec microseconds pass without the controller achieving 1506 * the desired bit configuration, we return TRUE, else FALSE. 1507 */ 1508 1509int ata_usec_delay = 10; 1510 1511int 1512ata_wait( 1513 ddi_acc_handle_t io_hdl, 1514 caddr_t ioaddr, 1515 uchar_t onbits, 1516 uchar_t offbits, 1517 uint_t timeout_usec) 1518{ 1519 ushort_t val; 1520 hrtime_t deadline = gethrtime() + 1521 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1522 1523 1524 do { 1525 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1526 if ((val & onbits) == onbits && (val & offbits) == 0) 1527 return (TRUE); 1528 drv_usecwait(ata_usec_delay); 1529 } while (gethrtime() < deadline); 1530 1531 return (FALSE); 1532} 1533 1534 1535/* 1536 * 1537 * This is a slightly more complicated version that checks 1538 * for error conditions and bails-out rather than looping 1539 * until the timeout expires 1540 */ 1541int 1542ata_wait3( 1543 ddi_acc_handle_t io_hdl, 1544 caddr_t ioaddr, 1545 uchar_t onbits1, 1546 uchar_t offbits1, 1547 uchar_t failure_onbits2, 1548 uchar_t failure_offbits2, 1549 uchar_t failure_onbits3, 1550 uchar_t failure_offbits3, 1551 uint_t timeout_usec) 1552{ 1553 ushort_t val; 1554 hrtime_t deadline = gethrtime() + 1555 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1556 1557 do { 1558 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1559 1560 /* 1561 * check for expected condition 1562 */ 1563 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1564 return (TRUE); 1565 1566 /* 1567 * check for error conditions 1568 */ 1569 if ((val & failure_onbits2) == failure_onbits2 && 1570 (val & failure_offbits2) == 0) { 1571 return (FALSE); 1572 } 1573 1574 if ((val & failure_onbits3) == failure_onbits3 && 1575 (val & failure_offbits3) == 0) { 1576 return (FALSE); 1577 } 1578 1579 drv_usecwait(ata_usec_delay); 1580 } while (gethrtime() < deadline); 1581 1582 return (FALSE); 1583} 1584 1585 1586/* 1587 * 1588 * low level routine for ata_disk_id() and atapi_id() 1589 * 1590 */ 1591 1592int 1593ata_id_common( 1594 uchar_t id_cmd, 1595 int expect_drdy, 1596 ddi_acc_handle_t io_hdl1, 1597 caddr_t ioaddr1, 1598 ddi_acc_handle_t io_hdl2, 1599 caddr_t ioaddr2, 1600 struct ata_id *aidp) 1601{ 1602 uchar_t status; 1603 1604 ADBG_TRACE(("ata_id_common entered\n")); 1605 1606 bzero(aidp, sizeof (struct ata_id)); 1607 1608 /* 1609 * clear the features register 1610 */ 1611 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1612 1613 /* 1614 * Disable interrupts from the device. When the ata 1615 * hardware is sharing its interrupt with another 1616 * device, the shared interrupt might have already been 1617 * unmasked in the interrupt controller and 1618 * triggering ata device interrupts will result in an 1619 * interrupt storm and a hung system. 1620 */ 1621 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1622 1623 /* 1624 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1625 */ 1626 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1627 1628 /* wait for the busy bit to settle */ 1629 ata_nsecwait(400); 1630 1631 /* 1632 * read alternate status and check for conditions which 1633 * may indicate the drive is not present, to prevent getting 1634 * stuck in ata_wait3() below. 1635 */ 1636 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1637 1638 /* 1639 * 0x0, 0x7f, or ATS_DF can happen when no drive is present 1640 */ 1641 if ((status == 0x0) || (status == 0x7f) || 1642 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) { 1643 /* invalid status, can't be an ATA or ATAPI device */ 1644 return (FALSE); 1645 } 1646 1647 /* 1648 * According to the ATA specification, some drives may have 1649 * to read the media to complete this command. We need to 1650 * make sure we give them enough time to respond. 1651 */ 1652 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1653 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1654 1655 /* 1656 * read the status byte and clear the pending interrupt 1657 */ 1658 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS); 1659 1660 /* 1661 * this happens if there's no drive present 1662 */ 1663 if (status == 0xff || status == 0x7f) { 1664 /* invalid status, can't be an ATA or ATAPI device */ 1665 return (FALSE); 1666 } 1667 1668 if (status & ATS_BSY) { 1669 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1670 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1671 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1672 return (FALSE); 1673 } 1674 1675 if (!(status & ATS_DRQ)) { 1676 if (status & (ATS_ERR | ATS_DF)) { 1677 return (FALSE); 1678 } 1679 /* 1680 * Give the drive another second to assert DRQ. Some older 1681 * drives de-assert BSY before asserting DRQ. Bail out 1682 * immediately if the status becomes 0x7f, which is invalid 1683 * value. It can happen when no drive is present. 1684 */ 1685 if (!ata_wait3(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 0x7f, 1686 ATS_BSY, 0x7f, ATS_BSY, 1000000)) { 1687 ADBG_WARN(("ata_id_common: " 1688 "!DRQ status 0x%x error 0x%x\n", 1689 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1690 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1691 return (FALSE); 1692 } 1693 } 1694 1695 /* 1696 * transfer the data 1697 */ 1698 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1699 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1700 1701 /* wait for the busy bit to settle */ 1702 ata_nsecwait(400); 1703 1704 1705 /* 1706 * Wait for the drive to recognize I've read all the data. 1707 * Some drives have been observed to take as much as 3msec to 1708 * deassert DRQ after reading the data; allow 1 sec just in case. 1709 * 1710 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1711 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1712 * safely ignore the DRDY bit since the ATAPI Packet command 1713 * actually doesn't require it to ever be asserted. 1714 * 1715 * Bail out immediately if the status becomes 0x7f, which is invalid 1716 * value. It can happen when no drive is present. 1717 * 1718 */ 1719 if (!ata_wait3(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1720 (ATS_BSY | ATS_DRQ), 0x7f, ATS_BSY, 0x7f, ATS_BSY, 1000000)) { 1721 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1722 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1723 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1724 return (FALSE); 1725 } 1726 1727 /* 1728 * Check to see if the command aborted. This happens if 1729 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1730 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1731 * (non-PACKET) device. 1732 */ 1733 if (status & (ATS_DF | ATS_ERR)) { 1734 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1735 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1736 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1737 return (FALSE); 1738 } 1739 return (TRUE); 1740} 1741 1742 1743/* 1744 * Low level routine to issue a non-data command and busy wait for 1745 * the completion status. 1746 */ 1747 1748int 1749ata_command( 1750 ata_ctl_t *ata_ctlp, 1751 ata_drv_t *ata_drvp, 1752 int expect_drdy, 1753 int silent, 1754 uint_t busy_wait, 1755 uchar_t cmd, 1756 uchar_t feature, 1757 uchar_t count, 1758 uchar_t sector, 1759 uchar_t head, 1760 uchar_t cyl_low, 1761 uchar_t cyl_hi) 1762{ 1763 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1764 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1765 uchar_t status; 1766 1767 /* select the drive */ 1768 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1769 ata_nsecwait(400); 1770 1771 /* make certain the drive selected */ 1772 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1773 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1774 ATS_BSY, busy_wait)) { 1775 ADBG_ERROR(("ata_command: select failed " 1776 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1777 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1778 expect_drdy, cmd, feature, count, 1779 sector, head, cyl_low, cyl_hi)); 1780 return (FALSE); 1781 } 1782 1783 /* 1784 * set all the regs 1785 */ 1786 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1787 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1788 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1789 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1790 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1791 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1792 1793 /* send the command */ 1794 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1795 1796 /* wait for the busy bit to settle */ 1797 ata_nsecwait(400); 1798 1799 /* wait for not busy */ 1800 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1801 ADBG_ERROR(("ata_command: BSY too long!" 1802 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1803 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1804 expect_drdy, cmd, feature, count, 1805 sector, head, cyl_low, cyl_hi)); 1806 return (FALSE); 1807 } 1808 1809 /* 1810 * wait for DRDY before continuing 1811 */ 1812 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1813 ATS_DRDY, ATS_BSY, /* okay */ 1814 ATS_ERR, ATS_BSY, /* cmd failed */ 1815 ATS_DF, ATS_BSY, /* drive failed */ 1816 busy_wait); 1817 1818 /* read status to clear IRQ, and check for error */ 1819 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1820 1821 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1822 return (TRUE); 1823 1824 if (!silent) { 1825 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1826 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1827 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1828 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1829 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1830 expect_drdy, cmd, feature, count, 1831 sector, head, cyl_low, cyl_hi)); 1832 } 1833 return (FALSE); 1834} 1835 1836 1837 1838/* 1839 * 1840 * Issue a SET FEATURES command 1841 * 1842 */ 1843 1844int 1845ata_set_feature( 1846 ata_ctl_t *ata_ctlp, 1847 ata_drv_t *ata_drvp, 1848 uchar_t feature, 1849 uchar_t value) 1850{ 1851 int rc; 1852 1853 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1854 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1855 /* feature, count, sector, head, cyl_low, cyl_hi */ 1856 1857 if (rc) { 1858 return (TRUE); 1859 } 1860 1861 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1862 return (FALSE); 1863} 1864 1865 1866 1867/* 1868 * 1869 * Issue a FLUSH CACHE command 1870 * 1871 */ 1872 1873static int 1874ata_flush_cache( 1875 ata_ctl_t *ata_ctlp, 1876 ata_drv_t *ata_drvp) 1877{ 1878 /* this command is optional so fail silently */ 1879 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1880 ata_flush_cache_wait, 1881 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1882} 1883 1884/* 1885 * ata_setup_ioaddr() 1886 * 1887 * Map the device registers and return the handles. 1888 * 1889 * If this is a ISA-ATA controller then only two handles are 1890 * initialized and returned. 1891 * 1892 * If this is a PCI-IDE controller than a third handle (for the 1893 * PCI-IDE Bus Mastering registers) is initialized and returned. 1894 * 1895 */ 1896 1897static int 1898ata_setup_ioaddr( 1899 dev_info_t *dip, 1900 ddi_acc_handle_t *handle1p, 1901 caddr_t *addr1p, 1902 ddi_acc_handle_t *handle2p, 1903 caddr_t *addr2p, 1904 ddi_acc_handle_t *bm_hdlp, 1905 caddr_t *bm_addrp) 1906{ 1907 ddi_device_acc_attr_t dev_attr; 1908 int rnumber; 1909 int rc; 1910 off_t regsize; 1911 1912 /* 1913 * Make certain the controller is enabled and its regs are map-able 1914 * 1915 */ 1916 rc = ddi_dev_regsize(dip, 0, ®size); 1917 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1918 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1919 rc, (long long)regsize)); 1920 return (FALSE); 1921 } 1922 1923 rc = ddi_dev_regsize(dip, 1, ®size); 1924 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1925 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1926 rc, (long long)regsize)); 1927 return (FALSE); 1928 } 1929 1930 /* 1931 * setup the device attribute structure for little-endian, 1932 * strict ordering access. 1933 */ 1934 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1935 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1936 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1937 1938 *handle1p = NULL; 1939 *handle2p = NULL; 1940 *bm_hdlp = NULL; 1941 1942 /* 1943 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1944 */ 1945 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1946 /* it's PNP-ISA, skip over the extra reg tuple */ 1947 rnumber = 1; 1948 goto not_pciide; 1949 } 1950 1951 /* else, it's ISA or PCI-IDE, check further */ 1952 rnumber = 0; 1953 1954 if (!ata_is_pci(dip)) { 1955 /* 1956 * If it's not a PCI-IDE, there are only two reg tuples 1957 * and the first one contains the I/O base (170 or 1f0) 1958 * rather than the controller instance number. 1959 */ 1960 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1961 goto not_pciide; 1962 } 1963 1964 1965 /* 1966 * Map the correct half of the PCI-IDE Bus Master registers. 1967 * There's a single BAR that maps these registers for both 1968 * controller's in a dual-controller chip and it's upto my 1969 * parent nexus, pciide, to adjust which (based on my instance 1970 * number) half this call maps. 1971 */ 1972 rc = ddi_dev_regsize(dip, 2, ®size); 1973 if (rc != DDI_SUCCESS || regsize < 8) { 1974 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1975 rc, (long long)regsize)); 1976 goto not_pciide; 1977 } 1978 1979 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1980 1981 if (rc != DDI_SUCCESS) { 1982 /* map failed, try to use in non-pci-ide mode */ 1983 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1984 rc)); 1985 *bm_hdlp = NULL; 1986 } 1987 1988not_pciide: 1989 /* 1990 * map the lower command block registers 1991 */ 1992 1993 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1994 handle1p); 1995 1996 if (rc != DDI_SUCCESS) { 1997 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1998 goto out1; 1999 } 2000 2001 /* 2002 * If the controller is being used in compatibility mode 2003 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 2004 * will specify zeros for the I/O ports for the PCI 2005 * instance. 2006 */ 2007 if (*addr1p == 0) { 2008 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 2009 goto out2; 2010 } 2011 2012 /* 2013 * map the upper control block registers 2014 */ 2015 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 2016 handle2p); 2017 if (rc == DDI_SUCCESS) 2018 return (TRUE); 2019 2020 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 2021 2022out2: 2023 if (*handle1p != NULL) { 2024 ddi_regs_map_free(handle1p); 2025 *handle1p = NULL; 2026 } 2027 2028out1: 2029 if (*bm_hdlp != NULL) { 2030 ddi_regs_map_free(bm_hdlp); 2031 *bm_hdlp = NULL; 2032 } 2033 return (FALSE); 2034 2035} 2036 2037/* 2038 * 2039 * Currently, the only supported controllers are ones which 2040 * support the SFF-8038 Bus Mastering spec. 2041 * 2042 * Check the parent node's IEEE 1275 class-code property to 2043 * determine if it's an PCI-IDE instance which supports SFF-8038 2044 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 2045 * that doesn't do Bus Mastering. In that case, my interrupt handler 2046 * only uses the interrupt latch bit in PCI-IDE status register. 2047 * The assumption is that the programming interface byte of the 2048 * class-code property reflects the bus master DMA capability of 2049 * the controller. 2050 * 2051 * Whether the drive support supports the DMA option still needs 2052 * to be checked later. Each individual request also has to be 2053 * checked for alignment and size to decide whether to use the 2054 * DMA transfer mode. 2055 */ 2056 2057static void 2058ata_init_pciide( 2059 dev_info_t *dip, 2060 ata_ctl_t *ata_ctlp) 2061{ 2062 uint_t class_code; 2063 uchar_t status; 2064 2065 ata_cntrl_DMA_sel_msg = NULL; 2066 2067 if (ata_ctlp->ac_bmhandle == NULL) { 2068 ata_ctlp->ac_pciide = FALSE; 2069 ata_ctlp->ac_pciide_bm = FALSE; 2070 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2071 return; 2072 } 2073 2074 /* 2075 * check if it's a known bogus PCI-IDE chip 2076 */ 2077 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2078 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2079 ata_ctlp->ac_pciide = FALSE; 2080 ata_ctlp->ac_pciide_bm = FALSE; 2081 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2082 return; 2083 } 2084 ata_ctlp->ac_pciide = TRUE; 2085 2086 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2087 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2088 } 2089 2090 /* 2091 * check for a PCI-IDE chip with a broken DMA engine 2092 */ 2093 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2094 ata_ctlp->ac_pciide_bm = FALSE; 2095 ata_cntrl_DMA_sel_msg = 2096 "cntrl blacklisted/DMA engine broken"; 2097 return; 2098 } 2099 2100 /* 2101 * Check the Programming Interface register to determine 2102 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2103 * devices don't support Bus Mastering or DMA. 2104 * Since we are dealing with pre-qualified pci-ide controller, 2105 * check programming interface byte only. 2106 */ 2107 2108 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2109 DDI_PROP_DONTPASS, "class-code", 0); 2110 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2111 ata_ctlp->ac_pciide_bm = FALSE; 2112 ata_cntrl_DMA_sel_msg = 2113 "cntrl not Bus Master DMA capable"; 2114 return; 2115 } 2116 2117 /* 2118 * Avoid doing DMA on "simplex" chips which share hardware 2119 * between channels 2120 */ 2121 status = ddi_get8(ata_ctlp->ac_bmhandle, 2122 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2123 /* 2124 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2125 * In such a mode, the simplex bit is asserted, but in fact testing 2126 * on such a motherboard has shown that the devices are not simplex 2127 * -- DMA can be used on both channels concurrently with no special 2128 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2129 * flag set to indicate that the value of the simplex bit can be 2130 * ignored. 2131 */ 2132 2133 if (status & PCIIDE_BMISX_SIMPLEX) { 2134 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2135 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2136 2137 } else { 2138 2139 int simplex_dma_channel, *rp, proplen, channel; 2140 int dma_on = FALSE; 2141 2142 /* 2143 * By default,use DMA on channel 0 and PIO on channel 2144 * 1. This can be switched by setting 2145 * ata-simplex-dma-channel to: 2146 * 0 DMA on channel 0 (default without this 2147 * property) 2148 * 1 DMA on channel 1 2149 * any other value: DMA off on both channels. 2150 */ 2151 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2152 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2153 2154 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2155 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2156 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2157 2158 channel = *rp; 2159 ddi_prop_free(rp); 2160 2161 if (simplex_dma_channel == channel) { 2162 cmn_err(CE_CONT, "?ata: simplex " 2163 "controller. DMA on channel" 2164 " %d PIO on channel %d", 2165 channel, channel ? 0:1); 2166 dma_on = TRUE; 2167 } else { 2168 ata_cntrl_DMA_sel_msg = 2169 "simplex controller"; 2170 } 2171 } 2172 2173 if (dma_on == FALSE) { 2174 ata_ctlp->ac_pciide_bm = FALSE; 2175 2176 return; 2177 } 2178 } 2179 } 2180 2181 /* 2182 * It's a compatible PCI-IDE Bus Mastering controller, 2183 * allocate and map the DMA Scatter/Gather list (PRDE table). 2184 */ 2185 if (ata_pciide_alloc(dip, ata_ctlp)) 2186 ata_ctlp->ac_pciide_bm = TRUE; 2187 else { 2188 ata_ctlp->ac_pciide_bm = FALSE; 2189 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2190 } 2191} 2192 2193/* 2194 * 2195 * Determine whether to enable DMA support for this drive. 2196 * The controller and the drive both have to support DMA. 2197 * The controller's capabilities were already checked in 2198 * ata_init_pciide(), now just check the drive's capabilities. 2199 * 2200 */ 2201 2202static int 2203ata_init_drive_pcidma( 2204 ata_ctl_t *ata_ctlp, 2205 ata_drv_t *ata_drvp, 2206 dev_info_t *tdip) 2207{ 2208 boolean_t dma; 2209 boolean_t cd_dma; 2210 boolean_t disk_dma; 2211 boolean_t atapi_dma; 2212 int ata_options; 2213 2214 ata_dev_DMA_sel_msg = NULL; 2215 2216 if (ata_ctlp->ac_pciide_bm != TRUE) { 2217 ata_dev_DMA_sel_msg = 2218 "controller is not Bus Master capable"; 2219 2220 return (ATA_DMA_OFF); 2221 } 2222 2223 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2224 0, "ata-options", 0); 2225 2226 if (!(ata_options & ATA_OPTIONS_DMA)) { 2227 /* 2228 * Either the ata-options property was not found or 2229 * DMA is not enabled by this property 2230 */ 2231 ata_dev_DMA_sel_msg = 2232 "disabled by \"ata-options\" property"; 2233 2234 return (ATA_DMA_OFF); 2235 } 2236 2237 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2238 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2239 2240 return (ATA_DMA_OFF); 2241 } 2242 2243 /* 2244 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2245 * optional on ATA-2 (or older) drives. 2246 * 2247 * On ATA-2 drives the ai_majorversion word will probably 2248 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2249 * the capabilities word instead. The order of these tests 2250 * is important since an ATA-3 drive doesn't have to set 2251 * the DMA bit in the capabilities word. 2252 * 2253 */ 2254 2255 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2256 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2257 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2258 ata_dev_DMA_sel_msg = "device not DMA capable"; 2259 2260 return (ATA_DMA_OFF); 2261 } 2262 2263 /* 2264 * Disable DMA for ATAPI devices on controllers known to 2265 * have trouble with ATAPI DMA 2266 */ 2267 2268 if (ATAPIDRV(ata_drvp)) { 2269 if (ata_check_pciide_blacklist(ata_ctlp->ac_dip, 2270 ATA_BL_ATAPI_NODMA)) { 2271 ata_dev_DMA_sel_msg = 2272 "controller incapable of DMA for ATAPI device"; 2273 2274 return (ATA_DMA_OFF); 2275 } 2276 } 2277 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2278 0, "ata-dma-enabled", TRUE); 2279 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2280 0, "ata-disk-dma-enabled", TRUE); 2281 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2282 0, "atapi-cd-dma-enabled", FALSE); 2283 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2284 0, "atapi-other-dma-enabled", TRUE); 2285 2286 if (dma == FALSE) { 2287 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2288 "DMA disabled by \"ata-dma-enabled\" property"); 2289 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2290 2291 return (ATA_DMA_OFF); 2292 } 2293 2294 if (IS_CDROM(ata_drvp) == TRUE) { 2295 if (cd_dma == FALSE) { 2296 ata_dev_DMA_sel_msg = 2297 "disabled. Control with \"atapi-cd-dma-enabled\"" 2298 " property"; 2299 2300 return (ATA_DMA_OFF); 2301 } 2302 2303 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2304 if (disk_dma == FALSE) { 2305 ata_dev_DMA_sel_msg = 2306 "disabled by \"ata-disk-dma-enabled\" property"; 2307 2308 return (ATA_DMA_OFF); 2309 } 2310 2311 } else if (atapi_dma == FALSE) { 2312 ata_dev_DMA_sel_msg = 2313 "disabled by \"atapi-other-dma-enabled\" property"; 2314 2315 return (ATA_DMA_OFF); 2316 } 2317 2318 return (ATA_DMA_ON); 2319} 2320 2321 2322 2323/* 2324 * this compare routine squeezes out extra blanks and 2325 * returns TRUE if p1 matches the leftmost substring of p2 2326 */ 2327 2328static int 2329ata_strncmp( 2330 char *p1, 2331 char *p2, 2332 int cnt) 2333{ 2334 2335 for (;;) { 2336 /* 2337 * skip over any extra blanks in both strings 2338 */ 2339 while (*p1 != '\0' && *p1 == ' ') 2340 p1++; 2341 2342 while (cnt != 0 && *p2 == ' ') { 2343 p2++; 2344 cnt--; 2345 } 2346 2347 /* 2348 * compare the two strings 2349 */ 2350 2351 if (cnt == 0 || *p1 != *p2) 2352 break; 2353 2354 while (cnt > 0 && *p1 == *p2) { 2355 p1++; 2356 p2++; 2357 cnt--; 2358 } 2359 2360 } 2361 2362 /* return TRUE if both strings ended at same point */ 2363 return ((*p1 == '\0') ? TRUE : FALSE); 2364} 2365 2366/* 2367 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2368 * on the target's dev_info node. Currently, the sd target driver 2369 * is the only driver which refers to this property. 2370 * 2371 * If the flag ata_id_debug is set also create the 2372 * the "ata" or "atapi" property on the target's dev_info node 2373 * 2374 */ 2375 2376int 2377ata_prop_create( 2378 dev_info_t *tgt_dip, 2379 ata_drv_t *ata_drvp, 2380 char *name) 2381{ 2382 int rc; 2383 2384 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2385 2386 if (strcmp("atapi", name) == 0) { 2387 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2388 "variant", name); 2389 if (rc != DDI_PROP_SUCCESS) 2390 return (FALSE); 2391 } 2392 2393 if (!ata_id_debug) 2394 return (TRUE); 2395 2396 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2397 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2398 if (rc != DDI_PROP_SUCCESS) { 2399 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2400 } 2401 return (TRUE); 2402} 2403 2404 2405/* *********************************************************************** */ 2406/* *********************************************************************** */ 2407/* *********************************************************************** */ 2408 2409/* 2410 * This state machine doesn't implement the ATAPI Optional Overlap 2411 * feature. You need that feature to efficiently support ATAPI 2412 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2413 * for an example of how to add the necessary additional NextActions 2414 * and NextStates to this FSM and the atapi_fsm, in order to support 2415 * the Overlap Feature. 2416 */ 2417 2418 2419uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2420/* --------------------- next action --------------------- | - current - */ 2421/* start0 --- start1 ---- intr ------ fini --- reset --- */ 2422{ AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2423{ AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2424{ AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2425}; 2426 2427uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2428 2429/* --------------------- next state --------------------- | - current - */ 2430/* start0 --- start1 ---- intr ------ fini --- reset --- */ 2431{ AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2432{ AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2433{ AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2434}; 2435 2436 2437static int 2438ata_ctlr_fsm( 2439 uchar_t fsm_func, 2440 ata_ctl_t *ata_ctlp, 2441 ata_drv_t *ata_drvp, 2442 ata_pkt_t *ata_pktp, 2443 int *DoneFlgp) 2444{ 2445 uchar_t action; 2446 uchar_t current_state; 2447 uchar_t next_state; 2448 int rc; 2449 2450 current_state = ata_ctlp->ac_state; 2451 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2452 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2453 2454 /* 2455 * Set the controller's new state 2456 */ 2457 ata_ctlp->ac_state = next_state; 2458 switch (action) { 2459 2460 case AC_BUSY: 2461 return (ATA_FSM_RC_BUSY); 2462 2463 case AC_NADA: 2464 return (ATA_FSM_RC_OKAY); 2465 2466 case AC_START: 2467 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2468 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2469 2470 ata_ctlp->ac_active_pktp = ata_pktp; 2471 ata_ctlp->ac_active_drvp = ata_drvp; 2472 2473 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2474 2475 if (rc == ATA_FSM_RC_BUSY) { 2476 /* the request didn't start, GHD will requeue it */ 2477 ata_ctlp->ac_state = AS_IDLE; 2478 ata_ctlp->ac_active_pktp = NULL; 2479 ata_ctlp->ac_active_drvp = NULL; 2480 } 2481 return (rc); 2482 2483 case AC_INTR: 2484 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2485 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2486 2487 ata_drvp = ata_ctlp->ac_active_drvp; 2488 ata_pktp = ata_ctlp->ac_active_pktp; 2489 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2490 2491 case AC_RESET_A: /* Reset, controller active */ 2492 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2493 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2494 2495 /* clean up the active request */ 2496 ata_pktp = ata_ctlp->ac_active_pktp; 2497 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2498 2499 /* halt the DMA engine */ 2500 if (ata_pktp->ap_pciide_dma) { 2501 ata_pciide_dma_stop(ata_ctlp); 2502 (void) ata_pciide_status_clear(ata_ctlp); 2503 } 2504 2505 /* Do a Software Reset to unwedge the bus */ 2506 if (!ata_software_reset(ata_ctlp)) { 2507 return (ATA_FSM_RC_BUSY); 2508 } 2509 2510 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2511 atapi_fsm_reset(ata_ctlp); 2512 return (ATA_FSM_RC_FINI); 2513 2514 case AC_RESET_I: /* Reset, controller idle */ 2515 /* Do a Software Reset to unwedge the bus */ 2516 if (!ata_software_reset(ata_ctlp)) { 2517 return (ATA_FSM_RC_BUSY); 2518 } 2519 2520 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2521 atapi_fsm_reset(ata_ctlp); 2522 return (ATA_FSM_RC_OKAY); 2523 2524 case AC_FINI: 2525 break; 2526 } 2527 2528 /* 2529 * AC_FINI, check ARQ needs to be started or finished 2530 */ 2531 2532 ASSERT(action == AC_FINI); 2533 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2534 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2535 2536 /* 2537 * The active request is done now. 2538 * Disconnect the request from the controller and 2539 * add it to the done queue. 2540 */ 2541 ata_drvp = ata_ctlp->ac_active_drvp; 2542 ata_pktp = ata_ctlp->ac_active_pktp; 2543 2544 /* 2545 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2546 */ 2547 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2548 ata_pkt_t *arq_pktp; 2549 2550 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2551 2552 arq_pktp = ata_pktp; 2553 ata_pktp = ata_ctlp->ac_fault_pktp; 2554 ata_ctlp->ac_fault_pktp = NULL; 2555 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2556 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2557 else 2558 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2559 goto all_done; 2560 } 2561 2562 2563#define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2564 2565 /* 2566 * Start ARQ pkt if necessary 2567 */ 2568 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2569 (ata_pktp->ap_status & ATS_ERR)) { 2570 2571 /* set controller state back to active */ 2572 ata_ctlp->ac_state = current_state; 2573 2574 /* try to start the ARQ pkt */ 2575 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2576 2577 if (rc == ATA_FSM_RC_BUSY) { 2578 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2579 /* let the target driver handle the problem */ 2580 ata_ctlp->ac_state = AS_IDLE; 2581 ata_ctlp->ac_active_pktp = NULL; 2582 ata_ctlp->ac_active_drvp = NULL; 2583 ata_ctlp->ac_fault_pktp = NULL; 2584 goto all_done; 2585 } 2586 2587 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2588 return (rc); 2589 } 2590 2591 /* 2592 * Normal completion, no error status, and not an ARQ pkt, 2593 * just fall through. 2594 */ 2595 2596all_done: 2597 2598 /* 2599 * wrap everything up and tie a ribbon around it 2600 */ 2601 ata_ctlp->ac_active_pktp = NULL; 2602 ata_ctlp->ac_active_drvp = NULL; 2603 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2604 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2605 if (DoneFlgp) 2606 *DoneFlgp = TRUE; 2607 } 2608 2609 return (ATA_FSM_RC_OKAY); 2610} 2611 2612 2613static int 2614ata_start_arq( 2615 ata_ctl_t *ata_ctlp, 2616 ata_drv_t *ata_drvp, 2617 ata_pkt_t *ata_pktp) 2618{ 2619 ata_pkt_t *arq_pktp; 2620 int bytes; 2621 uint_t senselen; 2622 2623 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2624 2625 /* 2626 * Determine just the size of the Request Sense Data buffer within 2627 * the scsi_arq_status structure. 2628 */ 2629#define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2630 - sizeof (struct scsi_extended_sense)) 2631 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2632 ASSERT(senselen > 0); 2633 2634 2635 /* save ptr to original pkt */ 2636 ata_ctlp->ac_fault_pktp = ata_pktp; 2637 2638 /* switch the controller's active pkt to the ARQ pkt */ 2639 arq_pktp = ata_ctlp->ac_arq_pktp; 2640 ata_ctlp->ac_active_pktp = arq_pktp; 2641 2642 /* finish initializing the ARQ CDB */ 2643 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2644 ata_ctlp->ac_arq_cdb[4] = (uchar_t)senselen; 2645 2646 /* finish initializing the ARQ pkt */ 2647 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2648 2649 arq_pktp->ap_resid = senselen; 2650 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2651 arq_pktp->ap_cdb_pad = 2652 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2653 2654 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2655 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2656 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2657 2658 /* 2659 * This packet is shared by all drives on this controller 2660 * therefore we need to init the drive number on every ARQ. 2661 */ 2662 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2663 2664 /* start it up */ 2665 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2666} 2667 2668/* 2669 * 2670 * reset the bus 2671 * 2672 */ 2673 2674static int 2675ata_reset_bus( 2676 ata_ctl_t *ata_ctlp) 2677{ 2678 int watchdog; 2679 uchar_t drive; 2680 int rc = FALSE; 2681 uchar_t fsm_func; 2682 int DoneFlg = FALSE; 2683 2684 /* 2685 * Do a Software Reset to unwedge the bus, and send 2686 * ATAPI DEVICE RESET to each ATAPI drive. 2687 */ 2688 fsm_func = ATA_FSM_RESET; 2689 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2690 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2691 &DoneFlg)) { 2692 case ATA_FSM_RC_OKAY: 2693 rc = TRUE; 2694 goto fsm_done; 2695 2696 case ATA_FSM_RC_BUSY: 2697 return (FALSE); 2698 2699 case ATA_FSM_RC_INTR: 2700 fsm_func = ATA_FSM_INTR; 2701 rc = TRUE; 2702 continue; 2703 2704 case ATA_FSM_RC_FINI: 2705 fsm_func = ATA_FSM_FINI; 2706 rc = TRUE; 2707 continue; 2708 } 2709 } 2710 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2711 2712fsm_done: 2713 2714 /* 2715 * Reinitialize the ATA drives 2716 */ 2717 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2718 ata_drv_t *ata_drvp; 2719 2720 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2721 continue; 2722 2723 if (ATAPIDRV(ata_drvp)) 2724 continue; 2725 2726 /* 2727 * Reprogram the Read/Write Multiple block factor 2728 * and current geometry into the drive. 2729 */ 2730 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2731 rc = FALSE; 2732 } 2733 2734 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2735 /* has been already called. In this case ignore any errors and */ 2736 /* return TRUE to the caller, otherwise return the value of rc */ 2737 /* to the caller */ 2738 if (DoneFlg) 2739 return (TRUE); 2740 else 2741 return (rc); 2742} 2743 2744 2745/* 2746 * 2747 * Low level routine to toggle the Software Reset bit 2748 * 2749 */ 2750 2751static int 2752ata_software_reset( 2753 ata_ctl_t *ata_ctlp) 2754{ 2755 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2756 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2757 hrtime_t deadline; 2758 uint_t usecs_left; 2759 2760 ADBG_TRACE(("ata_reset_bus entered\n")); 2761 2762 /* disable interrupts and turn the software reset bit on */ 2763 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2764 2765 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2766 drv_usecwait(30000); 2767 2768 /* turn the software reset bit back off */ 2769 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2770 2771 /* 2772 * Wait for the controller to assert BUSY status. 2773 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2774 * spec says 400 nsecs, (and 2 msecs if device 2775 * was in sleep mode; but we don't put drives to sleep 2776 * so it probably doesn't matter). 2777 */ 2778 drv_usecwait(300000); 2779 2780 /* 2781 * If drive 0 exists the test for completion is simple 2782 */ 2783 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2784 2785 if (CTL2DRV(ata_ctlp, 0, 0)) { 2786 goto wait_for_not_busy; 2787 } 2788 2789 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2790 2791 /* 2792 * This must be a single device configuration, with drive 1 2793 * only. This complicates the test for completion because 2794 * issuing the software reset just caused drive 1 to 2795 * deselect. With drive 1 deselected, if I just read the 2796 * status register to test the BSY bit I get garbage, but 2797 * I can't re-select drive 1 until I'm certain the BSY bit 2798 * is de-asserted. Catch-22. 2799 * 2800 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2801 * this situation like this: 2802 */ 2803 2804 /* give up if the drive doesn't settle within 31 seconds */ 2805 while (gethrtime() < deadline) { 2806 /* 2807 * delay 10msec each time around the loop 2808 */ 2809 drv_usecwait(10000); 2810 2811 /* 2812 * try to select drive 1 2813 */ 2814 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2815 2816 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2817 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2818 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2819 continue; 2820 2821 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2822 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2823 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2824 continue; 2825 2826 goto wait_for_not_busy; 2827 } 2828 return (FALSE); 2829 2830wait_for_not_busy: 2831 2832 /* 2833 * Now wait up to 31 seconds for BUSY to clear. 2834 */ 2835 usecs_left = (deadline - gethrtime()) / 1000; 2836 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2837 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2838 2839 return (TRUE); 2840} 2841 2842/* 2843 * 2844 * DDI interrupt handler 2845 * 2846 */ 2847 2848static uint_t 2849ata_intr( 2850 caddr_t arg) 2851{ 2852 ata_ctl_t *ata_ctlp; 2853 int one_shot = 1; 2854 2855 ata_ctlp = (ata_ctl_t *)arg; 2856 2857 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2858} 2859 2860 2861/* 2862 * 2863 * GHD ccc_get_status callback 2864 * 2865 */ 2866 2867static int 2868ata_get_status( 2869 void *hba_handle, 2870 void *intr_status) 2871{ 2872 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2873 uchar_t status; 2874 2875 ADBG_TRACE(("ata_get_status entered\n")); 2876 2877 /* 2878 * ignore interrupts before ata_attach completes 2879 */ 2880 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2881 return (FALSE); 2882 2883 /* 2884 * can't be interrupt pending if nothing active 2885 */ 2886 switch (ata_ctlp->ac_state) { 2887 case AS_IDLE: 2888 return (FALSE); 2889 case AS_ACTIVE0: 2890 case AS_ACTIVE1: 2891 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2892 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2893 break; 2894 } 2895 2896 /* 2897 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2898 * interrupt status latch. But don't clear it yet. 2899 * 2900 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2901 * CMD chips with device id 0x646. Since the interrupt bit on 2902 * Bus master IDE register is not usable when in PIO mode, 2903 * this chip is treated as a legacy device for interrupt 2904 * indication. The following code for CMD 2905 * chips may need to be revisited when we enable support for dma. 2906 * 2907 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2908 * checked only if there was DMA used or BM intr is useable on PIO, 2909 * else treat it as before - as legacy device. 2910 */ 2911 2912 if ((ata_ctlp->ac_pciide) && 2913 ((ata_ctlp->ac_pciide_bm != FALSE) && 2914 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2915 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2916 2917 if (!ata_pciide_status_pending(ata_ctlp)) 2918 return (FALSE); 2919 } else { 2920 /* 2921 * Interrupts from legacy ATA/IDE controllers are 2922 * edge-triggered but the dumb legacy ATA/IDE controllers 2923 * and drives don't have an interrupt status bit. 2924 * 2925 * Use a one_shot variable to make sure we only return 2926 * one status per interrupt. 2927 */ 2928 if (intr_status != NULL) { 2929 int *one_shot = (int *)intr_status; 2930 2931 if (*one_shot == 1) 2932 *one_shot = 0; 2933 else 2934 return (FALSE); 2935 } 2936 } 2937 2938 /* check if device is still busy */ 2939 2940 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2941 if (status & ATS_BSY) 2942 return (FALSE); 2943 return (TRUE); 2944} 2945 2946 2947/* 2948 * 2949 * get the current status and clear the IRQ 2950 * 2951 */ 2952 2953int 2954ata_get_status_clear_intr( 2955 ata_ctl_t *ata_ctlp, 2956 ata_pkt_t *ata_pktp) 2957{ 2958 uchar_t status; 2959 2960 /* 2961 * Here's where we clear the PCI-IDE interrupt latch. If this 2962 * request used DMA mode then we also have to check and clear 2963 * the DMA error latch at the same time. 2964 */ 2965 2966 if (ata_pktp->ap_pciide_dma) { 2967 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2968 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2969 } else if ((ata_ctlp->ac_pciide) && 2970 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2971 /* 2972 * Some requests don't use DMA mode and therefore won't 2973 * set the DMA error latch, but we still have to clear 2974 * the interrupt latch. 2975 * Controllers with broken BM intr in PIO mode do not go 2976 * through this path. 2977 */ 2978 (void) ata_pciide_status_clear(ata_ctlp); 2979 } 2980 2981 /* 2982 * this clears the drive's interrupt 2983 */ 2984 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2985 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2986 return (status); 2987} 2988 2989 2990 2991/* 2992 * 2993 * GHD interrupt handler 2994 * 2995 */ 2996 2997/* ARGSUSED */ 2998static void 2999ata_process_intr( 3000 void *hba_handle, 3001 void *intr_status) 3002{ 3003 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 3004 int watchdog; 3005 uchar_t fsm_func; 3006 int rc; 3007 3008 ADBG_TRACE(("ata_process_intr entered\n")); 3009 3010 /* 3011 * process the ATA or ATAPI interrupt 3012 */ 3013 3014 fsm_func = ATA_FSM_INTR; 3015 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 3016 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 3017 3018 switch (rc) { 3019 case ATA_FSM_RC_OKAY: 3020 return; 3021 3022 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 3023 return; 3024 3025 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 3026 fsm_func = ATA_FSM_INTR; 3027 break; 3028 3029 case ATA_FSM_RC_FINI: /* move a request to done Q */ 3030 fsm_func = ATA_FSM_FINI; 3031 break; 3032 } 3033 } 3034 ADBG_WARN(("ata_process_intr: watchdog\n")); 3035} 3036 3037 3038 3039/* 3040 * 3041 * GHD ccc_hba_start callback 3042 * 3043 */ 3044 3045static int 3046ata_hba_start( 3047 void *hba_handle, 3048 gcmd_t *gcmdp) 3049{ 3050 ata_ctl_t *ata_ctlp; 3051 ata_drv_t *ata_drvp; 3052 ata_pkt_t *ata_pktp; 3053 uchar_t fsm_func; 3054 int request_started; 3055 int watchdog; 3056 3057 ADBG_TRACE(("ata_hba_start entered\n")); 3058 3059 ata_ctlp = (ata_ctl_t *)hba_handle; 3060 3061 if (ata_ctlp->ac_active_drvp != NULL) { 3062 ADBG_WARN(("ata_hba_start drvp not null\n")); 3063 return (FALSE); 3064 } 3065 if (ata_ctlp->ac_active_pktp != NULL) { 3066 ADBG_WARN(("ata_hba_start pktp not null\n")); 3067 return (FALSE); 3068 } 3069 3070 ata_pktp = GCMD2APKT(gcmdp); 3071 ata_drvp = GCMD2DRV(gcmdp); 3072 3073 /* 3074 * which drive? 3075 */ 3076 if (ata_drvp->ad_targ == 0) 3077 fsm_func = ATA_FSM_START0; 3078 else 3079 fsm_func = ATA_FSM_START1; 3080 3081 /* 3082 * start the request 3083 */ 3084 request_started = FALSE; 3085 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3086 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3087 NULL)) { 3088 case ATA_FSM_RC_OKAY: 3089 request_started = TRUE; 3090 goto fsm_done; 3091 3092 case ATA_FSM_RC_BUSY: 3093 /* if first time, tell GHD to requeue the request */ 3094 goto fsm_done; 3095 3096 case ATA_FSM_RC_INTR: 3097 /* 3098 * The start function polled for the next 3099 * bus phase, now fake an interrupt to process 3100 * the next action. 3101 */ 3102 request_started = TRUE; 3103 fsm_func = ATA_FSM_INTR; 3104 ata_drvp = NULL; 3105 ata_pktp = NULL; 3106 break; 3107 3108 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3109 request_started = TRUE; 3110 fsm_func = ATA_FSM_FINI; 3111 ata_drvp = NULL; 3112 ata_pktp = NULL; 3113 break; 3114 } 3115 } 3116 ADBG_WARN(("ata_hba_start: watchdog\n")); 3117 3118fsm_done: 3119 return (request_started); 3120 3121} 3122 3123static int 3124ata_check_pciide_blacklist( 3125 dev_info_t *dip, 3126 uint_t flags) 3127{ 3128 ushort_t vendorid; 3129 ushort_t deviceid; 3130 pcibl_t *blp; 3131 int *propp; 3132 uint_t count; 3133 int rc; 3134 3135 3136 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3137 DDI_PROP_DONTPASS, "vendor-id", 0); 3138 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3139 DDI_PROP_DONTPASS, "device-id", 0); 3140 3141 /* 3142 * first check for a match in the "pci-ide-blacklist" property 3143 */ 3144 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3145 "pci-ide-blacklist", &propp, &count); 3146 3147 if (rc == DDI_PROP_SUCCESS) { 3148 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3149 blp = (pcibl_t *)propp; 3150 while (count--) { 3151 /* check for matching ID */ 3152 if ((vendorid & blp->b_vmask) 3153 != (blp->b_vendorid & blp->b_vmask)) { 3154 blp++; 3155 continue; 3156 } 3157 if ((deviceid & blp->b_dmask) 3158 != (blp->b_deviceid & blp->b_dmask)) { 3159 blp++; 3160 continue; 3161 } 3162 3163 /* got a match */ 3164 if (blp->b_flags & flags) { 3165 ddi_prop_free(propp); 3166 return (TRUE); 3167 } else { 3168 ddi_prop_free(propp); 3169 return (FALSE); 3170 } 3171 } 3172 ddi_prop_free(propp); 3173 } 3174 3175 /* 3176 * then check the built-in blacklist 3177 */ 3178 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3179 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3180 continue; 3181 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3182 continue; 3183 if (!(blp->b_flags & flags)) 3184 continue; 3185 return (TRUE); 3186 } 3187 return (FALSE); 3188} 3189 3190int 3191ata_check_drive_blacklist( 3192 struct ata_id *aidp, 3193 uint_t flags) 3194{ 3195 atabl_t *blp; 3196 3197 for (blp = ata_drive_blacklist; blp->b_model != NULL; blp++) { 3198 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3199 sizeof (aidp->ai_model))) 3200 continue; 3201 if (blp->b_fw != NULL) { 3202 if (!ata_strncmp(blp->b_fw, aidp->ai_fw, 3203 sizeof (aidp->ai_fw))) 3204 continue; 3205 } 3206 if (blp->b_flags & flags) 3207 return (TRUE); 3208 return (FALSE); 3209 } 3210 return (FALSE); 3211} 3212 3213/* 3214 * Queue a request to perform some sort of internally 3215 * generated command. When this request packet reaches 3216 * the front of the queue (*func)() is invoked. 3217 * 3218 */ 3219 3220int 3221ata_queue_cmd( 3222 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3223 void *arg, 3224 ata_ctl_t *ata_ctlp, 3225 ata_drv_t *ata_drvp, 3226 gtgt_t *gtgtp) 3227{ 3228 ata_pkt_t *ata_pktp; 3229 gcmd_t *gcmdp; 3230 int rc; 3231 3232 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3233 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3234 return (FALSE); 3235 } 3236 3237 3238 /* set the back ptr from the ata_pkt to the gcmd_t */ 3239 ata_pktp = GCMD2APKT(gcmdp); 3240 ata_pktp->ap_gcmdp = gcmdp; 3241 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3242 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3243 3244 /* 3245 * over-ride the default start function 3246 */ 3247 ata_pktp = GCMD2APKT(gcmdp); 3248 ata_pktp->ap_start = func; 3249 ata_pktp->ap_complete = NULL; 3250 ata_pktp->ap_v_addr = (caddr_t)arg; 3251 3252 /* 3253 * add it to the queue, when it gets to the front the 3254 * ap_start function is called. 3255 */ 3256 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3257 0, TRUE, NULL); 3258 3259 if (rc != TRAN_ACCEPT) { 3260 /* this should never, ever happen */ 3261 return (FALSE); 3262 } 3263 3264 if (ata_pktp->ap_flags & AP_ERROR) 3265 return (FALSE); 3266 return (TRUE); 3267} 3268 3269/* 3270 * Check if this drive has the "revert to defaults" bug 3271 * PSARC 2001/500 and 2001/xxx - check for the properties 3272 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3273 * examining the blacklist. 3274 * <diskmodel> is made from the model number reported by Identify Drive 3275 * with uppercase letters converted to lowercase and all characters 3276 * except letters, digits, ".", "_", and "-" deleted. 3277 * Return value: 3278 * TRUE: enable revert to defaults 3279 * FALSE: disable revert to defaults 3280 * 3281 * NOTE: revert to power on defaults that includes reverting to MDMA 3282 * mode is allowed by ATA-6 & ATA-7 specs. 3283 * Therefore drives exhibiting this behaviour are not violating the spec. 3284 * Furthermore, the spec explicitly says that after the soft reset 3285 * host should check the current setting of the device features. 3286 * Correctly working BIOS would therefore reprogram either the drive 3287 * and/or the host controller to match transfer modes. 3288 * Devices with ATA_BL_NORVRT flag will be removed from 3289 * the ata_blacklist. 3290 * The default behaviour will be - no revert to power-on defaults 3291 * for all devices. The property is retained in case the user 3292 * explicitly requests revert-to-defaults before reboot. 3293 */ 3294 3295#define ATA_REVERT_PROP_PREFIX "revert-" 3296#define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3297/* room for prefix + model number + terminating NUL character */ 3298#define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3299 sizeof (aidp->ai_model) + 1) 3300#define PROP_LEN_MAX (31) 3301 3302static int 3303ata_check_revert_to_defaults( 3304 ata_drv_t *ata_drvp) 3305{ 3306 struct ata_id *aidp = &ata_drvp->ad_id; 3307 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3308 char prop_buf[PROP_BUF_SIZE]; 3309 int i, j; 3310 int propval; 3311 3312 /* put prefix into the buffer */ 3313 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3314 j = strlen(prop_buf); 3315 3316 /* append the model number, leaving out invalid characters */ 3317 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3318 char c = aidp->ai_model[i]; 3319 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3320 c = c - 'A' + 'a'; 3321 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3322 c == '.' || c == '_' || c == '-') 3323 prop_buf[j++] = c; 3324 if (c == '\0') 3325 break; 3326 } 3327 3328 /* make sure there's a terminating NUL character */ 3329 if (j >= PROP_LEN_MAX) 3330 j = PROP_LEN_MAX; 3331 prop_buf[j] = '\0'; 3332 3333 /* look for a disk-specific "revert" property" */ 3334 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3335 DDI_PROP_DONTPASS, prop_buf, -1); 3336 if (propval == 0) 3337 return (FALSE); 3338 else if (propval != -1) 3339 return (TRUE); 3340 3341 /* look for a global "revert" property" */ 3342 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3343 0, ATA_REVERT_PROP_GLOBAL, -1); 3344 if (propval == 0) 3345 return (FALSE); 3346 else if (propval != -1) 3347 return (TRUE); 3348 3349 return (FALSE); 3350} 3351 3352void 3353ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3354{ 3355 int i; 3356 3357 if (ata_ctlp->ac_pciide_bm == FALSE || 3358 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3359 if (ata_cntrl_DMA_sel_msg) { 3360 ATAPRT(( 3361 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3362 } else if (ata_dev_DMA_sel_msg) { 3363 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3364 } 3365 ATAPRT(("?\tPIO mode %d selected\n", 3366 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3367 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3368 } else { 3369 /* Using DMA */ 3370 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3371 /* 3372 * Rely on the fact that either dwdma or udma is 3373 * selected, not both. 3374 */ 3375 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3376 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3377 ATAC_MDMA_2_SEL ? 2 : 3378 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3379 ATAC_MDMA_1_SEL ? 1 : 0)); 3380 } else { 3381 for (i = 0; i <= 6; i++) { 3382 if (ata_drvp->ad_id.ai_ultradma & 3383 (1 << (i + 8))) { 3384 ATAPRT(( 3385 "?\tUltraDMA mode %d selected\n", 3386 i)); 3387 break; 3388 } 3389 } 3390 } 3391 } 3392} 3393 3394/* 3395 * Controller-specific operation pointers. 3396 * Should be extended as needed - init only for now 3397 */ 3398struct ata_ctl_spec_ops { 3399 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3400}; 3401 3402 3403struct ata_ctl_spec { 3404 ushort_t cs_vendor_id; 3405 ushort_t cs_device_id; 3406 struct ata_ctl_spec_ops *cs_ops; 3407}; 3408 3409/* Sil3XXX-specific functions (init only for now) */ 3410struct ata_ctl_spec_ops sil3xxx_ops = { 3411 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3412}; 3413 3414 3415struct ata_ctl_spec ata_cntrls_spec[] = { 3416 {0x1095, 0x3114, &sil3xxx_ops}, 3417 {0x1095, 0x3512, &sil3xxx_ops}, 3418 {0x1095, 0x3112, &sil3xxx_ops}, 3419 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3420}; 3421 3422/* 3423 * Do controller specific initialization if necessary. 3424 * Pick-up controller specific functions. 3425 */ 3426 3427int 3428ata_spec_init_controller(dev_info_t *dip) 3429{ 3430 ushort_t vendor_id; 3431 ushort_t device_id; 3432 struct ata_ctl_spec *ctlsp; 3433 3434 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3435 DDI_PROP_DONTPASS, "vendor-id", 0); 3436 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3437 DDI_PROP_DONTPASS, "device-id", 0); 3438 3439 /* Locate controller specific ops, if they exist */ 3440 ctlsp = ata_cntrls_spec; 3441 while (ctlsp->cs_ops != NULL) { 3442 if (ctlsp->cs_vendor_id == vendor_id && 3443 ctlsp->cs_device_id == device_id) 3444 break; 3445 ctlsp++; 3446 } 3447 3448 if (ctlsp->cs_ops != NULL) { 3449 if (ctlsp->cs_ops->cs_init != NULL) { 3450 /* Initialize controller */ 3451 if ((*(ctlsp->cs_ops->cs_init)) 3452 (dip, vendor_id, device_id) != TRUE) { 3453 cmn_err(CE_WARN, 3454 "pci%4x,%4x cntrl specific " 3455 "initialization failed", 3456 vendor_id, device_id); 3457 return (FALSE); 3458 } 3459 } 3460 } 3461 return (TRUE); 3462} 3463 3464/* 3465 * this routine works like ddi_prop_get_int, except that it works on 3466 * a string property that contains ascii representations 3467 * of an integer. 3468 * If the property is not found, the default value is returned. 3469 */ 3470static int 3471ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3472 uint_t flags, char *name, int defvalue) 3473{ 3474 3475 char *bufp, *cp; 3476 int rc = defvalue; 3477 int proprc; 3478 3479 proprc = ddi_prop_lookup_string(match_dev, dip, 3480 flags, name, &bufp); 3481 3482 if (proprc == DDI_PROP_SUCCESS) { 3483 cp = bufp; 3484 rc = stoi(&cp); 3485 ddi_prop_free(bufp); 3486 } else { 3487 /* 3488 * see if property is encoded as an int instead of string. 3489 */ 3490 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3491 } 3492 3493 return (rc); 3494} 3495 3496/* 3497 * Initialize the power management components 3498 */ 3499static void 3500ata_init_pm(dev_info_t *dip) 3501{ 3502 char pmc_name[16]; 3503 char *pmc[] = { 3504 NULL, 3505 "0=Sleep (PCI D3 State)", 3506 "3=PowerOn (PCI D0 State)", 3507 NULL 3508 }; 3509 int instance; 3510 ata_ctl_t *ata_ctlp; 3511 3512 3513 instance = ddi_get_instance(dip); 3514 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3515 ata_ctlp->ac_pm_support = 0; 3516 3517 /* check PCI capabilities */ 3518 if (!ata_is_pci(dip)) 3519 return; 3520 3521 (void) sprintf(pmc_name, "NAME=ata%d", instance); 3522 pmc[0] = pmc_name; 3523 3524#ifdef ATA_USE_AUTOPM 3525 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3526 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 3527 return; 3528 } 3529#endif 3530 3531 ata_ctlp->ac_pm_support = 1; 3532 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3533 3534 ATA_BUSY_COMPONENT(dip, 0); 3535 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 3536 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 3537 } 3538 ATA_IDLE_COMPONENT(dip, 0); 3539} 3540 3541/* 3542 * resume the hard drive 3543 */ 3544static void 3545ata_resume_drive(ata_drv_t *ata_drvp) 3546{ 3547 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3548 int drive_type; 3549 struct ata_id id; 3550 3551 ADBG_TRACE(("ata_resume_drive entered\n")); 3552 3553 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 3554 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3555 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3556 &id); 3557 if (drive_type == ATA_DEV_NONE) 3558 return; 3559 3560 if (!ATAPIDRV(ata_drvp)) { 3561 /* Reset Ultra DMA mode */ 3562 ata_reset_dma_mode(ata_drvp); 3563 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 3564 return; 3565 } else { 3566 (void) atapi_init_drive(ata_drvp); 3567 if (ata_drvp->ad_dma_mode != 0) { 3568 (void) atapi_reset_dma_mode(ata_drvp, FALSE); 3569 if (!ata_check_dma_mode(ata_drvp)) 3570 atapi_reset_dma_mode(ata_drvp, TRUE); 3571 if (ata_drvp->ad_id.ai_ultradma != 3572 ata_drvp->ad_dma_mode) { 3573 ata_drvp->ad_pciide_dma = ATA_DMA_OFF; 3574 } else { 3575 ata_drvp->ad_pciide_dma = ATA_DMA_ON; 3576 } 3577 } 3578 } 3579 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 3580 3581} 3582 3583/* 3584 * resume routine, it will be run when get the command 3585 * DDI_RESUME at attach(9E) from system power management 3586 */ 3587static int 3588ata_resume(dev_info_t *dip) 3589{ 3590 int instance; 3591 ata_ctl_t *ata_ctlp; 3592 ddi_acc_handle_t io_hdl2; 3593 caddr_t ioaddr2; 3594 3595 instance = ddi_get_instance(dip); 3596 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3597 3598 if (!ata_ctlp->ac_pm_support) 3599 return (DDI_FAILURE); 3600 if (ata_ctlp->ac_pm_level == PM_LEVEL_D0) 3601 return (DDI_SUCCESS); 3602 3603 ATA_BUSY_COMPONENT(dip, 0); 3604 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE) 3605 return (DDI_FAILURE); 3606 ATA_IDLE_COMPONENT(dip, 0); 3607 3608 /* enable interrupts from the device */ 3609 io_hdl2 = ata_ctlp->ac_iohandle2; 3610 ioaddr2 = ata_ctlp->ac_ioaddr2; 3611 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 3612 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3613 3614 return (DDI_SUCCESS); 3615} 3616 3617/* 3618 * suspend routine, it will be run when get the command 3619 * DDI_SUSPEND at detach(9E) from system power management 3620 */ 3621static int 3622ata_suspend(dev_info_t *dip) 3623{ 3624 int instance; 3625 ata_ctl_t *ata_ctlp; 3626 ddi_acc_handle_t io_hdl2; 3627 3628 instance = ddi_get_instance(dip); 3629 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3630 3631 if (!ata_ctlp->ac_pm_support) 3632 return (DDI_FAILURE); 3633 if (ata_ctlp->ac_pm_level == PM_LEVEL_D3) 3634 return (DDI_SUCCESS); 3635 3636 /* disable interrupts and turn the software reset bit on */ 3637 io_hdl2 = ata_ctlp->ac_iohandle2; 3638 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 3639 3640 (void) ata_reset_bus(ata_ctlp); 3641 (void) ata_change_power(dip, ATC_SLEEP); 3642 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3643 return (DDI_SUCCESS); 3644} 3645 3646int ata_save_pci_config = 0; 3647/* 3648 * ata specific power management entry point, it was 3649 * used to change the power management component 3650 */ 3651static int 3652ata_power(dev_info_t *dip, int component, int level) 3653{ 3654 int instance; 3655 ata_ctl_t *ata_ctlp; 3656 uint8_t cmd; 3657 3658 ADBG_TRACE(("ata_power entered, component = %d, level = %d\n", 3659 component, level)); 3660 3661 instance = ddi_get_instance(dip); 3662 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3663 if (ata_ctlp == NULL || component != 0) 3664 return (DDI_FAILURE); 3665 3666 if (!ata_ctlp->ac_pm_support) 3667 return (DDI_FAILURE); 3668 3669 if (ata_ctlp->ac_pm_level == level) 3670 return (DDI_SUCCESS); 3671 3672 switch (level) { 3673 case PM_LEVEL_D0: 3674 if (ata_save_pci_config) 3675 (void) pci_restore_config_regs(dip); 3676 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3677 cmd = ATC_IDLE_IMMED; 3678 break; 3679 case PM_LEVEL_D3: 3680 if (ata_save_pci_config) 3681 (void) pci_save_config_regs(dip); 3682 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3683 cmd = ATC_SLEEP; 3684 break; 3685 default: 3686 return (DDI_FAILURE); 3687 } 3688 return (ata_change_power(dip, cmd)); 3689} 3690 3691/* 3692 * sent commands to ata controller to change the power level 3693 */ 3694static int 3695ata_change_power(dev_info_t *dip, uint8_t cmd) 3696{ 3697 int instance; 3698 ata_ctl_t *ata_ctlp; 3699 ata_drv_t *ata_drvp; 3700 uchar_t targ; 3701 struct ata_id id; 3702 uchar_t lun; 3703 uchar_t lastlun; 3704 struct ata_id *aidp; 3705 3706 ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd)); 3707 3708 instance = ddi_get_instance(dip); 3709 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3710 3711 /* 3712 * Issue command on each disk device on the bus. 3713 */ 3714 if (cmd == ATC_SLEEP) { 3715 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3716 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3717 if (ata_drvp == NULL) 3718 continue; 3719 if (ata_drvp->ad_dma_cap == 0 && 3720 ata_drvp->ad_pciide_dma == ATA_DMA_ON) { 3721 aidp = &ata_drvp->ad_id; 3722 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3723 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) { 3724 ata_drvp->ad_dma_cap = 3725 ATA_DMA_ULTRAMODE; 3726 ata_drvp->ad_dma_mode = 3727 aidp->ai_ultradma; 3728 } else if (aidp->ai_dworddma & 3729 ATAC_MDMA_SEL_MASK) { 3730 ata_drvp->ad_dma_cap = 3731 ATA_DMA_MWORDMODE; 3732 ata_drvp->ad_dma_mode = 3733 aidp->ai_dworddma; 3734 } 3735 } 3736 if (ata_drive_type(ata_drvp->ad_drive_bits, 3737 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3738 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3739 &id) != ATA_DEV_DISK) 3740 continue; 3741 (void) ata_flush_cache(ata_ctlp, ata_drvp); 3742 if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 3743 5 * 1000000, cmd, 0, 0, 0, 0, 0, 0)) { 3744 cmn_err(CE_WARN, "!ata_controller - Can not " 3745 "put drive %d in to power mode %u", 3746 targ, cmd); 3747 (void) ata_devo_reset(dip, DDI_RESET_FORCE); 3748 return (DDI_FAILURE); 3749 } 3750 } 3751 return (DDI_SUCCESS); 3752 } 3753 3754 (void) ata_software_reset(ata_ctlp); 3755 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3756 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3757 if (ata_drvp == NULL) 3758 continue; 3759 ata_resume_drive(ata_drvp); 3760 3761 if (ATAPIDRV(ata_drvp)) 3762 lastlun = ata_drvp->ad_id.ai_lastlun; 3763 else 3764 lastlun = 0; 3765 if (!ata_enable_atapi_luns) 3766 lastlun = 0; 3767 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 3768 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 3769 if (ata_drvp != NULL) 3770 ata_resume_drive(ata_drvp); 3771 } 3772 } 3773 3774 return (DDI_SUCCESS); 3775} 3776 3777/* 3778 * return 1 when ata controller is a pci device, 3779 * otherwise return 0 3780 */ 3781static int 3782ata_is_pci(dev_info_t *dip) 3783{ 3784 int rc; 3785 char *bufp; 3786 int ispci; 3787 3788 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 3789 DDI_PROP_DONTPASS, "device_type", &bufp); 3790 3791 if (rc != DDI_PROP_SUCCESS) { 3792 ADBG_ERROR(("ata_is_pci !device_type\n")); 3793 return (0); 3794 } 3795 3796 ispci = (strcmp(bufp, "pci-ide") == 0); 3797 3798 ddi_prop_free(bufp); 3799 3800 return (ispci); 3801} 3802 3803/* 3804 * Disable DMA for this drive 3805 */ 3806static void 3807ata_disable_DMA(ata_drv_t *ata_drvp) 3808{ 3809 struct ata_id *aidp; 3810 char buf[sizeof (aidp->ai_model) +2]; 3811 int i; 3812 3813 if (ata_drvp == NULL) 3814 return; 3815 3816 if (ata_drvp->ad_pciide_dma == ATA_DMA_OFF) 3817 return; 3818 3819 ata_drvp->ad_pciide_dma = ATA_DMA_OFF; 3820 3821 /* Print the message */ 3822 buf[0] = '\0'; 3823 aidp = &ata_drvp->ad_id; 3824 if (aidp != NULL) { 3825 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 3826 buf[sizeof (aidp->ai_model) -1] = '\0'; 3827 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 3828 buf[i] = '\0'; 3829 } 3830 cmn_err(CE_CONT, 3831 "?DMA disabled on %s target=%d, lun=%d due to DMA errors,", 3832 buf, ata_drvp->ad_targ, ata_drvp->ad_lun); 3833 cmn_err(CE_CONT, "?most likely due to the CF-to-IDE adapter."); 3834} 3835 3836/* 3837 * Check and select DMA mode 3838 * 3839 * TRUE is returned when set feature is called successfully, 3840 * otherwise return FALSE 3841 */ 3842int 3843ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3844{ 3845 struct ata_id *aidp; 3846 int mode, rval = FALSE; 3847 uint8_t subcmd; 3848 3849 aidp = &ata_drvp->ad_id; 3850 3851 /* Return directly if DMA is not supported */ 3852 if (!(aidp->ai_cap & ATAC_DMA_SUPPORT)) 3853 return (rval); 3854 3855 /* Return if DMA mode is already selected */ 3856 if (((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3857 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) || 3858 (aidp->ai_dworddma & ATAC_MDMA_SEL_MASK)) 3859 return (rval); 3860 3861 /* First check Ultra DMA mode if no DMA is selected */ 3862 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3863 (aidp->ai_ultradma & ATAC_UDMA_SUP_MASK)) { 3864 for (mode = 6; mode >= 0; --mode) { 3865 if (aidp->ai_ultradma & (1 << mode)) 3866 break; 3867 } 3868 subcmd = ATF_XFRMOD_UDMA; 3869 3870 } else if (aidp->ai_dworddma & ATAC_MDMA_SUP_MASK) { 3871 /* Then check multi-word DMA mode */ 3872 for (mode = 2; mode >= 0; --mode) { 3873 if (aidp->ai_dworddma & (1 << mode)) 3874 break; 3875 } 3876 subcmd = ATF_XFRMOD_MDMA; 3877 3878 } else { 3879 return (rval); 3880 } 3881 3882 rval = ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3883 subcmd|mode); 3884 3885 return (rval); 3886} 3887 3888/* 3889 * Reset Ultra DMA mode / MWDMA mode 3890 */ 3891void 3892ata_reset_dma_mode(ata_drv_t *ata_drvp) 3893{ 3894 uint8_t subcmd; 3895 int mode; 3896 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3897 3898 switch (ata_drvp->ad_dma_cap) { 3899 case ATA_DMA_ULTRAMODE: 3900 subcmd = ATF_XFRMOD_UDMA; 3901 for (mode = 0; mode <= 6; mode++) { 3902 if (ata_drvp->ad_dma_mode & (1 << (mode + 8))) 3903 break; 3904 } 3905 break; 3906 case ATA_DMA_MWORDMODE: 3907 subcmd = ATF_XFRMOD_MDMA; 3908 mode = ((ata_drvp->ad_dma_mode & ATAC_MDMA_2_SEL) == 3909 ATAC_MDMA_2_SEL ? 2 : 3910 (ata_drvp->ad_dma_mode & ATAC_MDMA_1_SEL) == 3911 ATAC_MDMA_1_SEL ? 1 : 0); 3912 break; 3913 default: 3914 return; 3915 } 3916 3917 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3918 (subcmd | mode)); 3919} 3920 3921/* 3922 * Check DMA mode is the same with saved info 3923 * return value: 0 - not same 3924 * 1 - same 3925 */ 3926static int 3927ata_check_dma_mode(ata_drv_t *ata_drvp) 3928{ 3929 struct ata_id *aidp; 3930 3931 aidp = &ata_drvp->ad_id; 3932 switch (ata_drvp->ad_dma_cap) { 3933 case ATA_DMA_ULTRAMODE: 3934 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3935 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK) && 3936 (aidp->ai_ultradma == ata_drvp->ad_dma_mode)) 3937 break; 3938 else 3939 return (0); 3940 case ATA_DMA_MWORDMODE: 3941 if ((aidp->ai_dworddma & ATAC_MDMA_SEL_MASK) && 3942 (aidp->ai_dworddma == ata_drvp->ad_dma_mode)) 3943 break; 3944 else 3945 return (0); 3946 default: 3947 return (0); 3948 } 3949 return (1); 3950} 3951