pci_cfgspace_impl.h revision 748:3a1ae73086e8 
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#ifndef _SYS_PCI_CFGSPACE_IMPL_H
28#define	_SYS_PCI_CFGSPACE_IMPL_H
29
30#pragma ident	"%Z%%M%	%I%	%E% SMI"
31
32/*
33 * Routines to support particular PCI chipsets
34 */
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40/*
41 * Generic Mechanism 1 routines
42 * XX64 putb -> put8, putw -> put16 etc.
43 */
44extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg);
45extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg);
46extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg);
47extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val);
48extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val);
49extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val);
50
51/*
52 * Generic Mechanism 2 routines
53 */
54extern uint8_t pci_mech2_getb(int bus, int dev, int func, int reg);
55extern uint16_t pci_mech2_getw(int bus, int dev, int func, int reg);
56extern uint32_t pci_mech2_getl(int bus, int dev, int func, int reg);
57extern void pci_mech2_putb(int bus, int dev, int func, int reg, uint8_t val);
58extern void pci_mech2_putw(int bus, int dev, int func, int reg, uint16_t val);
59extern void pci_mech2_putl(int bus, int dev, int func, int reg, uint32_t val);
60
61/*
62 * Intel Neptune routines.  Neptune is Mech 1, except that BIOSes
63 * often initialize it into Mech 2 so we dynamically switch it to
64 * Mech 1.  The chipset's buggy, so we have to do it carefully.
65 */
66extern boolean_t pci_check_neptune(void);
67extern uint8_t pci_neptune_getb(int bus, int dev, int func, int reg);
68extern uint16_t pci_neptune_getw(int bus, int dev, int func, int reg);
69extern uint32_t pci_neptune_getl(int bus, int dev, int func, int reg);
70extern void pci_neptune_putb(int bus, int dev, int func, int reg, uint8_t val);
71extern void pci_neptune_putw(int bus, int dev, int func, int reg, uint16_t val);
72extern void pci_neptune_putl(int bus, int dev, int func, int reg, uint32_t val);
73
74/*
75 * Intel Orion routines.  Orion is Mech 1, except that there's a bug
76 * in the peer bridge that requires that it be tweaked specially
77 * around accesses to config space.
78 */
79extern boolean_t pci_is_broken_orion(void);
80extern uint8_t pci_orion_getb(int bus, int dev, int func, int reg);
81extern uint16_t pci_orion_getw(int bus, int dev, int func, int reg);
82extern uint32_t pci_orion_getl(int bus, int dev, int func, int reg);
83extern void pci_orion_putb(int bus, int dev, int func, int reg, uint8_t val);
84extern void pci_orion_putw(int bus, int dev, int func, int reg, uint16_t val);
85extern void pci_orion_putl(int bus, int dev, int func, int reg, uint32_t val);
86
87/*
88 * Generic PCI constants.  Probably these should be in pci.h.
89 */
90#define	PCI_MAX_BUSSES		256
91#define	PCI_MAX_DEVS		32
92#define	PCI_MAX_FUNCS		8
93/*
94 * PCI access mechanism constants.  Probably these should be in pci_impl.h.
95 */
96#define	PCI_MECH2_CONFIG_ENABLE	0x10	/* any nonzero high nibble works */
97
98#define	PCI_MECH1_SPEC_CYCLE_DEV	0x1f	/* dev to request spec cyc */
99#define	PCI_MECH1_SPEC_CYCLE_FUNC	0x07	/* func to request spec cyc */
100
101/*
102 * Mutex for all pci config space routines to share
103 */
104
105extern kmutex_t pcicfg_mutex;
106
107/*
108 * Orion/Neptune cfg access wraps mech1 cfg access, so needs a separate mutex
109 */
110
111extern kmutex_t pcicfg_chipset_mutex;
112
113/*
114 * pci get irq routing information support
115 */
116#define	PCI_GET_IRQ_ROUTING	0x0e
117
118#define	PCI_FUNCTION_ID		(0xb1)
119#define	PCI_BIOS_PRESENT	(0x1)
120
121/*
122 * low-mem addresses for irq routing bios operations
123 * We set up the initial request for up to 32 table entries, and will
124 * re-issue for up to 255 entries if the bios indicates it requires
125 * a larger table.  255 entries plus the header would consume the
126 * memory between 0x7000-0x7fff.
127 */
128#define	BIOS_IRQ_ROUTING_HDR	0x7000
129#define	BIOS_IRQ_ROUTING_DATA	0x7010
130
131#define	N_PCI_IRQ_ROUTES	32
132#define	N_PCI_IRQ_ROUTES_MAX	255
133
134#define	FP_OFF(fp)	(((uintptr_t)(fp)) & 0xFFFF)
135#define	FP_SEG(fp)	((((uintptr_t)(fp)) >> 16) & 0xFFFF)
136
137#pragma pack(1)
138typedef struct pci_irq_route {
139	uchar_t		pir_bus;
140	uchar_t		pir_dev;
141	uchar_t		pir_inta_link;
142	uint16_t	pir_inta_irq_map;
143	uchar_t		pir_intb_link;
144	uint16_t	pir_intb_irq_map;
145	uchar_t		pir_intc_link;
146	uint16_t	pir_intc_irq_map;
147	uchar_t		pir_intd_link;
148	uint16_t	pir_intd_irq_map;
149	uchar_t		pir_slot;
150	uchar_t		pir_reserved;
151} pci_irq_route_t;
152#pragma pack()
153
154#pragma pack(1)
155typedef struct pci_irq_route_hdr {
156	uint16_t	pir_size;
157	uint32_t	pir_addr;
158} pci_irq_route_hdr_t;
159#pragma pack()
160
161#ifdef __cplusplus
162}
163#endif
164
165#endif /* _SYS_PCI_CFGSPACE_IMPL_H */
166