1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26#ifndef _SYS_PCI_CFGSPACE_IMPL_H 27#define _SYS_PCI_CFGSPACE_IMPL_H 28 29/* 30 * Routines to support particular PCI chipsets 31 */ 32 33#ifdef __cplusplus 34extern "C" { 35#endif 36 37/* 38 * Generic Mechanism 1 routines 39 * XX64 putb -> put8, putw -> put16 etc. 40 */ 41extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg); 42extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg); 43extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg); 44extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val); 45extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val); 46extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val); 47 48/* 49 * AMD family >= 0x10 Mechanism 1 routines with ECS support 50 */ 51extern boolean_t pci_check_amd_ioecs(void); 52extern uint8_t pci_mech1_amd_getb(int bus, int dev, int func, int reg); 53extern uint16_t pci_mech1_amd_getw(int bus, int dev, int func, int reg); 54extern uint32_t pci_mech1_amd_getl(int bus, int dev, int func, int reg); 55extern void pci_mech1_amd_putb(int bus, int dev, int func, int reg, 56 uint8_t val); 57extern void pci_mech1_amd_putw(int bus, int dev, int func, int reg, 58 uint16_t val); 59extern void pci_mech1_amd_putl(int bus, int dev, int func, int reg, 60 uint32_t val); 61 62/* 63 * Generic Mechanism 2 routines 64 */ 65extern uint8_t pci_mech2_getb(int bus, int dev, int func, int reg); 66extern uint16_t pci_mech2_getw(int bus, int dev, int func, int reg); 67extern uint32_t pci_mech2_getl(int bus, int dev, int func, int reg); 68extern void pci_mech2_putb(int bus, int dev, int func, int reg, uint8_t val); 69extern void pci_mech2_putw(int bus, int dev, int func, int reg, uint16_t val); 70extern void pci_mech2_putl(int bus, int dev, int func, int reg, uint32_t val); 71 72/* 73 * Intel Neptune routines. Neptune is Mech 1, except that BIOSes 74 * often initialize it into Mech 2 so we dynamically switch it to 75 * Mech 1. The chipset's buggy, so we have to do it carefully. 76 */ 77extern boolean_t pci_check_neptune(void); 78extern uint8_t pci_neptune_getb(int bus, int dev, int func, int reg); 79extern uint16_t pci_neptune_getw(int bus, int dev, int func, int reg); 80extern uint32_t pci_neptune_getl(int bus, int dev, int func, int reg); 81extern void pci_neptune_putb(int bus, int dev, int func, int reg, uint8_t val); 82extern void pci_neptune_putw(int bus, int dev, int func, int reg, uint16_t val); 83extern void pci_neptune_putl(int bus, int dev, int func, int reg, uint32_t val); 84 85/* 86 * Intel Orion routines. Orion is Mech 1, except that there's a bug 87 * in the peer bridge that requires that it be tweaked specially 88 * around accesses to config space. 89 */ 90extern boolean_t pci_is_broken_orion(void); 91extern uint8_t pci_orion_getb(int bus, int dev, int func, int reg); 92extern uint16_t pci_orion_getw(int bus, int dev, int func, int reg); 93extern uint32_t pci_orion_getl(int bus, int dev, int func, int reg); 94extern void pci_orion_putb(int bus, int dev, int func, int reg, uint8_t val); 95extern void pci_orion_putw(int bus, int dev, int func, int reg, uint16_t val); 96extern void pci_orion_putl(int bus, int dev, int func, int reg, uint32_t val); 97 98/* 99 * Generic PCI constants. Probably these should be in pci.h. 100 */ 101#define PCI_MAX_BUSSES 256 102#define PCI_MAX_DEVS 32 103#define PCI_MAX_FUNCS 8 104/* 105 * PCI access mechanism constants. Probably these should be in pci_impl.h. 106 */ 107#define PCI_MECH2_CONFIG_ENABLE 0x10 /* any nonzero high nibble works */ 108 109#define PCI_MECH1_SPEC_CYCLE_DEV 0x1f /* dev to request spec cyc */ 110#define PCI_MECH1_SPEC_CYCLE_FUNC 0x07 /* func to request spec cyc */ 111 112extern uint64_t mcfg_mem_base; 113extern uint8_t mcfg_bus_start; 114extern uint8_t mcfg_bus_end; 115 116/* 117 * Mutexes for pci config space routines 118 */ 119extern kmutex_t pcicfg_mutex; 120extern kmutex_t pcicfg_mmio_mutex; 121 122/* 123 * Orion/Neptune cfg access wraps mech1 cfg access, so needs a separate mutex 124 */ 125 126extern kmutex_t pcicfg_chipset_mutex; 127 128/* 129 * pci get irq routing information support 130 */ 131#define PCI_GET_IRQ_ROUTING 0x0e 132 133#define PCI_FUNCTION_ID (0xb1) 134#define PCI_BIOS_PRESENT (0x1) 135 136/* 137 * low-mem addresses for irq routing bios operations 138 * We set up the initial request for up to 32 table entries, and will 139 * re-issue for up to 255 entries if the bios indicates it requires 140 * a larger table. 255 entries plus the header would consume the 141 * memory between 0x7000-0x7fff. 142 */ 143#define BIOS_IRQ_ROUTING_HDR 0x7000 144#define BIOS_IRQ_ROUTING_DATA 0x7010 145 146#define N_PCI_IRQ_ROUTES 32 147#define N_PCI_IRQ_ROUTES_MAX 255 148 149#define MCFG_PROPNAME "ecfg" 150 151#define FP_OFF(fp) (((uintptr_t)(fp)) & 0xFFFF) 152#define FP_SEG(fp) ((((uintptr_t)(fp)) >> 16) & 0xFFFF) 153 154#pragma pack(1) 155typedef struct pci_irq_route { 156 uchar_t pir_bus; 157 uchar_t pir_dev; 158 uchar_t pir_inta_link; 159 uint16_t pir_inta_irq_map; 160 uchar_t pir_intb_link; 161 uint16_t pir_intb_irq_map; 162 uchar_t pir_intc_link; 163 uint16_t pir_intc_irq_map; 164 uchar_t pir_intd_link; 165 uint16_t pir_intd_irq_map; 166 uchar_t pir_slot; 167 uchar_t pir_reserved; 168} pci_irq_route_t; 169#pragma pack() 170 171#pragma pack(1) 172typedef struct pci_irq_route_hdr { 173 uint16_t pir_size; 174 uint32_t pir_addr; 175} pci_irq_route_hdr_t; 176#pragma pack() 177 178#ifdef __cplusplus 179} 180#endif 181 182#endif /* _SYS_PCI_CFGSPACE_IMPL_H */ 183