pci_cfgspace_impl.h revision 11787:92f11db549bc 
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
24 * Use is subject to license terms.
25 */
26
27#ifndef _SYS_PCI_CFGSPACE_IMPL_H
28#define	_SYS_PCI_CFGSPACE_IMPL_H
29
30/*
31 * Routines to support particular PCI chipsets
32 */
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38/*
39 * Generic Mechanism 1 routines
40 * XX64 putb -> put8, putw -> put16 etc.
41 */
42extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg);
43extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg);
44extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg);
45extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val);
46extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val);
47extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val);
48
49/*
50 * Generic Mechanism 2 routines
51 */
52extern uint8_t pci_mech2_getb(int bus, int dev, int func, int reg);
53extern uint16_t pci_mech2_getw(int bus, int dev, int func, int reg);
54extern uint32_t pci_mech2_getl(int bus, int dev, int func, int reg);
55extern void pci_mech2_putb(int bus, int dev, int func, int reg, uint8_t val);
56extern void pci_mech2_putw(int bus, int dev, int func, int reg, uint16_t val);
57extern void pci_mech2_putl(int bus, int dev, int func, int reg, uint32_t val);
58
59/*
60 * Intel Neptune routines.  Neptune is Mech 1, except that BIOSes
61 * often initialize it into Mech 2 so we dynamically switch it to
62 * Mech 1.  The chipset's buggy, so we have to do it carefully.
63 */
64extern boolean_t pci_check_neptune(void);
65extern uint8_t pci_neptune_getb(int bus, int dev, int func, int reg);
66extern uint16_t pci_neptune_getw(int bus, int dev, int func, int reg);
67extern uint32_t pci_neptune_getl(int bus, int dev, int func, int reg);
68extern void pci_neptune_putb(int bus, int dev, int func, int reg, uint8_t val);
69extern void pci_neptune_putw(int bus, int dev, int func, int reg, uint16_t val);
70extern void pci_neptune_putl(int bus, int dev, int func, int reg, uint32_t val);
71
72/*
73 * Intel Orion routines.  Orion is Mech 1, except that there's a bug
74 * in the peer bridge that requires that it be tweaked specially
75 * around accesses to config space.
76 */
77extern boolean_t pci_is_broken_orion(void);
78extern uint8_t pci_orion_getb(int bus, int dev, int func, int reg);
79extern uint16_t pci_orion_getw(int bus, int dev, int func, int reg);
80extern uint32_t pci_orion_getl(int bus, int dev, int func, int reg);
81extern void pci_orion_putb(int bus, int dev, int func, int reg, uint8_t val);
82extern void pci_orion_putw(int bus, int dev, int func, int reg, uint16_t val);
83extern void pci_orion_putl(int bus, int dev, int func, int reg, uint32_t val);
84
85/*
86 * Generic PCI constants.  Probably these should be in pci.h.
87 */
88#define	PCI_MAX_BUSSES		256
89#define	PCI_MAX_DEVS		32
90#define	PCI_MAX_FUNCS		8
91/*
92 * PCI access mechanism constants.  Probably these should be in pci_impl.h.
93 */
94#define	PCI_MECH2_CONFIG_ENABLE	0x10	/* any nonzero high nibble works */
95
96#define	PCI_MECH1_SPEC_CYCLE_DEV	0x1f	/* dev to request spec cyc */
97#define	PCI_MECH1_SPEC_CYCLE_FUNC	0x07	/* func to request spec cyc */
98
99extern uint64_t mcfg_mem_base;
100extern uint8_t mcfg_bus_start;
101extern uint8_t mcfg_bus_end;
102
103/*
104 * Mutexes for pci config space routines
105 */
106extern kmutex_t pcicfg_mutex;
107extern kmutex_t pcicfg_mmio_mutex;
108
109/*
110 * Orion/Neptune cfg access wraps mech1 cfg access, so needs a separate mutex
111 */
112
113extern kmutex_t pcicfg_chipset_mutex;
114
115/*
116 * pci get irq routing information support
117 */
118#define	PCI_GET_IRQ_ROUTING	0x0e
119
120#define	PCI_FUNCTION_ID		(0xb1)
121#define	PCI_BIOS_PRESENT	(0x1)
122
123/*
124 * low-mem addresses for irq routing bios operations
125 * We set up the initial request for up to 32 table entries, and will
126 * re-issue for up to 255 entries if the bios indicates it requires
127 * a larger table.  255 entries plus the header would consume the
128 * memory between 0x7000-0x7fff.
129 */
130#define	BIOS_IRQ_ROUTING_HDR	0x7000
131#define	BIOS_IRQ_ROUTING_DATA	0x7010
132
133#define	N_PCI_IRQ_ROUTES	32
134#define	N_PCI_IRQ_ROUTES_MAX	255
135
136#define	MCFG_PROPNAME		"ecfg"
137
138#define	FP_OFF(fp)	(((uintptr_t)(fp)) & 0xFFFF)
139#define	FP_SEG(fp)	((((uintptr_t)(fp)) >> 16) & 0xFFFF)
140
141#pragma pack(1)
142typedef struct pci_irq_route {
143	uchar_t		pir_bus;
144	uchar_t		pir_dev;
145	uchar_t		pir_inta_link;
146	uint16_t	pir_inta_irq_map;
147	uchar_t		pir_intb_link;
148	uint16_t	pir_intb_irq_map;
149	uchar_t		pir_intc_link;
150	uint16_t	pir_intc_irq_map;
151	uchar_t		pir_intd_link;
152	uint16_t	pir_intd_irq_map;
153	uchar_t		pir_slot;
154	uchar_t		pir_reserved;
155} pci_irq_route_t;
156#pragma pack()
157
158#pragma pack(1)
159typedef struct pci_irq_route_hdr {
160	uint16_t	pir_size;
161	uint32_t	pir_addr;
162} pci_irq_route_hdr_t;
163#pragma pack()
164
165#ifdef __cplusplus
166}
167#endif
168
169#endif /* _SYS_PCI_CFGSPACE_IMPL_H */
170