pci_cfgspace_impl.h revision 11245:28613b254aad
141459Sdillon/* 237Srgrimes * CDDL HEADER START 337Srgrimes * 42878Srgrimes * The contents of this file are subject to the terms of the 58571Srgrimes * Common Development and Distribution License (the "License"). 639490Sobrien * You may not use this file except in compliance with the License. 72878Srgrimes * 839849Sjkh * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 939849Sjkh * or http://www.opensolaris.org/os/licensing. 1039161Sobrien * See the License for the specific language governing permissions 1139490Sobrien * and limitations under the License. 128571Srgrimes * 132878Srgrimes * When distributing Covered Code, include this CDDL HEADER in each 142878Srgrimes * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 152878Srgrimes * If applicable, add the following below this CDDL HEADER, with the 168571Srgrimes * fields enclosed by brackets "[]" replaced with your own identifying 1728376Spst * information: Portions Copyright [yyyy] [name of copyright owner] 1828117Spst * 1928117Spst * CDDL HEADER END 2028117Spst */ 2128117Spst 2228117Spst/* 2328117Spst * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 2428117Spst * Use is subject to license terms. 258571Srgrimes */ 262878Srgrimes 278571Srgrimes#ifndef _SYS_PCI_CFGSPACE_IMPL_H 282878Srgrimes#define _SYS_PCI_CFGSPACE_IMPL_H 2930589Sjmb 3030589Sjmb/* 318571Srgrimes * Routines to support particular PCI chipsets 322878Srgrimes */ 338571Srgrimes 3441459Sdillon#ifdef __cplusplus 3541459Sdillonextern "C" { 3641459Sdillon#endif 3741459Sdillon 382878Srgrimes/* 398571Srgrimes * Generic Mechanism 1 routines 408571Srgrimes * XX64 putb -> put8, putw -> put16 etc. 4123219Swosch */ 4223219Swoschextern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg); 432878Srgrimesextern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg); 442878Srgrimesextern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg); 452878Srgrimesextern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val); 4639490Sobrienextern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val); 472878Srgrimesextern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val); 488571Srgrimes 492878Srgrimes/* 5040464Speter * Generic Mechanism 2 routines 5140464Speter */ 522878Srgrimesextern uint8_t pci_mech2_getb(int bus, int dev, int func, int reg); 532878Srgrimesextern uint16_t pci_mech2_getw(int bus, int dev, int func, int reg); 548571Srgrimesextern uint32_t pci_mech2_getl(int bus, int dev, int func, int reg); 552878Srgrimesextern void pci_mech2_putb(int bus, int dev, int func, int reg, uint8_t val); 5639490Sobrienextern void pci_mech2_putw(int bus, int dev, int func, int reg, uint16_t val); 572878Srgrimesextern void pci_mech2_putl(int bus, int dev, int func, int reg, uint32_t val); 5839161Sobrien 592878Srgrimes/* 608571Srgrimes * Intel Neptune routines. Neptune is Mech 1, except that BIOSes 612878Srgrimes * often initialize it into Mech 2 so we dynamically switch it to 628571Srgrimes * Mech 1. The chipset's buggy, so we have to do it carefully. 632878Srgrimes */ 642612Srgrimesextern boolean_t pci_check_neptune(void); 65extern uint8_t pci_neptune_getb(int bus, int dev, int func, int reg); 66extern uint16_t pci_neptune_getw(int bus, int dev, int func, int reg); 67extern uint32_t pci_neptune_getl(int bus, int dev, int func, int reg); 68extern void pci_neptune_putb(int bus, int dev, int func, int reg, uint8_t val); 69extern void pci_neptune_putw(int bus, int dev, int func, int reg, uint16_t val); 70extern void pci_neptune_putl(int bus, int dev, int func, int reg, uint32_t val); 71 72/* 73 * Intel Orion routines. Orion is Mech 1, except that there's a bug 74 * in the peer bridge that requires that it be tweaked specially 75 * around accesses to config space. 76 */ 77extern boolean_t pci_is_broken_orion(void); 78extern uint8_t pci_orion_getb(int bus, int dev, int func, int reg); 79extern uint16_t pci_orion_getw(int bus, int dev, int func, int reg); 80extern uint32_t pci_orion_getl(int bus, int dev, int func, int reg); 81extern void pci_orion_putb(int bus, int dev, int func, int reg, uint8_t val); 82extern void pci_orion_putw(int bus, int dev, int func, int reg, uint16_t val); 83extern void pci_orion_putl(int bus, int dev, int func, int reg, uint32_t val); 84 85/* 86 * Generic PCI constants. Probably these should be in pci.h. 87 */ 88#define PCI_MAX_BUSSES 256 89#define PCI_MAX_DEVS 32 90#define PCI_MAX_FUNCS 8 91/* 92 * PCI access mechanism constants. Probably these should be in pci_impl.h. 93 */ 94#define PCI_MECH2_CONFIG_ENABLE 0x10 /* any nonzero high nibble works */ 95 96#define PCI_MECH1_SPEC_CYCLE_DEV 0x1f /* dev to request spec cyc */ 97#define PCI_MECH1_SPEC_CYCLE_FUNC 0x07 /* func to request spec cyc */ 98 99extern uint64_t mcfg_mem_base; 100extern uint8_t mcfg_bus_start; 101extern uint8_t mcfg_bus_end; 102 103/* 104 * Mutex for all pci config space routines to share 105 */ 106extern kmutex_t pcicfg_mutex; 107 108/* 109 * Orion/Neptune cfg access wraps mech1 cfg access, so needs a separate mutex 110 */ 111 112extern kmutex_t pcicfg_chipset_mutex; 113 114/* 115 * pci get irq routing information support 116 */ 117#define PCI_GET_IRQ_ROUTING 0x0e 118 119#define PCI_FUNCTION_ID (0xb1) 120#define PCI_BIOS_PRESENT (0x1) 121 122/* 123 * low-mem addresses for irq routing bios operations 124 * We set up the initial request for up to 32 table entries, and will 125 * re-issue for up to 255 entries if the bios indicates it requires 126 * a larger table. 255 entries plus the header would consume the 127 * memory between 0x7000-0x7fff. 128 */ 129#define BIOS_IRQ_ROUTING_HDR 0x7000 130#define BIOS_IRQ_ROUTING_DATA 0x7010 131 132#define N_PCI_IRQ_ROUTES 32 133#define N_PCI_IRQ_ROUTES_MAX 255 134 135#define MCFG_PROPNAME "ecfg" 136 137#define FP_OFF(fp) (((uintptr_t)(fp)) & 0xFFFF) 138#define FP_SEG(fp) ((((uintptr_t)(fp)) >> 16) & 0xFFFF) 139 140#pragma pack(1) 141typedef struct pci_irq_route { 142 uchar_t pir_bus; 143 uchar_t pir_dev; 144 uchar_t pir_inta_link; 145 uint16_t pir_inta_irq_map; 146 uchar_t pir_intb_link; 147 uint16_t pir_intb_irq_map; 148 uchar_t pir_intc_link; 149 uint16_t pir_intc_irq_map; 150 uchar_t pir_intd_link; 151 uint16_t pir_intd_irq_map; 152 uchar_t pir_slot; 153 uchar_t pir_reserved; 154} pci_irq_route_t; 155#pragma pack() 156 157#pragma pack(1) 158typedef struct pci_irq_route_hdr { 159 uint16_t pir_size; 160 uint32_t pir_addr; 161} pci_irq_route_hdr_t; 162#pragma pack() 163 164#ifdef __cplusplus 165} 166#endif 167 168#endif /* _SYS_PCI_CFGSPACE_IMPL_H */ 169