1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, Version 1.0 only
6 * (the "License").  You may not use this file except in compliance
7 * with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22/*	Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T	*/
23/*	  All Rights Reserved  	*/
24
25
26#ifndef	_SYS_TERMIOX_H
27#define	_SYS_TERMIOX_H
28
29#pragma ident	"%Z%%M%	%I%	%E% SMI"	/* SVr4.0 1.4 */
30
31#ifdef	__cplusplus
32extern "C" {
33#endif
34
35/* This structure provides an extended terminal interface. */
36/* Features of this interface are optional and may not be */
37/* implemented on all machines. */
38
39
40#define	NFF	5
41
42/* hardware flow control modes */
43
44#define	RTSXOFF	0000001	/* Enable RTS hardware flow control on input */
45#define	CTSXON	0000002	/* Enable CTS hardware flow control on output */
46#define	DTRXOFF	0000004	/* Enable DTR hardware flow control on input */
47#define	CDXON	0000010	/* Enable CD hardware flow control on output */
48#define	ISXOFF	0000020	/* Enable isochronous hardware flow control on input */
49
50/* clock modes */
51
52#define	XMTCLK		0000007	/* Transmit Clock Source: */
53#define	XCIBRG		0000000	/* Get transmit clock from */
54				/*	internal baud rate generator */
55#define	XCTSET		0000001	/* Get transmit clock from */
56				/*	transmitter signal element */
57				/*	timing (DCE source) lead, */
58				/*	CCITT V.24 circuit 114, */
59				/*	EIA-232-D pin 15 */
60#define	XCRSET		0000002	/* Get transmit clock from */
61				/*	receiver signal element */
62				/*	timing (DCE source) lead, */
63				/*	CCITT V.24 circuit 115, */
64				/*	EIA-232-D pin 17 */
65
66#define	RCVCLK		0000070	/* Receive Clock Source: */
67#define	RCIBRG		0000000	/* get receive clock from internal */
68				/*	baud rate generator */
69#define	RCTSET		0000010	/* Get receive clock from */
70				/*	transmitter signal element */
71				/*	timing (DCE source) lead, */
72				/*	CCITT V.24 circuit 114, */
73				/*	EIA-232-D pin 15 */
74#define	RCRSET		0000020	/* Get receive clock from */
75				/*	receiver signal element */
76				/*	timing (DCE source) lead, */
77				/*	CCITT V.24 circuit 115, */
78				/*	EIA-232-D pin 17 */
79
80#define	TSETCLK		0000700	/* Transmitter Signal Element */
81				/*	timing (DTE source) lead, */
82				/*	CCITT V.24 circuit 113, */
83				/*	EIA-232-D pin 24, clock source: */
84#define	TSETCOFF	0000000	/* TSET clock not provided */
85#define	TSETCRBRG	0000100	/* Output receive baud rate generator */
86				/*	on circuit 113 */
87#define	TSETCTBRG	0000200	/* Output transmit baud rate generator */
88				/*	on circuit 113 */
89#define	TSETCTSET	0000300	/* Output transmitter signal element */
90				/*	timing (DCE source) on circuit 113 */
91#define	TSETCRSET	0000400	/* Output receiver signal element */
92				/*	timing (DCE source) on circuit 113 */
93
94#define	RSETCLK		0007000	/* Receiver Signal Element */
95				/*	timing (DTE source) lead, */
96				/*	CCITT V.24 circuit 128, */
97				/*	no EIA-232-D pin, clock source: */
98#define	RSETCOFF	0000000	/* RSET clock not provided */
99#define	RSETCRBRG	0001000	/* Output receive baud rate generator */
100				/*	on circuit 128 */
101#define	RSETCTBRG	0002000	/* Output transmit baud rate generator */
102				/*	on circuit 128 */
103#define	RSETCTSET	0003000	/* Output transmitter signal element */
104				/*	timing (DCE source) on circuit 128 */
105#define	RSETCRSET	0004000	/* Output receiver signal element */
106				/*	timing (DCE source) on circuit 128 */
107
108
109struct termiox {
110	unsigned short x_hflag;		/* hardware flow control modes */
111	unsigned short x_cflag;		/* clock modes */
112	unsigned short x_rflag[NFF];	/* reserved modes */
113	unsigned short x_sflag;		/* spare modes */
114};
115
116#define	XIOC    ('X'<<8)
117#define	TCGETX  (XIOC|1)
118#define	TCSETX  (XIOC|2)
119#define	TCSETXW (XIOC|3)
120#define	TCSETXF (XIOC|4)
121
122#ifdef	__cplusplus
123}
124#endif
125
126#endif	/* _SYS_TERMIOX_H */
127