1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_NXGE_NXGE_COMMON_H 27#define _SYS_NXGE_NXGE_COMMON_H 28 29#ifdef __cplusplus 30extern "C" { 31#endif 32 33#define NXGE_DMA_START B_TRUE 34#define NXGE_DMA_STOP B_FALSE 35 36/* 37 * Default DMA configurations. 38 */ 39#define NXGE_RDMA_PER_NIU_PORT (NXGE_MAX_RDCS/NXGE_PORTS_NIU) 40#define NXGE_TDMA_PER_NIU_PORT (NXGE_MAX_TDCS_NIU/NXGE_PORTS_NIU) 41#define NXGE_RDMA_PER_NEP_PORT (NXGE_MAX_RDCS/NXGE_PORTS_NEPTUNE) 42#define NXGE_TDMA_PER_NEP_PORT (NXGE_MAX_TDCS/NXGE_PORTS_NEPTUNE) 43#define NXGE_RDCGRP_PER_NIU_PORT (NXGE_MAX_RDC_GROUPS/NXGE_PORTS_NIU) 44#define NXGE_RDCGRP_PER_NEP_PORT (NXGE_MAX_RDC_GROUPS/NXGE_PORTS_NEPTUNE) 45 46#define NXGE_TIMER_RESO 2 47 48#define NXGE_TIMER_LDG 2 49 50/* 51 * Receive and Transmit DMA definitions 52 */ 53#if defined(sun4v) && defined(NIU_LP_WORKAROUND) 54/* 55 * N2/NIU: Maximum descriptors if we need to call 56 * Hypervisor to set up the logical pages 57 * and the driver must use contiguous memory. 58 */ 59#define NXGE_NIU_MAX_ENTRY (1 << 9) /* 512 */ 60#define NXGE_NIU_CONTIG_RBR_MAX (NXGE_NIU_MAX_ENTRY) 61#define NXGE_NIU_CONTIG_RCR_MAX (NXGE_NIU_MAX_ENTRY) 62#define NXGE_NIU_CONTIG_TX_MAX (NXGE_NIU_MAX_ENTRY) 63#endif 64 65#ifdef _DMA_USES_VIRTADDR 66#ifdef NIU_PA_WORKAROUND 67#define NXGE_DMA_BLOCK (16 * 64 * 4) 68#else 69#define NXGE_DMA_BLOCK 1 70#endif 71#else 72#define NXGE_DMA_BLOCK (64 * 64) 73#endif 74 75#define NXGE_RBR_RBB_MIN (128) 76#define NXGE_RBR_RBB_MAX (64 * 128 -1) 77 78#if defined(sun4v) && defined(NIU_LP_WORKAROUND) 79#define NXGE_RBR_RBB_DEFAULT 512 80#define NXGE_RBR_SPARE 0 81#else 82#if defined(__i386) 83#define NXGE_RBR_RBB_DEFAULT 256 84#else 85#define NXGE_RBR_RBB_DEFAULT (64 * 16) /* x86 hello */ 86#endif 87#define NXGE_RBR_SPARE 0 88#endif 89 90 91#define NXGE_RCR_MIN (NXGE_RBR_RBB_MIN * 2) 92 93#if defined(sun4v) && defined(NIU_LP_WORKAROUND) 94#define NXGE_RCR_MAX (8192) 95#define NXGE_RCR_DEFAULT (512) 96#define NXGE_TX_RING_DEFAULT (512) 97#else 98#ifndef NIU_PA_WORKAROUND 99#define NXGE_RCR_MAX (65355) /* MAX hardware supported */ 100#if defined(_BIG_ENDIAN) 101#define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 8) 102#else 103#ifdef USE_RX_BIG_BUF 104#define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 8) 105#else 106#define NXGE_RCR_DEFAULT (NXGE_RBR_RBB_DEFAULT * 4) 107#endif 108#endif 109#if defined(__i386) 110#define NXGE_TX_RING_DEFAULT (256) 111#else 112#define NXGE_TX_RING_DEFAULT (1024) 113#endif 114#define NXGE_TX_RING_MAX (64 * 128 - 1) 115#else 116#if defined(__i386) 117#define NXGE_RCR_DEFAULT (256) 118#define NXGE_TX_RING_DEFAULT (256) 119#else 120#define NXGE_RCR_DEFAULT (512) 121#define NXGE_TX_RING_DEFAULT (512) 122#endif 123#define NXGE_RCR_MAX (1024) 124#define NXGE_TX_RING_MAX (1024) 125#endif 126#endif 127 128#define NXGE_TX_RECLAIM 32 129 130/* per receive DMA channel configuration data structure */ 131typedef struct nxge_rdc_cfg { 132 uint32_t flag; /* 0: not configured, 1: configured */ 133 struct nxge_hw_list *nxge_hw_p; 134 uint32_t partition_id; 135 uint32_t port; /* function number */ 136 uint32_t rx_group_id; 137 138 /* Partitioning, DMC function zero. */ 139 uint32_t rx_log_page_vld_page0; /* TRUE or FALSE */ 140 uint32_t rx_log_page_vld_page1; /* TRUE or FALSE */ 141 uint64_t rx_log_mask1; 142 uint64_t rx_log_value1; 143 uint64_t rx_log_mask2; 144 uint64_t rx_log_value2; 145 uint64_t rx_log_page_relo1; 146 uint64_t rx_log_page_relo2; 147 uint64_t rx_log_page_hdl; 148 149 /* WRED parameters, DMC function zero */ 150 uint32_t red_enable; 151 152 uint32_t thre_syn; 153 uint32_t win_syn; 154 uint32_t threshold; 155 uint32_t win_non_syn; 156 157 /* RXDMA configuration, DMC */ 158 char *rdc_mbaddr_p; /* mailbox address */ 159 uint32_t min_flag; /* TRUE for 18 bytes header */ 160 161 /* Software Reserved Packet Buffer Offset, DMC */ 162 uint32_t sw_offset; 163 164 /* RBR Configuration A */ 165 uint64_t rbr_staddr; /* starting address of RBR */ 166 uint32_t rbr_nblks; /* # of RBR entries */ 167 uint32_t rbr_len; /* # of RBR entries in 64B lines */ 168 169 /* RBR Configuration B */ 170 uint32_t bksize; /* Block size is fixed. */ 171#define RBR_BKSIZE_4K 0 172#define RBR_BKSIZE_4K_BYTES (4 * 1024) 173#define RBR_BKSIZE_8K 1 174#define RBR_BKSIZE_8K_BYTES (8 * 1024) 175#define RBR_BKSIZE_16K 2 176#define RBR_BKSIZE_16K_BYTES (16 * 1024) 177#define RBR_BKSIZE_32K 3 178#define RBR_BKSIZE_32K_BYTES (32 * 1024) 179 180 uint32_t bufsz2; 181#define RBR_BUFSZ2_2K 0 182#define RBR_BUFSZ2_2K_BYTES (2 * 1024) 183#define RBR_BUFSZ2_4K 1 184#define RBR_BUFSZ2_4K_BYTES (4 * 1024) 185#define RBR_BUFSZ2_8K 2 186#define RBR_BUFSZ2_8K_BYTES (8 * 1024) 187#define RBR_BUFSZ2_16K 3 188#define RBR_BUFSZ2_16K_BYTES (16 * 1024) 189 190 uint32_t bufsz1; 191#define RBR_BUFSZ1_1K 0 192#define RBR_BUFSZ1_1K_BYTES 1024 193#define RBR_BUFSZ1_2K 1 194#define RBR_BUFSZ1_2K_BYTES (2 * 1024) 195#define RBR_BUFSZ1_4K 2 196#define RBR_BUFSZ1_4K_BYTES (4 * 1024) 197#define RBR_BUFSZ1_8K 3 198#define RBR_BUFSZ1_8K_BYTES (8 * 1024) 199 200 uint32_t bufsz0; 201#define RBR_BUFSZ0_256B 0 202#define RBR_BUFSZ0_256_BYTES 256 203#define RBR_BUFSZ0_512B 1 204#define RBR_BUFSZ0_512B_BYTES 512 205#define RBR_BUFSZ0_1K 2 206#define RBR_BUFSZ0_1K_BYTES (1024) 207#define RBR_BUFSZ0_2K 3 208#define RBR_BUFSZ0_2K_BYTES (2 * 1024) 209 210 /* Receive buffers added by the software */ 211 uint32_t bkadd; /* maximum size is 1 million */ 212 213 /* Receive Completion Ring Configuration A */ 214 uint32_t rcr_len; /* # of 64B blocks, each RCR is 8B */ 215 uint64_t rcr_staddr; 216 217 /* Receive Completion Ring Configuration B */ 218 uint32_t pthres; /* packet threshold */ 219 uint32_t entout; /* enable timeout */ 220 uint32_t timeout; /* timeout value */ 221 222 /* Logical Device Group Number */ 223 uint16_t rx_ldg; 224 uint16_t rx_ld_state_flags; 225 226 /* Receive DMA Channel Event Mask */ 227 uint64_t rx_dma_ent_mask; 228 229 /* 32 bit (set to 1) or 64 bit (set to 0) addressing mode */ 230 uint32_t rx_addr_md; 231} nxge_rdc_cfg_t, *p_nxge_rdc_cfg_t; 232 233/* 234 * Per Transmit DMA Channel Configuration Data Structure (32 TDC) 235 */ 236typedef struct nxge_tdc_cfg { 237 uint32_t flag; /* 0: not configured 1: configured */ 238 struct nxge_hw_list *nxge_hw_p; 239 uint32_t port; /* function number */ 240 /* partitioning, DMC function zero (All 0s for non-partitioning) */ 241 uint32_t tx_log_page_vld_page0; /* TRUE or FALSE */ 242 uint32_t tx_log_page_vld_page1; /* TRUE or FALSE */ 243 uint64_t tx_log_mask1; 244 uint64_t tx_log_value1; 245 uint64_t tx_log_mask2; 246 uint64_t tx_log_value2; 247 uint64_t tx_log_page_relo1; 248 uint64_t tx_log_page_relo2; 249 uint64_t tx_log_page_hdl; 250 251 /* Transmit Ring Configuration */ 252 uint64_t tx_staddr; 253 uint64_t tx_rng_len; /* in 64 B Blocks */ 254#define TX_MAX_BUF_SIZE 4096 255 256 /* TXDMA configuration, DMC */ 257 char *tdc_mbaddr_p; /* mailbox address */ 258 259 /* Logical Device Group Number */ 260 uint16_t tx_ldg; 261 uint16_t tx_ld_state_flags; 262 263 /* TXDMA event flags */ 264 uint64_t tx_event_mask; 265 266 /* Transmit threshold before reclamation */ 267 uint32_t tx_rng_threshold; 268#define TX_RING_THRESHOLD (TX_DEFAULT_MAX_GPS/4) 269#define TX_RING_JUMBO_THRESHOLD (TX_DEFAULT_JUMBO_MAX_GPS/4) 270 271 /* For reclaim: a wrap-around counter (packets transmitted) */ 272 uint32_t tx_pkt_cnt; 273 /* last packet with the mark bit set */ 274 uint32_t tx_lastmark; 275} nxge_tdc_cfg_t, *p_nxge_tdc_cfg_t; 276 277#define RDC_TABLE_ENTRY_METHOD_SEQ 0 278#define RDC_TABLE_ENTRY_METHOD_REP 1 279 280/* per transmit DMA channel table group data structure */ 281typedef struct nxge_tdc_grp { 282 uint32_t start_tdc; /* assume assigned in sequence */ 283 uint8_t max_tdcs; 284 dc_map_t map; 285 uint8_t grp_index; /* nxge_t.tx_set.group[grp_index] */ 286} nxge_tdc_grp_t, *p_nxge_tdc_grp_t; 287 288/* per receive DMA channel table group data structure */ 289typedef struct nxge_rdc_grp { 290 boolean_t flag; /* 0: not configured 1: configured */ 291 uint8_t port; 292 uint32_t start_rdc; /* assume assigned in sequence */ 293 uint8_t max_rdcs; 294 uint8_t def_rdc; 295 dc_map_t map; 296 uint16_t config_method; 297 uint8_t grp_index; /* nxge_t.rx_set.group[grp_index] */ 298} nxge_rdc_grp_t, *p_nxge_rdc_grp_t; 299 300#define RDC_MAP_IN(map, rdc) \ 301 (map |= (1 << rdc)) 302 303#define RDC_MAP_OUT(map, rdc) \ 304 (map &= (~(1 << rdc))) 305 306/* Common RDC and TDC configuration of DMC */ 307typedef struct _nxge_dma_common_cfg_t { 308 uint16_t rdc_red_ran_init; /* RED initial seed value */ 309 310 /* Transmit Ring */ 311} nxge_dma_common_cfg_t, *p_nxge_dma_common_cfg_t; 312 313/* 314 * VLAN and MAC table configurations: 315 * Each VLAN ID should belong to at most one RDC group. 316 * Each port could own multiple RDC groups. 317 * Each MAC should belong to one RDC group. 318 */ 319typedef struct nxge_mv_cfg { 320 uint8_t flag; /* 0:unconfigure 1:configured */ 321 uint8_t rdctbl; /* RDC channel table group */ 322 uint8_t mpr_npr; /* MAC and VLAN preference */ 323} nxge_mv_cfg_t, *p_nxge_mv_cfg_t; 324 325typedef struct nxge_param_map { 326#if defined(_BIG_ENDIAN) 327 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 328 uint32_t remove:1; /* [29] Remove */ 329 uint32_t pref:1; /* [28] preference */ 330 uint32_t rsrv:4; /* [27:24] preference */ 331 uint32_t map_to:8; /* [23:16] map to resource */ 332 uint32_t param_id:16; /* [15:0] Param ID */ 333#else 334 uint32_t param_id:16; /* [15:0] Param ID */ 335 uint32_t map_to:8; /* [23:16] map to resource */ 336 uint32_t rsrv:4; /* [27:24] preference */ 337 uint32_t pref:1; /* [28] preference */ 338 uint32_t remove:1; /* [29] Remove */ 339 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 340#endif 341} nxge_param_map_t, *p_nxge_param_map_t; 342 343typedef struct nxge_rcr_param { 344#if defined(_BIG_ENDIAN) 345 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 346 uint32_t remove:1; /* [29] Remove */ 347 uint32_t rsrv:5; /* [28:24] preference */ 348 uint32_t rdc:8; /* [23:16] rdc # */ 349 uint32_t cfg_val:16; /* [15:0] interrupt parameter */ 350#else 351 uint32_t cfg_val:16; /* [15:0] interrupt parameter */ 352 uint32_t rdc:8; /* [23:16] rdc # */ 353 uint32_t rsrv:5; /* [28:24] preference */ 354 uint32_t remove:1; /* [29] Remove */ 355 uint32_t rsrvd2:2; /* [30:31] rsrvd */ 356#endif 357} nxge_rcr_param_t, *p_nxge_rcr_param_t; 358 359/* 360 * These are the properties of the TxDMA channels for this 361 * port (instance). 362 * <start> is the index of the first TDC that is being managed 363 * by this port. 364 * <count> is the number of TDCs being managed by this port. 365 * <owned> is the number of TDCs currently being utilized by this port. 366 * 367 * <owned> may be less than <count> in hybrid I/O systems. 368 */ 369typedef struct { 370 int start; /* start TDC (0 - 31) */ 371 int count; /* 8 - 32 */ 372 int owned; /* 1 - count */ 373} tdc_cfg_t; 374 375/* Needs to have entries in the ndd table */ 376/* 377 * Hardware properties created by fcode. 378 * In order for those properties visible to the user 379 * command ndd, we need to add the following properties 380 * to the ndd defined parameter array and data structures. 381 * 382 * Use default static configuration for x86. 383 */ 384typedef struct nxge_hw_pt_cfg { 385 uint32_t function_number; /* function number */ 386 tdc_cfg_t tdc; 387 uint32_t start_rdc; /* start RDC (0 - 31) */ 388 uint32_t max_rdcs; /* max rdc in sequence */ 389 uint32_t ninterrupts; /* obp interrupts(mac/mif/syserr) */ 390 uint32_t mac_ldvid; 391 uint32_t mif_ldvid; 392 uint32_t ser_ldvid; 393 uint32_t def_rdc; /* default RDC */ 394 uint32_t drr_wt; /* port DRR weight */ 395 uint32_t max_grpids; /* max group ID */ 396 uint32_t grpids[NXGE_MAX_RDCS]; /* RDC group IDs */ 397 uint32_t max_rdc_grpids; /* max RDC group ID */ 398 uint32_t start_ldg; /* starting logical group # */ 399 uint32_t max_ldgs; /* max logical device group */ 400 uint32_t max_ldvs; /* max logical devices */ 401 uint32_t start_mac_entry; /* where to put the first mac */ 402 uint32_t max_macs; /* the max mac entry allowed */ 403 uint32_t mac_pref; /* preference over VLAN */ 404 uint32_t def_mac_txdma_grpid; /* default TDC group ID */ 405 uint32_t def_mac_rxdma_grpid; /* default RDC group ID */ 406 uint32_t vlan_pref; /* preference over MAC */ 407 408 /* Expand if we have more hardware or default configurations */ 409 uint16_t ldg[NXGE_INT_MAX_LDG]; 410 uint16_t ldg_chn_start; 411} nxge_hw_pt_cfg_t, *p_nxge_hw_pt_cfg_t; 412 413 414/* per port configuration */ 415typedef struct nxge_dma_pt_cfg { 416 uint8_t mac_port; /* MAC port (function) */ 417 nxge_hw_pt_cfg_t hw_config; /* hardware configuration */ 418 419 uint32_t alloc_buf_size; 420 uint32_t rbr_size; 421 uint32_t rcr_size; 422 423 /* 424 * Configuration for hardware initialization based on the 425 * hardware properties or the default properties. 426 */ 427 uint32_t tx_dma_map; /* Transmit DMA channel bit map */ 428 429 /* Transmit DMA channel: device wise */ 430 nxge_tdc_grp_t tdc_grps[NXGE_MAX_TDC_GROUPS]; 431 432 /* Receive DMA channel */ 433 nxge_rdc_grp_t rdc_grps[NXGE_MAX_RDC_GROUPS]; 434 435 uint16_t rcr_timeout[NXGE_MAX_RDCS]; 436 uint16_t rcr_threshold[NXGE_MAX_RDCS]; 437 uint8_t rcr_full_header; 438 uint16_t rx_drr_weight; 439 440 /* Add more stuff later */ 441} nxge_dma_pt_cfg_t, *p_nxge_dma_pt_cfg_t; 442 443/* classification configuration */ 444typedef struct nxge_class_pt_cfg { 445 446 /* MAC table */ 447 nxge_mv_cfg_t mac_host_info[NXGE_MAX_MACS]; 448 449 /* VLAN table */ 450 nxge_mv_cfg_t vlan_tbl[NXGE_MAX_VLANS]; 451 /* class config value */ 452 uint32_t init_h1; 453 uint16_t init_h2; 454 uint8_t mcast_rdcgrp; 455 uint8_t mac_rdcgrp; 456 uint32_t class_cfg[TCAM_CLASS_MAX]; 457} nxge_class_pt_cfg_t, *p_nxge_class_pt_cfg_t; 458 459/* per Neptune sharable resources among ports */ 460typedef struct nxge_common { 461 uint32_t partition_id; 462 boolean_t mode32; 463 /* DMA Channels: RDC and TDC */ 464 nxge_rdc_cfg_t rdc_config[NXGE_MAX_RDCS]; 465 nxge_tdc_cfg_t tdc_config[NXGE_MAX_TDCS]; 466 nxge_dma_common_cfg_t dma_common_config; 467 468 uint32_t timer_res; 469 boolean_t ld_sys_error_set; 470 uint8_t sys_error_owner; 471 472 /* Layer 2/3/4 */ 473 uint16_t class2_etype; 474 uint16_t class3_etype; 475 476 /* FCRAM (hashing) */ 477 uint32_t hash1_initval; 478 uint32_t hash2_initval; 479} nxge_common_t, *p_nxge_common_t; 480 481/* 482 * Partition (logical domain) configuration per Neptune/NIU. 483 */ 484typedef struct nxge_part_cfg { 485 uint32_t rdc_grpbits; /* RDC group bit masks */ 486 uint32_t tdc_bitmap; /* bounded TDC */ 487 nxge_dma_pt_cfg_t pt_config[NXGE_MAX_PORTS]; 488 489 /* Flow Classification Partition (flow partition select register) */ 490 uint8_t hash_lookup; /* external lookup is available */ 491 uint8_t base_mask; /* select bits in base_h1 to replace */ 492 /* bits [19:15} in Hash 1. */ 493 uint8_t base_h1; /* value to replace Hash 1 [19:15]. */ 494 495 /* Add more here */ 496 uint32_t attributes; /* permission and attribute bits */ 497#define FZC_SERVICE_ENTITY 0x01 498#define FZC_READ_WRITE 0x02 499#define FZC_READ_ONLY 0x04 500} nxge_part_cfg_t, *p_nxge_part_cfg_t; 501 502typedef struct nxge_usr_l3_cls { 503 uint64_t cls; 504 uint16_t tcam_ref_cnt; 505 uint8_t pid; 506 uint8_t flow_pkt_type; 507 uint8_t valid; 508} nxge_usr_l3_cls_t, *p_nxge_usr_l3_cls_t; 509 510typedef struct nxge_hw_list { 511 struct nxge_hw_list *next; 512 nxge_os_mutex_t nxge_cfg_lock; 513 nxge_os_mutex_t nxge_tcam_lock; 514 nxge_os_mutex_t nxge_vlan_lock; 515 nxge_os_mutex_t nxge_mdio_lock; 516 517 nxge_dev_info_t *parent_devp; 518#if defined(sun4v) 519 /* 520 * With Hybrid I/O, a VR (virtualization region) is the moral 521 * equivalent of a device function as seen in the service domain. 522 * And, a guest domain can map up to 8 VRs for a single NIU for both 523 * of the physical ports. Hence, need space for up to the maximum 524 * number of VRs (functions) for the guest domain driver. 525 * 526 * For non-sun4v platforms, NXGE_MAX_PORTS provides the correct 527 * number of functions for the device. For sun4v platforms, 528 * NXGE_MAX_FUNCTIONS will be defined by the number of 529 * VRs that the guest domain can map. 530 * 531 * NOTE: This solution only works for one NIU and will need to 532 * revisit this for KT-NIU. 533 */ 534#define NXGE_MAX_GUEST_FUNCTIONS 8 535#define NXGE_MAX_FUNCTIONS NXGE_MAX_GUEST_FUNCTIONS 536#else 537#define NXGE_MAX_FUNCTIONS NXGE_MAX_PORTS 538#endif 539 struct _nxge_t *nxge_p[NXGE_MAX_FUNCTIONS]; 540 uint32_t ndevs; 541 uint32_t flags; 542 uint32_t magic; 543 uint32_t niu_type; 544 uint32_t platform_type; 545 uint8_t xcvr_addr[NXGE_MAX_PORTS]; 546 uintptr_t hio; 547 void *tcam; 548 uint32_t tcam_size; 549 uint64_t tcam_l2_prog_cls[NXGE_L2_PROG_CLS]; 550 nxge_usr_l3_cls_t tcam_l3_prog_cls[NXGE_L3_PROG_CLS]; 551} nxge_hw_list_t, *p_nxge_hw_list_t; 552 553#ifdef __cplusplus 554} 555#endif 556 557#endif /* _SYS_NXGE_NXGE_COMMON_H */ 558