oce_hw_eth.h revision 11374:b345d20da176
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * header file containing the data structure definitions for the NIC 29 * subsystetm 30 */ 31 32#ifndef _OCE_HW_ETH_H_ 33#define _OCE_HW_ETH_H_ 34 35#ifdef __cplusplus 36extern "C" { 37#endif 38 39#include <oce_hw.h> 40 41#define NIC_WQE_SIZE 16 42/* NIC packet type */ 43#define NIC_UNICAST 0x00 44#define NIC_MULTICAST 0x01 45#define NIC_BROADCAST 0x02 46 47/* HDS type */ 48#define NIC_HDS_NO_SPLIT 0x00 49#define NIC_HDS_SPLIT_L3PL 0x01 50#define NIC_HDS_SPLIT_L4PL 0x02 51 52/* NIC WQ types */ 53#define NIC_WQ_TYPE_FORWARDING 0x01 54#define NIC_WQ_TYPE_STANDARD 0x02 55#define NIC_WQ_TYPE_LOW_LATENCY 0x04 56 57#pragma pack(1) 58enum { 59 OPCODE_CONFIG_NIC_RSS = 1, 60 OPCODE_CONFIG_NIC_ACPI = 2, 61 OPCODE_CONFIG_NIC_PROMISCUOUS = 3, 62 OPCODE_GET_NIC_STATS = 4, 63 OPCODE_CREATE_NIC_WQ = 7, 64 OPCODE_CREATE_NIC_RQ = 8, 65 OPCODE_DELETE_NIC_WQ = 9, 66 OPCODE_DELETE_NIC_RQ = 10, 67 OPCODE_CREATE_NIC_RSS_CQ = 11, 68 OPCODE_DELETE_NIC_RSS_CQ = 12, 69 OPCODE_SET_RSS_EQ_MSI = 13, 70 OPCODE_CREATE_NIC_HDS_RQ = 14, 71 OPCODE_DELETE_NIC_HDS_RQ = 15, 72 OPCODE_CONFIG_NIC_RSS_ADVANCED = 16 73}; 74 75/* NIC header WQE */ 76struct oce_nic_hdr_wqe { 77 union { 78 struct { 79#ifdef _BIG_ENDIAN 80 /* dw0 */ 81 uint32_t rsvd0; 82 83 /* dw1 */ 84 uint32_t last_seg_udp_len:14; 85 uint32_t rsvd1:18; 86 87 /* dw2 */ 88 uint32_t lso_mss:14; 89 uint32_t num_wqe:5; 90 uint32_t rsvd4:2; 91 uint32_t vlan:1; 92 uint32_t lso:1; 93 uint32_t tcpcs:1; 94 uint32_t udpcs:1; 95 uint32_t ipcs:1; 96 uint32_t rsvd3:1; 97 uint32_t rsvd2:1; 98 uint32_t forward:1; 99 uint32_t crc:1; 100 uint32_t event:1; 101 uint32_t complete:1; 102 103 /* dw3 */ 104 uint32_t vlan_tag:16; 105 uint32_t total_length:16; 106#else 107 /* dw0 */ 108 uint32_t rsvd0; 109 110 /* dw1 */ 111 uint32_t rsvd1:18; 112 uint32_t last_seg_udp_len:14; 113 114 /* dw2 */ 115 uint32_t complete:1; 116 uint32_t event:1; 117 uint32_t crc:1; 118 uint32_t forward:1; 119 uint32_t rsvd2:1; 120 uint32_t rsvd3:1; 121 uint32_t ipcs:1; 122 uint32_t udpcs:1; 123 uint32_t tcpcs:1; 124 uint32_t lso:1; 125 uint32_t vlan:1; 126 uint32_t rsvd4:2; 127 uint32_t num_wqe:5; 128 uint32_t lso_mss:14; 129 130 /* dw3 */ 131 uint32_t total_length:16; 132 uint32_t vlan_tag:16; 133#endif 134 }s; 135 uint32_t dw[4]; 136 }u0; 137}; 138 139/* NIC fragment WQE */ 140struct oce_nic_frag_wqe { 141 union { 142 struct { 143 /* dw0 */ 144 uint32_t frag_pa_hi; 145 /* dw1 */ 146 uint32_t frag_pa_lo; 147 /* dw2 */ 148 uint32_t rsvd0; 149 uint32_t frag_len; 150 }s; 151 uint32_t dw[4]; 152 }u0; 153}; 154 155/* Ethernet Tx Completion Descriptor */ 156struct oce_nic_tx_cqe { 157 union { 158 struct { 159#ifdef _BIG_ENDIAN 160 /* dw 0 */ 161 uint32_t status:4; 162 uint32_t rsvd0:8; 163 uint32_t port:2; 164 uint32_t ct:2; 165 uint32_t wqe_index:16; 166 167 /* dw 1 */ 168 uint32_t rsvd1:5; 169 uint32_t cast_enc:2; 170 uint32_t lso:1; 171 uint32_t nwh_bytes:8; 172 uint32_t user_bytes:16; 173 174 /* dw 2 */ 175 uint32_t rsvd2; 176 177 178 /* dw 3 */ 179 uint32_t valid:1; 180 uint32_t rsvd3:4; 181 uint32_t wq_id:11; 182 uint32_t num_pkts:16; 183#else 184 /* dw 0 */ 185 uint32_t wqe_index:16; 186 uint32_t ct:2; 187 uint32_t port:2; 188 uint32_t rsvd0:8; 189 uint32_t status:4; 190 191 /* dw 1 */ 192 uint32_t user_bytes:16; 193 uint32_t nwh_bytes:8; 194 uint32_t lso:1; 195 uint32_t cast_enc:2; 196 uint32_t rsvd1:5; 197 /* dw 2 */ 198 uint32_t rsvd2; 199 200 /* dw 3 */ 201 uint32_t num_pkts:16; 202 uint32_t wq_id:11; 203 uint32_t rsvd3:4; 204 uint32_t valid:1; 205#endif 206 }s; 207 uint32_t dw[4]; 208 }u0; 209}; 210#define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) 211#define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) 212 213/* Receive Queue Entry (RQE) */ 214struct oce_nic_rqe { 215 union { 216 struct { 217 uint32_t frag_pa_hi; 218 uint32_t frag_pa_lo; 219 }s; 220 uint32_t dw[2]; 221 }u0; 222}; 223 224/* NIC Receive CQE */ 225struct oce_nic_rx_cqe { 226 union { 227 struct { 228#ifdef _BIG_ENDIAN 229 /* dw 0 */ 230 uint32_t ip_options:1; 231 uint32_t port:1; 232 uint32_t pkt_size:14; 233 uint32_t vlan_tag:16; 234 235 /* dw 1 */ 236 uint32_t num_fragments:3; 237 uint32_t switched:1; 238 uint32_t ct:2; 239 uint32_t frag_index:10; 240 uint32_t rsvd0:1; 241 uint32_t vlan_tag_present:1; 242 uint32_t mac_dst:6; 243 uint32_t ip6_frame:1; 244 uint32_t l4_cksum_pass:1; 245 uint32_t ip_cksum_pass:1; 246 uint32_t udpframe:1; 247 uint32_t tcpframe:1; 248 uint32_t ip4_frame:1; 249 uint32_t rss_hp:1; 250 uint32_t error:1; 251 252 /* dw 2 */ 253 uint32_t valid:1; 254 uint32_t hds_type:2; 255 uint32_t lro_pkt:1; 256 uint32_t rsvd4:1; 257 uint32_t hds_hdr_size:12; 258 uint32_t hds_hdr_frag_index:10; 259 uint32_t rss_bank:1; 260 uint32_t qnq:1; 261 uint32_t pkt_type:2; 262 uint32_t rss_flush:1; 263 264 /* dw 3 */ 265 uint32_t rss_hash_value; 266#else 267 /* dw 0 */ 268 uint32_t vlan_tag:16; 269 uint32_t pkt_size:14; 270 uint32_t port:1; 271 uint32_t ip_options:1; 272 /* dw 1 */ 273 uint32_t error:1; 274 uint32_t rss_hp:1; 275 uint32_t ip4_frame:1; 276 uint32_t tcpframe:1; 277 uint32_t udpframe:1; 278 uint32_t ip_cksum_pass:1; 279 uint32_t l4_cksum_pass:1; 280 uint32_t ip6_frame:1; 281 uint32_t mac_dst:6; 282 uint32_t vlan_tag_present:1; 283 uint32_t rsvd0:1; 284 uint32_t frag_index:10; 285 uint32_t ct:2; 286 uint32_t switched:1; 287 uint32_t num_fragments:3; 288 289 /* dw 2 */ 290 uint32_t rss_flush:1; 291 uint32_t pkt_type:2; 292 uint32_t qnq:1; 293 uint32_t rss_bank:1; 294 uint32_t hds_hdr_frag_index:10; 295 uint32_t hds_hdr_size:12; 296 uint32_t rsvd4:1; 297 uint32_t lro_pkt:1; 298 uint32_t hds_type:2; 299 uint32_t valid:1; 300 /* dw 3 */ 301 uint32_t rss_hash_value; 302#endif 303 }s; 304 uint32_t dw[4]; 305 }u0; 306}; 307#define RQ_CQE_VALID_MASK 0x80 308#define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2]) 309#define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0) 310 311struct mbx_config_nic_promiscuous { 312 struct mbx_hdr hdr; 313 union { 314 struct { 315#ifdef _BIG_ENDIAN 316 uint16_t rsvd0; 317 uint8_t port1_promisc; 318 uint8_t port0_promisc; 319#else 320 uint8_t port0_promisc; 321 uint8_t port1_promisc; 322 uint16_t rsvd0; 323#endif 324 }req; 325 326 struct { 327 uint32_t rsvd0; 328 }rsp; 329 }params; 330}; 331 332/* [07] OPCODE_CREATE_NIC_WQ */ 333struct mbx_create_nic_wq { 334 335 /* dw0 - dw3 */ 336 struct mbx_hdr hdr; 337 union { 338 struct { 339#ifdef _BIG_ENDIAN 340 /* dw4 */ 341 uint8_t rsvd1; 342 uint8_t nic_wq_type; 343 uint8_t rsvd0; 344 uint8_t num_pages; 345 346 /* dw5 */ 347 uint32_t rsvd3:12; 348 uint32_t wq_size:4; 349 uint32_t rsvd2:16; 350 351 /* dw6 */ 352 uint32_t valid:1; 353 uint32_t pd_id:9; 354 uint32_t pci_function_id:8; 355 uint32_t rsvd4:14; 356 357 /* dw7 */ 358 uint32_t rsvd5:16; 359 uint32_t cq_id:16; 360#else 361 /* dw4 */ 362 uint8_t num_pages; 363 uint8_t rsvd0; 364 uint8_t nic_wq_type; 365 uint8_t rsvd1; 366 367 /* dw5 */ 368 uint32_t rsvd2:16; 369 uint32_t wq_size:4; 370 uint32_t rsvd3:12; 371 372 /* dw6 */ 373 uint32_t rsvd4:14; 374 uint32_t pci_function_id:8; 375 uint32_t pd_id:9; 376 uint32_t valid:1; 377 378 /* dw7 */ 379 uint32_t cq_id:16; 380 uint32_t rsvd5:16; 381#endif 382 /* dw8 - dw20 */ 383 uint32_t rsvd6[13]; 384 /* dw21 - dw36 */ 385 struct phys_addr pages[8]; 386 }req; 387 388 struct { 389 uint16_t wq_id; 390 uint16_t rsvd0; 391 }rsp; 392 }params; 393}; 394 395/* [09] OPCODE_DELETE_NIC_WQ */ 396struct mbx_delete_nic_wq { 397 /* dw0 - dw3 */ 398 struct mbx_hdr hdr; 399 union { 400 struct { 401#ifdef _BIG_ENDIAN 402 /* dw4 */ 403 uint16_t rsvd0; 404 uint16_t wq_id; 405#else 406 /* dw4 */ 407 uint16_t wq_id; 408 uint16_t rsvd0; 409#endif 410 }req; 411 struct { 412 uint32_t rsvd0; 413 }rsp; 414 }params; 415}; 416 417/* [08] OPCODE_CREATE_NIC_RQ */ 418struct mbx_create_nic_rq { 419 /* dw0 - dw3 */ 420 struct mbx_hdr hdr; 421 union { 422 struct { 423#ifdef _BIG_ENDIAN 424 /* dw4 */ 425 uint8_t num_pages; 426 uint8_t frag_size; 427 uint16_t cq_id; 428#else 429 /* dw4 */ 430 uint16_t cq_id; 431 uint8_t frag_size; 432 uint8_t num_pages; 433#endif 434 /* dw5 - dw8 */ 435 struct phys_addr pages[2]; 436 /* dw9 */ 437 uint32_t if_id; 438#ifdef _BIG_ENDIAN 439 /* dw10 */ 440 uint16_t rsvd0; 441 uint16_t max_frame_size; 442#else 443 /* dw10 */ 444 uint16_t max_frame_size; 445 uint16_t rsvd0; 446#endif 447 /* dw11 */ 448 uint32_t is_rss_queue; 449 }req; 450 451 struct { 452 /* dw4 */ 453 union { 454 struct { 455 uint16_t rq_id; 456 uint8_t rss_cpuid; 457 uint8_t rsvd0; 458 } s; 459 uint32_t dw4; 460 }u0; 461 }rsp; 462 }params; 463}; 464 465/* [10] OPCODE_DELETE_NIC_RQ */ 466struct mbx_delete_nic_rq { 467 /* dw0 - dw3 */ 468 struct mbx_hdr hdr; 469 union { 470 struct { 471#ifdef _BIG_ENDIAN 472 /* dw4 */ 473 uint16_t bypass_flush; 474 uint16_t rq_id; 475#else 476 /* dw4 */ 477 uint16_t rq_id; 478 uint16_t bypass_flush; 479#endif 480 }req; 481 482 struct { 483 /* dw4 */ 484 uint32_t rsvd0; 485 }rsp; 486 }params; 487}; 488 489struct rx_port_stats { 490 uint32_t rx_bytes_lsd; 491 uint32_t rx_bytes_msd; 492 uint32_t rx_total_frames; 493 uint32_t rx_unicast_frames; 494 uint32_t rx_multicast_frames; 495 uint32_t rx_broadcast_frames; 496 uint32_t rx_crc_errors; 497 uint32_t rx_alignment_symbol_errors; 498 uint32_t rx_pause_frames; 499 uint32_t rx_control_frames; 500 uint32_t rx_in_range_errors; 501 uint32_t rx_out_range_errors; 502 uint32_t rx_frame_too_long; 503 uint32_t rx_address_match_errors; 504 uint32_t rx_vlan_mismatch; 505 uint32_t rx_dropped_too_small; 506 uint32_t rx_dropped_too_short; 507 uint32_t rx_dropped_header_too_small; 508 uint32_t rx_dropped_tcp_length; 509 uint32_t rx_dropped_runt; 510 uint32_t rx_64_byte_packets; 511 uint32_t rx_65_127_byte_packets; 512 uint32_t rx_128_256_byte_packets; 513 uint32_t rx_256_511_byte_packets; 514 uint32_t rx_512_1023_byte_packets; 515 uint32_t rx_1024_1518_byte_packets; 516 uint32_t rx_1519_2047_byte_packets; 517 uint32_t rx_2048_4095_byte_packets; 518 uint32_t rx_4096_8191_byte_packets; 519 uint32_t rx_8192_9216_byte_packets; 520 uint32_t rx_ip_checksum_errs; 521 uint32_t rx_tcp_checksum_errs; 522 uint32_t rx_udp_checksum_errs; 523 uint32_t rx_non_rss_packets; 524 uint32_t rx_ipv4_packets; 525 uint32_t rx_ipv6_packets; 526 uint32_t rx_ipv4_bytes_lsd; 527 uint32_t rx_ipv4_bytes_msd; 528 uint32_t rx_ipv6_bytes_lsd; 529 uint32_t rx_ipv6_bytes_msd; 530 uint32_t rx_chute1_packets; 531 uint32_t rx_chute2_packets; 532 uint32_t rx_chute3_packets; 533 uint32_t rx_management_packets; 534 uint32_t rx_switched_unicast_packets; 535 uint32_t rx_switched_multicast_packets; 536 uint32_t rx_switched_broadcast_packets; 537 uint32_t tx_bytes_lsd; 538 uint32_t tx_bytes_msd; 539 uint32_t tx_unicast_frames; 540 uint32_t tx_multicast_frames; 541 uint32_t tx_broadcast_frames; 542 uint32_t tx_pause_frames; 543 uint32_t tx_control_frames; 544 uint32_t tx_64_byte_packets; 545 uint32_t tx_65_127_byte_packets; 546 uint32_t tx_128_256_byte_packets; 547 uint32_t tx_256_511_byte_packets; 548 uint32_t tx_512_1023_byte_packets; 549 uint32_t tx_1024_1518_byte_packets; 550 uint32_t tx_1519_2047_byte_packets; 551 uint32_t tx_2048_4095_byte_packets; 552 uint32_t tx_4096_8191_byte_packets; 553 uint32_t tx_8192_9216_byte_packets; 554 uint32_t rx_fifo_overflow; 555 uint32_t rx_input_fifo_overflow; 556}; 557 558struct rx_stats { 559 /* dw 0-131 --2 X 66 */ 560 struct rx_port_stats port[2]; 561 /* dw 132-147 --16 */ 562 uint32_t rx_drops_no_pbuf; 563 uint32_t rx_drops_no_txpb; 564 uint32_t rx_drops_no_erx_descr; 565 uint32_t rx_drops_no_tpre_descr; 566 uint32_t management_rx_port_packets; 567 uint32_t management_rx_port_bytes; 568 uint32_t management_rx_port_pause_frames; 569 uint32_t management_rx_port_errors; 570 uint32_t management_tx_port_packets; 571 uint32_t management_tx_port_bytes; 572 uint32_t management_tx_port_pause; 573 uint32_t management_rx_port_rxfifo_overflow; 574 uint32_t rx_drops_too_many_frags; 575 uint32_t rx_drops_invalid_ring; 576 uint32_t forwarded_packets; 577 uint32_t rx_drops_mtu; 578 /* fcoe is not relevent */ 579 uint32_t rsvd[15]; 580}; 581 582struct tx_counter { 583 uint32_t pkts; 584 uint32_t lsd; 585 uint32_t msd; 586}; 587 588struct tx_stats { 589 struct tx_counter ct1pt0_xmt_ipv4_ctrs; 590 struct tx_counter ct1pt0_xmt_ipv6_ctrs; 591 struct tx_counter ct1pt0_rexmt_ipv4_ctrs; 592 struct tx_counter ct1pt0_rexmt_ipv6_ctrs; 593 struct tx_counter ct1pt1_xmt_ipv4_ctrs; 594 struct tx_counter ct1pt1_xmt_ipv6_ctrs; 595 struct tx_counter ct1pt1_rexmt_ipv4_ctrs; 596 struct tx_counter ct1pt1_rexmt_ipv6_ctrs; 597 struct tx_counter ct2pt0_xmt_ipv4_ctrs; 598 struct tx_counter ct2pt0_xmt_ipv6_ctrs; 599 struct tx_counter ct2pt0_rexmt_ipv4_ctrs; 600 struct tx_counter ct2pt0_rexmt_ipv6_ctrs; 601 struct tx_counter ct2pt1_xmt_ipv4_ctrs; 602 struct tx_counter ct2pt1_xmt_ipv6_ctrs; 603 struct tx_counter ct2pt1_rexmt_ipv4_ctrs; 604 struct tx_counter ct2pt1_rexmt_ipv6_ctrs; 605}; 606 607struct rx_err_stats { 608 uint32_t rx_drops_no_fragments[44]; 609 uint32_t debug_wdma_sent_hold; 610 uint32_t debug_wdma_pbfree_sent_hold; 611 uint32_t debug_wdma_zerobyte_pbfree_sent_hold; 612 uint32_t debug_pmem_pbuf_dealloc; 613}; 614 615struct mem_stats { 616 uint32_t eth_red_drops; 617 uint32_t lro_red_drops; 618 uint32_t ulp0_red_drops; 619 uint32_t ulp1_red_drops; 620}; 621 622/* [04] OPCODE_GET_NIC_STATS */ 623struct mbx_get_nic_stats { 624 /* dw0 - dw3 */ 625 struct mbx_hdr hdr; 626 union { 627 struct { 628 uint32_t rsvd0; 629 }req; 630 631 struct { 632 struct rx_stats rx; 633 struct tx_stats tx; 634 struct rx_err_stats err_rx; 635 struct mem_stats mem; 636 }rsp; 637 }params; 638}; 639 640#pragma pack() 641 642#ifdef __cplusplus 643} 644#endif 645 646#endif /* _OCE_HW_ETH_H_ */ 647