1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * header file containing the data structure definitions for the NIC 29 * subsystetm 30 */ 31 32#ifndef _OCE_HW_ETH_H_ 33#define _OCE_HW_ETH_H_ 34 35#ifdef __cplusplus 36extern "C" { 37#endif 38 39#include <oce_hw.h> 40 41#define NIC_WQE_SIZE 16 42/* NIC packet type */ 43#define NIC_UNICAST 0x00 44#define NIC_MULTICAST 0x01 45#define NIC_BROADCAST 0x02 46 47/* HDS type */ 48#define NIC_HDS_NO_SPLIT 0x00 49#define NIC_HDS_SPLIT_L3PL 0x01 50#define NIC_HDS_SPLIT_L4PL 0x02 51 52/* NIC WQ types */ 53#define NIC_WQ_TYPE_FORWARDING 0x01 54#define NIC_WQ_TYPE_STANDARD 0x02 55#define NIC_WQ_TYPE_LOW_LATENCY 0x04 56 57#pragma pack(1) 58enum { 59 OPCODE_CONFIG_NIC_RSS = 1, 60 OPCODE_CONFIG_NIC_ACPI = 2, 61 OPCODE_CONFIG_NIC_PROMISCUOUS = 3, 62 OPCODE_GET_NIC_STATS = 4, 63 OPCODE_CREATE_NIC_WQ = 7, 64 OPCODE_CREATE_NIC_RQ = 8, 65 OPCODE_DELETE_NIC_WQ = 9, 66 OPCODE_DELETE_NIC_RQ = 10, 67 OPCODE_CREATE_NIC_RSS_CQ = 11, 68 OPCODE_DELETE_NIC_RSS_CQ = 12, 69 OPCODE_SET_RSS_EQ_MSI = 13, 70 OPCODE_CREATE_NIC_HDS_RQ = 14, 71 OPCODE_DELETE_NIC_HDS_RQ = 15, 72 OPCODE_CONFIG_NIC_RSS_ADVANCED = 16 73}; 74 75enum { 76 RSS_ENABLE_NONE = 0x0, /* (No RSS) */ 77 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */ 78 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */ 79 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */ 80 RSS_ENABLE_TCP_IPV6 = 0x8 /* (TCP IPV6 HASH */ 81 82}; 83/* NIC header WQE */ 84struct oce_nic_hdr_wqe { 85 union { 86 struct { 87#ifdef _BIG_ENDIAN 88 /* dw0 */ 89 uint32_t rsvd0; 90 91 /* dw1 */ 92 uint32_t last_seg_udp_len:14; 93 uint32_t rsvd1:18; 94 95 /* dw2 */ 96 uint32_t lso_mss:14; 97 uint32_t num_wqe:5; 98 uint32_t rsvd4:2; 99 uint32_t vlan:1; 100 uint32_t lso:1; 101 uint32_t tcpcs:1; 102 uint32_t udpcs:1; 103 uint32_t ipcs:1; 104 uint32_t rsvd3:1; 105 uint32_t rsvd2:1; 106 uint32_t forward:1; 107 uint32_t crc:1; 108 uint32_t event:1; 109 uint32_t complete:1; 110 111 /* dw3 */ 112 uint32_t vlan_tag:16; 113 uint32_t total_length:16; 114#else 115 /* dw0 */ 116 uint32_t rsvd0; 117 118 /* dw1 */ 119 uint32_t rsvd1:18; 120 uint32_t last_seg_udp_len:14; 121 122 /* dw2 */ 123 uint32_t complete:1; 124 uint32_t event:1; 125 uint32_t crc:1; 126 uint32_t forward:1; 127 uint32_t rsvd2:1; 128 uint32_t rsvd3:1; 129 uint32_t ipcs:1; 130 uint32_t udpcs:1; 131 uint32_t tcpcs:1; 132 uint32_t lso:1; 133 uint32_t vlan:1; 134 uint32_t rsvd4:2; 135 uint32_t num_wqe:5; 136 uint32_t lso_mss:14; 137 138 /* dw3 */ 139 uint32_t total_length:16; 140 uint32_t vlan_tag:16; 141#endif 142 }s; 143 uint32_t dw[4]; 144 }u0; 145}; 146 147/* NIC fragment WQE */ 148struct oce_nic_frag_wqe { 149 union { 150 struct { 151 /* dw0 */ 152 uint32_t frag_pa_hi; 153 /* dw1 */ 154 uint32_t frag_pa_lo; 155 /* dw2 */ 156 uint32_t rsvd0; 157 uint32_t frag_len; 158 }s; 159 uint32_t dw[4]; 160 }u0; 161}; 162 163/* Ethernet Tx Completion Descriptor */ 164struct oce_nic_tx_cqe { 165 union { 166 struct { 167#ifdef _BIG_ENDIAN 168 /* dw 0 */ 169 uint32_t status:4; 170 uint32_t rsvd0:8; 171 uint32_t port:2; 172 uint32_t ct:2; 173 uint32_t wqe_index:16; 174 175 /* dw 1 */ 176 uint32_t rsvd1:5; 177 uint32_t cast_enc:2; 178 uint32_t lso:1; 179 uint32_t nwh_bytes:8; 180 uint32_t user_bytes:16; 181 182 /* dw 2 */ 183 uint32_t rsvd2; 184 185 186 /* dw 3 */ 187 uint32_t valid:1; 188 uint32_t rsvd3:4; 189 uint32_t wq_id:11; 190 uint32_t num_pkts:16; 191#else 192 /* dw 0 */ 193 uint32_t wqe_index:16; 194 uint32_t ct:2; 195 uint32_t port:2; 196 uint32_t rsvd0:8; 197 uint32_t status:4; 198 199 /* dw 1 */ 200 uint32_t user_bytes:16; 201 uint32_t nwh_bytes:8; 202 uint32_t lso:1; 203 uint32_t cast_enc:2; 204 uint32_t rsvd1:5; 205 /* dw 2 */ 206 uint32_t rsvd2; 207 208 /* dw 3 */ 209 uint32_t num_pkts:16; 210 uint32_t wq_id:11; 211 uint32_t rsvd3:4; 212 uint32_t valid:1; 213#endif 214 }s; 215 uint32_t dw[4]; 216 }u0; 217}; 218#define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) 219#define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) 220 221/* Receive Queue Entry (RQE) */ 222struct oce_nic_rqe { 223 union { 224 struct { 225 uint32_t frag_pa_hi; 226 uint32_t frag_pa_lo; 227 }s; 228 uint32_t dw[2]; 229 }u0; 230}; 231 232/* NIC Receive CQE */ 233struct oce_nic_rx_cqe { 234 union { 235 struct { 236#ifdef _BIG_ENDIAN 237 /* dw 0 */ 238 uint32_t ip_options:1; 239 uint32_t port:1; 240 uint32_t pkt_size:14; 241 uint32_t vlan_tag:16; 242 243 /* dw 1 */ 244 uint32_t num_fragments:3; 245 uint32_t switched:1; 246 uint32_t ct:2; 247 uint32_t frag_index:10; 248 uint32_t rsvd0:1; 249 uint32_t vlan_tag_present:1; 250 uint32_t mac_dst:6; 251 uint32_t ip_ver:1; 252 uint32_t l4_cksum_pass:1; 253 uint32_t ip_cksum_pass:1; 254 uint32_t udpframe:1; 255 uint32_t tcpframe:1; 256 uint32_t ipframe:1; 257 uint32_t rss_hp:1; 258 uint32_t error:1; 259 260 /* dw 2 */ 261 uint32_t valid:1; 262 uint32_t hds_type:2; 263 uint32_t lro_pkt:1; 264 uint32_t rsvd4:1; 265 uint32_t hds_hdr_size:12; 266 uint32_t hds_hdr_frag_index:10; 267 uint32_t rss_bank:1; 268 uint32_t qnq:1; 269 uint32_t pkt_type:2; 270 uint32_t rss_flush:1; 271 272 /* dw 3 */ 273 uint32_t rss_hash_value; 274#else 275 /* dw 0 */ 276 uint32_t vlan_tag:16; 277 uint32_t pkt_size:14; 278 uint32_t port:1; 279 uint32_t ip_options:1; 280 /* dw 1 */ 281 uint32_t error:1; 282 uint32_t rss_hp:1; 283 uint32_t ipframe:1; 284 uint32_t tcpframe:1; 285 uint32_t udpframe:1; 286 uint32_t ip_cksum_pass:1; 287 uint32_t l4_cksum_pass:1; 288 uint32_t ip_ver:1; 289 uint32_t mac_dst:6; 290 uint32_t vlan_tag_present:1; 291 uint32_t rsvd0:1; 292 uint32_t frag_index:10; 293 uint32_t ct:2; 294 uint32_t switched:1; 295 uint32_t num_fragments:3; 296 297 /* dw 2 */ 298 uint32_t rss_flush:1; 299 uint32_t pkt_type:2; 300 uint32_t qnq:1; 301 uint32_t rss_bank:1; 302 uint32_t hds_hdr_frag_index:10; 303 uint32_t hds_hdr_size:12; 304 uint32_t rsvd4:1; 305 uint32_t lro_pkt:1; 306 uint32_t hds_type:2; 307 uint32_t valid:1; 308 /* dw 3 */ 309 uint32_t rss_hash_value; 310#endif 311 }s; 312 uint32_t dw[4]; 313 }u0; 314}; 315#define RQ_CQE_VALID_MASK 0x80 316#define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2]) 317#define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0) 318 319struct mbx_config_nic_promiscuous { 320 struct mbx_hdr hdr; 321 union { 322 struct { 323#ifdef _BIG_ENDIAN 324 uint16_t rsvd0; 325 uint8_t port1_promisc; 326 uint8_t port0_promisc; 327#else 328 uint8_t port0_promisc; 329 uint8_t port1_promisc; 330 uint16_t rsvd0; 331#endif 332 }req; 333 334 struct { 335 uint32_t rsvd0; 336 }rsp; 337 }params; 338}; 339 340/* [07] OPCODE_CREATE_NIC_WQ */ 341struct mbx_create_nic_wq { 342 343 /* dw0 - dw3 */ 344 struct mbx_hdr hdr; 345 union { 346 struct { 347#ifdef _BIG_ENDIAN 348 /* dw4 */ 349 uint8_t rsvd1; 350 uint8_t nic_wq_type; 351 uint8_t rsvd0; 352 uint8_t num_pages; 353 354 /* dw5 */ 355 uint32_t rsvd3:12; 356 uint32_t wq_size:4; 357 uint32_t rsvd2:16; 358 359 /* dw6 */ 360 uint32_t valid:1; 361 uint32_t pd_id:9; 362 uint32_t pci_function_id:8; 363 uint32_t rsvd4:14; 364 365 /* dw7 */ 366 uint32_t rsvd5:16; 367 uint32_t cq_id:16; 368#else 369 /* dw4 */ 370 uint8_t num_pages; 371 uint8_t rsvd0; 372 uint8_t nic_wq_type; 373 uint8_t rsvd1; 374 375 /* dw5 */ 376 uint32_t rsvd2:16; 377 uint32_t wq_size:4; 378 uint32_t rsvd3:12; 379 380 /* dw6 */ 381 uint32_t rsvd4:14; 382 uint32_t pci_function_id:8; 383 uint32_t pd_id:9; 384 uint32_t valid:1; 385 386 /* dw7 */ 387 uint32_t cq_id:16; 388 uint32_t rsvd5:16; 389#endif 390 /* dw8 - dw20 */ 391 uint32_t rsvd6[13]; 392 /* dw21 - dw36 */ 393 struct phys_addr pages[8]; 394 }req; 395 396 struct { 397 uint16_t wq_id; 398 uint16_t rsvd0; 399 }rsp; 400 }params; 401}; 402 403/* [09] OPCODE_DELETE_NIC_WQ */ 404struct mbx_delete_nic_wq { 405 /* dw0 - dw3 */ 406 struct mbx_hdr hdr; 407 union { 408 struct { 409#ifdef _BIG_ENDIAN 410 /* dw4 */ 411 uint16_t rsvd0; 412 uint16_t wq_id; 413#else 414 /* dw4 */ 415 uint16_t wq_id; 416 uint16_t rsvd0; 417#endif 418 }req; 419 struct { 420 uint32_t rsvd0; 421 }rsp; 422 }params; 423}; 424 425/* [08] OPCODE_CREATE_NIC_RQ */ 426struct mbx_create_nic_rq { 427 /* dw0 - dw3 */ 428 struct mbx_hdr hdr; 429 union { 430 struct { 431#ifdef _BIG_ENDIAN 432 /* dw4 */ 433 uint8_t num_pages; 434 uint8_t frag_size; 435 uint16_t cq_id; 436#else 437 /* dw4 */ 438 uint16_t cq_id; 439 uint8_t frag_size; 440 uint8_t num_pages; 441#endif 442 /* dw5 - dw8 */ 443 struct phys_addr pages[2]; 444 /* dw9 */ 445 uint32_t if_id; 446#ifdef _BIG_ENDIAN 447 /* dw10 */ 448 uint16_t rsvd0; 449 uint16_t max_frame_size; 450#else 451 /* dw10 */ 452 uint16_t max_frame_size; 453 uint16_t rsvd0; 454#endif 455 /* dw11 */ 456 uint32_t is_rss_queue; 457 }req; 458 459 struct { 460 /* dw4 */ 461 union { 462 struct { 463 uint16_t rq_id; 464 uint8_t rss_cpuid; 465 uint8_t rsvd0; 466 } s; 467 uint32_t dw4; 468 }u0; 469 }rsp; 470 }params; 471}; 472 473/* [10] OPCODE_DELETE_NIC_RQ */ 474struct mbx_delete_nic_rq { 475 /* dw0 - dw3 */ 476 struct mbx_hdr hdr; 477 union { 478 struct { 479#ifdef _BIG_ENDIAN 480 /* dw4 */ 481 uint16_t bypass_flush; 482 uint16_t rq_id; 483#else 484 /* dw4 */ 485 uint16_t rq_id; 486 uint16_t bypass_flush; 487#endif 488 }req; 489 490 struct { 491 /* dw4 */ 492 uint32_t rsvd0; 493 }rsp; 494 }params; 495}; 496 497struct rx_port_stats { 498 uint32_t rx_bytes_lsd; 499 uint32_t rx_bytes_msd; 500 uint32_t rx_total_frames; 501 uint32_t rx_unicast_frames; 502 uint32_t rx_multicast_frames; 503 uint32_t rx_broadcast_frames; 504 uint32_t rx_crc_errors; 505 uint32_t rx_alignment_symbol_errors; 506 uint32_t rx_pause_frames; 507 uint32_t rx_control_frames; 508 uint32_t rx_in_range_errors; 509 uint32_t rx_out_range_errors; 510 uint32_t rx_frame_too_long; 511 uint32_t rx_address_match_errors; 512 uint32_t rx_vlan_mismatch; 513 uint32_t rx_dropped_too_small; 514 uint32_t rx_dropped_too_short; 515 uint32_t rx_dropped_header_too_small; 516 uint32_t rx_dropped_tcp_length; 517 uint32_t rx_dropped_runt; 518 uint32_t rx_64_byte_packets; 519 uint32_t rx_65_127_byte_packets; 520 uint32_t rx_128_256_byte_packets; 521 uint32_t rx_256_511_byte_packets; 522 uint32_t rx_512_1023_byte_packets; 523 uint32_t rx_1024_1518_byte_packets; 524 uint32_t rx_1519_2047_byte_packets; 525 uint32_t rx_2048_4095_byte_packets; 526 uint32_t rx_4096_8191_byte_packets; 527 uint32_t rx_8192_9216_byte_packets; 528 uint32_t rx_ip_checksum_errs; 529 uint32_t rx_tcp_checksum_errs; 530 uint32_t rx_udp_checksum_errs; 531 uint32_t rx_non_rss_packets; 532 uint32_t rx_ipv4_packets; 533 uint32_t rx_ipv6_packets; 534 uint32_t rx_ipv4_bytes_lsd; 535 uint32_t rx_ipv4_bytes_msd; 536 uint32_t rx_ipv6_bytes_lsd; 537 uint32_t rx_ipv6_bytes_msd; 538 uint32_t rx_chute1_packets; 539 uint32_t rx_chute2_packets; 540 uint32_t rx_chute3_packets; 541 uint32_t rx_management_packets; 542 uint32_t rx_switched_unicast_packets; 543 uint32_t rx_switched_multicast_packets; 544 uint32_t rx_switched_broadcast_packets; 545 uint32_t tx_bytes_lsd; 546 uint32_t tx_bytes_msd; 547 uint32_t tx_unicast_frames; 548 uint32_t tx_multicast_frames; 549 uint32_t tx_broadcast_frames; 550 uint32_t tx_pause_frames; 551 uint32_t tx_control_frames; 552 uint32_t tx_64_byte_packets; 553 uint32_t tx_65_127_byte_packets; 554 uint32_t tx_128_256_byte_packets; 555 uint32_t tx_256_511_byte_packets; 556 uint32_t tx_512_1023_byte_packets; 557 uint32_t tx_1024_1518_byte_packets; 558 uint32_t tx_1519_2047_byte_packets; 559 uint32_t tx_2048_4095_byte_packets; 560 uint32_t tx_4096_8191_byte_packets; 561 uint32_t tx_8192_9216_byte_packets; 562 uint32_t rx_fifo_overflow; 563 uint32_t rx_input_fifo_overflow; 564}; 565 566struct rx_stats { 567 /* dw 0-131 --2 X 66 */ 568 struct rx_port_stats port[2]; 569 /* dw 132-147 --16 */ 570 uint32_t rx_drops_no_pbuf; 571 uint32_t rx_drops_no_txpb; 572 uint32_t rx_drops_no_erx_descr; 573 uint32_t rx_drops_no_tpre_descr; 574 uint32_t management_rx_port_packets; 575 uint32_t management_rx_port_bytes; 576 uint32_t management_rx_port_pause_frames; 577 uint32_t management_rx_port_errors; 578 uint32_t management_tx_port_packets; 579 uint32_t management_tx_port_bytes; 580 uint32_t management_tx_port_pause; 581 uint32_t management_rx_port_rxfifo_overflow; 582 uint32_t rx_drops_too_many_frags; 583 uint32_t rx_drops_invalid_ring; 584 uint32_t forwarded_packets; 585 uint32_t rx_drops_mtu; 586 /* fcoe is not relevent */ 587 uint32_t rsvd[15]; 588}; 589 590struct tx_counter { 591 uint32_t pkts; 592 uint32_t lsd; 593 uint32_t msd; 594}; 595 596struct tx_stats { 597 struct tx_counter ct1pt0_xmt_ipv4_ctrs; 598 struct tx_counter ct1pt0_xmt_ipv6_ctrs; 599 struct tx_counter ct1pt0_rexmt_ipv4_ctrs; 600 struct tx_counter ct1pt0_rexmt_ipv6_ctrs; 601 struct tx_counter ct1pt1_xmt_ipv4_ctrs; 602 struct tx_counter ct1pt1_xmt_ipv6_ctrs; 603 struct tx_counter ct1pt1_rexmt_ipv4_ctrs; 604 struct tx_counter ct1pt1_rexmt_ipv6_ctrs; 605 struct tx_counter ct2pt0_xmt_ipv4_ctrs; 606 struct tx_counter ct2pt0_xmt_ipv6_ctrs; 607 struct tx_counter ct2pt0_rexmt_ipv4_ctrs; 608 struct tx_counter ct2pt0_rexmt_ipv6_ctrs; 609 struct tx_counter ct2pt1_xmt_ipv4_ctrs; 610 struct tx_counter ct2pt1_xmt_ipv6_ctrs; 611 struct tx_counter ct2pt1_rexmt_ipv4_ctrs; 612 struct tx_counter ct2pt1_rexmt_ipv6_ctrs; 613}; 614 615struct rx_err_stats { 616 uint32_t rx_drops_no_fragments[44]; 617 uint32_t debug_wdma_sent_hold; 618 uint32_t debug_wdma_pbfree_sent_hold; 619 uint32_t debug_wdma_zerobyte_pbfree_sent_hold; 620 uint32_t debug_pmem_pbuf_dealloc; 621}; 622 623struct mem_stats { 624 uint32_t eth_red_drops; 625 uint32_t lro_red_drops; 626 uint32_t ulp0_red_drops; 627 uint32_t ulp1_red_drops; 628}; 629 630/* [04] OPCODE_GET_NIC_STATS */ 631struct mbx_get_nic_stats { 632 /* dw0 - dw3 */ 633 struct mbx_hdr hdr; 634 union { 635 struct { 636 uint32_t rsvd0; 637 }req; 638 639 struct { 640 struct rx_stats rx; 641 struct tx_stats tx; 642 struct rx_err_stats err_rx; 643 struct mem_stats mem; 644 }rsp; 645 }params; 646}; 647 648/* [01] OPCODE_CONFIG_NIC_RSS */ 649struct mbx_config_nic_rss { 650 struct mbx_hdr hdr; 651 union { 652 struct { 653#ifdef _BIG_ENDIAN 654 uint32_t if_id; 655 uint16_t cpu_tbl_sz_log2; 656 uint16_t enable_rss; 657 uint32_t hash[10]; 658 uint8_t cputable[128]; 659 uint8_t rsvd[3]; 660 uint8_t flush; 661#else 662 uint32_t if_id; 663 uint16_t enable_rss; 664 uint16_t cpu_tbl_sz_log2; 665 uint32_t hash[10]; 666 uint8_t cputable[128]; 667 uint8_t flush; 668 uint8_t rsvd[3]; 669#endif 670 }req; 671 struct { 672 uint8_t rsvd[3]; 673 uint8_t rss_bank; 674 }rsp; 675 }params; 676}; 677 678#pragma pack() 679 680#ifdef __cplusplus 681} 682#endif 683 684#endif /* _OCE_HW_ETH_H_ */ 685